FREE patent keyword monitoring and additional FREE benefits. /images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
Fresh Patents freshpatentsnav7_icons (5K)
browse patent apps by agents browse patent apps by inventors browse patent apps by industry browse patents by location monitor patent applications
    



USPTO Class 365  |  Browse by Industry: Previous - Next | All     monitor keywords
01/2008 | Recent  |  08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 07: D | N | O | S | A | J | J | M | A | M | F | J |  | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov |  | 2010 | 2009 |

    SEARCH:      Monitor Keywords | rss Custom RSS

Static information storage and retrieval January USPTO class listing 01/08

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/31/2008 > patent applications in patent subcategories. USPTO class listing

20080025060 - Semiconductor device using magnetic domain wall moving: Provided is a semiconductor device that uses magnetic domain wall movement. The semiconductor device includes a magnetic wire having a plurality of magnetic domains, wherein the magnetic wire comprises a magnetic domain wall that is moved by either a pulse field or a pulse current. The magnetic wire of the... Agent: Sughrue Mion, PLLC

20080025061 - High bandwidth one time field-programmable memory: A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can... Agent: Vierra Magen/sandisk Corporation

20080025059 - Content addressable memory architecture: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20080025062 - Method for using a mixed-use memory array with different data states: A method for using a mixed-use memory array with different data states is disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states.... Agent: Brinks Hofer Gilson & Lione/sandisk

20080025064 - Ferroelectric memory device, method for driving ferroelectric memory device, electronic apparatus, and method for driving electronic apparatus: A ferroelectric memory device includes: an odd number of memory regions, the odd number being at least three or higher; a readout circuit that reads data of 0 or 1 stored in the odd number of memory regions; a comparison circuit that compares readout data at corresponding addresses of the... Agent: Harness, Dickey & Pierce, P.L.C

20080025063 - Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080025065 - Ferroelectric memory devices having expanded plate lines: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate... Agent: Myers Bigel Sibley & Sajovec

20080025069 - Mixed-use memory array with different data states: A mixed-use memory array with different data states is disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of... Agent: Brinks Hofer Gilson & Lione/sandisk

20080025072 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell including a variable resistance element changing its electric resistance by voltage application and having current-voltage characteristics in which a positive bias current flowing when a positive voltage is applied from one electrode as a reference electrode to the other electrode through... Agent: Nixon & Vanderhye, PC

20080025066 - Passive element memory array incorporating reversible polarity word line and bit line decoders: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025068 - Reverse bias trim operations in non-volatile memory: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a... Agent: Vierra Magen/sandisk Corporation

20080025070 - Semiconductor memory device: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory... Agent: Nixon & Vanderhye, PC

20080025067 - Systems for high bandwidth one time field-programmable memory: A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can... Agent: Vierra Magen/sandisk Corporation

20080025071 - Method for improving sensing margin of electrically programmable fuses: A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse... Agent: Cantor Colburn LLP - IBM Fishkill

20080025073 - Self-referenced match-line sense amplifier for content addressable memories: A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent... Agent: Greenblum & Bernstein, P.L.C

20080025074 - Self-referenced match-line sense amplifier for content addressable memories: A design structure for designing, manufacturing, or testing a content addressable memory (CAM) device. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation... Agent: Greenblum & Bernstein, P.L.C

20080025075 - Semiconductor integrated circuit: A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply voltage of the data holding circuit to the... Agent: Mcdermott Will & Emery LLP

20080025076 - Controlled pulse operations in non-volatile memory: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array... Agent: Vierra Magen/sandisk Corporation

20080025080 - Method and apparatus for programming phase change devices: Methods and apparatus for programming a phase change device (PCD) to a low resistance state. According to an exemplary method, one or more first programming pulses having a predetermined magnitude and/or duration are applied to a PCD. After each programming pulse is applied, the programmed resistance of the PCD is... Agent: Patent Law Professionals

20080025079 - Read disturb sensor for phase change memories: A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array... Agent: Dicke, Billig & Czaja

20080025077 - Systems for controlled pulse operations in non-volatile memory: A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array... Agent: Vierra Magen/sandisk Corporation

20080025078 - Systems for reverse bias trim operations in non-volatile memory: A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a... Agent: Vierra Magen/sandisk Corporation

20080025081 - Variable resistance memory device: A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit... Agent: Volentine & Whitt PLLC

20080025082 - Spin-current switchable magnetic memory element and method of fabricating the memory element: A spin-current switchable magnetic memory element (and method of fabricating the memory element) includes a plurality of magnetic layers having a perpendicular magnetic anisotropy component, at least one of the plurality of magnetic layers including an alloy of a rare-earth metal and a transition metal, and at least one barrier... Agent: Mcginn Intellectual Property Law Group, PLLC

20080025083 - Bipolar reading technique for a memory cell having an electrically floating body transistor: A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor. In this regard, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating... Agent: Neil Steinberg

20080025084 - High aspect ration bitline oxides: A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to... Agent: Empk & Shiloh, LLP

20080025085 - Memory array incorporating two data busses for memory array block selection: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025088 - Apparatus for reading a multi-level passive element memory cell array: A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current... Agent: Zagorin O'brien Graham LLP (023)

20080025089 - Method for reading a multi-level passive element memory cell array: A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current... Agent: Zagorin O'brien Graham LLP (023)

20080025090 - Page buffer and multi-state nonvolatile memory device including the same: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth... Agent: Volentine & Whitt PLLC

20080025091 - Non-volatile memory cells in a field programmable gate array: A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a... Agent: Sierra Patent Group, Ltd.

20080025092 - New cell structure with buried capacitor for soft error rate improvement: A semiconductor memory device with an improved protection against soft errors includes a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor electrically couples the data storage node to a predefined voltage and a second capacitor electrically couples the data bar storage... Agent: Tung & Associates

20080025095 - Flash memory device and program method thereof: A flash memory device and method of programming a flash memory device which include an array of memory cells arranged in rows and columns. A method includes programming memory cells of a selected row with loaded data; determining whether the memory cells of the selected row are successfully programmed; when... Agent: F. Chau & Associates, LLC

20080025093 - Hierarchical bit line bias bus for block selectable memory array: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025094 - Method for using a hierarchical bit line bias bus for block selectable memory array: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025096 - Nonvolatile memory devices and methods of fabricating the same: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes.... Agent: Harness, Dickey & Pierce, P.L.C

20080025098 - Method of programming a nonvolatile memory device using hybrid local boosting: A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The... Agent: Volentine & Whitt PLLC

20080025097 - Nand flash memory programming: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20080025099 - Non-volatile memory and control with improved partial page program capability: In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080025086 - Memory device and operating method thereof: A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The working voltage is a... Agent: J C Patents, Inc.

20080025100 - Flash memory device and multi-block erase method: In a flash memory device, a multi-block erase operation is performed by applying stepwise increasing erase voltages to selected memory blocks during a first erase period and then applying fixed erase voltages to the selected memory blocks during a second erase period. Once a selected memory block is successfully erased... Agent: Volentine & Whitt PLLC

20080025101 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080025102 - Method for memory data storage by partition into narrower threshold voltage distribution regions: A method for data storage of a memory unit and a memory unit using the same are provided in the present invention. The method for data storage of a memory unit includes: first, dividing a memory unit into a plurality of small memory groups; next, defining a threshold voltage distribution... Agent: J C Patents, Inc.

20080025103 - Accelerated single-ended sensing for a memory circuit: A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing... Agent: Ryan, Mason & Lewis, LLP

20080025104 - Method and apparatus for charging large capacitances: A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating... Agent: Dickstein Shapiro LLP

20080025105 - Nonvolatile ferroelectric memory device and refresh method thereof: A nonvolatile ferroelectric memory device is provided which includes a cell array including a plurality of nonvolatile memory cells each configured to read/write data, a refresh control unit configured to control a refresh operation in a given cycle in response to a refresh control signal for improving retention characteristics of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080025107 - Semiconductor device: A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a... Agent: Miles & Stockbridge PC

20080025106 - Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof: Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory... Agent: Harness, Dickey & Pierce, P.L.C

20080025087 - Method for fabricating charge-trapping memory: A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a... Agent: J C Patents, Inc.

20080025109 - Sram device and operating method: An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080025108 - System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal... Agent: Zilka-kotab, PC

20080025110 - Non-volatile semiconductor storage device: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object... Agent: Volentine & Whitt PLLC

20080025111 - Memory circuit using a reference for sensing: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality... Agent: Freescale Semiconductor, Inc. Law Department

20080025112 - Reduction in size of column sample and hold circuitry in a cmos imager: Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over the columns that the capacitors service.... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20080025113 - Semiconductor memory device: Disclosed herein is a semiconductor memory device including, a memory array with memory cells array-like arranged, a read bit line connected to a data output node of the memory cells and shared by a plurality of the memory cells arranged in one direction in the memory array, a write bit... Agent: Rader Fishman & Grauer PLLC

20080025114 - Balanced sense amplifier circuits: Structures and methods are disclosed for operating Balanced Sense Amplifier Circuits. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode... Agent: Schmeiser, Olsen & Watts

20080025115 - Method and system for testing semiconductor memory device using internal clock signal of semiconductor memory device as data strobe signal: Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe... Agent: Volentine & Whitt PLLC

20080025116 - System and method for capturing data signals using a data strobe signal: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080025117 - Semiconductor memory devices having variable additive latency: A semiconductor memory device includes an additive latency setting unit configured to receive a mode setting code from an external unit in response to the mode setting signal during a mode setting operation, set an additive latency value in response to the mode setting code, and receive the mode setting... Agent: Harness, Dickey & Pierce, P.L.C

20080025118 - Method for using a mixed-use memory array: A method for using a mixed-use memory array is disclosed. In one preferred embodiment, a memory array is provided comprising a first set of memory cells operating as one-time programmable memory cells and a second set of memory cells operating as rewritable memory cells. In another preferred embodiment, a memory... Agent: Brinks Hofer Gilson & Lione/sandisk

20080025119 - Accelerated searching for content-addressable memory: A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the... Agent: Ryan, Mason & Lewis, LLP

20080025120 - Temperature update masking to ensure correct measurement of temperature when references become unstable: Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature measurement is received. A determination is made of whether the clocked standby... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20080025121 - Method and apparatus for generating temperature-compensated read and verify operations in flash memories: Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature... Agent: Trask Britt, P.C./ Micron Technology

20080025122 - Memory refresh system and method: A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.... Agent: Zilka-kotab, PC

20080025123 - Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with... Agent: Zilka-kotab, PC

20080025125 - Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits... Agent: Zilka-kotab, PC

20080025124 - Interface circuit system and method for performing power management operations utilizing power management signals: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to... Agent: Zilka-kotab, PC

20080025126 - Data storage systems: A storage adapter for use in a data storage subsystem includes a controlling processor, a volatile memory, and a nonvolatile memory “dump device.” The storage adapter also includes a battery that can be used to provide sufficient power to the storage adapter to allow data from the volatile memory to... Agent: Dillon & Yudell, LLP

20080025127 - Semiconductor memory, controller, and operating method of semiconductor memory: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an... Agent: Arent Fox LLP

20080025128 - Memory system: A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating... Agent: Posz Law Group, PLC

20080025130 - Computer system having daisy chained self timed memory chips: A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080025129 - Daisy chained memory system: A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one... Agent: Robert R. Williams IBM Corporation

20080025131 - Dual data-dependent busses for coupling read/write circuits to a memory array: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025132 - Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025133 - Method for using dual data-dependent busses for coupling read/write circuits to a memory array: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025134 - Method for using two data busses for memory array block selection: Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array... Agent: Zagorin O'brien Graham LLP (023)

20080025135 - Antifuse circuit with well bias transistor: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate... Agent: Williams, Morgan & Amerson

20080025136 - System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation: A system and method are provided for use in the context of a plurality of memory circuits. In use, first information is received in association with a first operation to be performed on at least one of the memory circuits. At least a portion of the first information is stored.... Agent: Zilka-kotab, PC

20080025137 - System and method for simulating an aspect of a memory circuit: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one... Agent: Zilka-kotab, PC

  
01/24/2008 > patent applications in patent subcategories. USPTO class listing

20080019162 - Non-volatile semiconductor storage device: This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20080019163 - Method and memory circuit for operating a resistive memory cell: The invention relates to a method for reading a memory datum from a resistive memory cell comprising a selection transistor which is addressable via a control value, the method comprising detecting a cell current flowing through the resistive memory cell, setting the control value depending on the detected cell current,... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20080019164 - Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage: The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below... Agent: Vierra Magen/sandisk Corporation

20080019165 - Semiconductor capacitor, one time programmable memory cell and fabricating method and operating method thereof: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source... Agent: J C Patents, Inc.

20080019166 - Display substrate and display device having the same: A display substrate includes a base substrate having a display area displaying an image and a peripheral area surrounding the display area the base substrate including a plurality of gate lines comprising a first gate line group and a second gate line group, a first dispersion circuit part formed at... Agent: F. Chau & Associates, LLC

20080019167 - Controllable ovonic phase-change semiconductor memory device and methods of programming the same: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower... Agent: Trask Britt, P.C./ Micron Technology

20080019168 - Memory structure and data writing method thereof: A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need... Agent: Fulbright And Jaworski LLP

20080019169 - Active compensation for operating point drift in mram write operation: A method and apparatus for minimizing errors that may occur when writing information to a magnetic memory cell array with an operating write current due to changes in the local magnetic fields and. A test write current is sent to a reference memory cell and the effect of the test... Agent: Michael Buchenhorner, P.A.

20080019170 - Integrated circuit having memory having a step-like programming characteristic: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material has a step-like programming characteristic.... Agent: Dicke, Billig & Czaja

20080019171 - Dual port memory device with reduced coupling effect: A dual port SRAM cell includes at least one pair of cross-coupled inverters connected between a power line and complementary power line. A number of pass gate transistors connect the cross-coupled inverters to a first bit line, a first complementary bit line, a second bit line, and a second complementary... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080019172 - Gated diode nonvolatile memory cell array: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080019174 - Method for configuring compensation: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20080019173 - System for configuring compensation: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20080019175 - System that compensates for coupling based on sensing a neighbor using coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen Marcus & Deniro LLP

20080019177 - Data encoding approach for implementing robust non-volatile memories: Data encoding system and method for implementing robust non-volatile memories. A data bit is stored using two memory cells. The data bit is represented by setting a voltage level of a first memory cell to a first voltage level and setting a voltage level of a second memory cell to... Agent: Mcandrews Held & Malloy, Ltd

20080019176 - Nonvolatile semiconductor memory device for writing multivalued data: A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to... Agent: Mcdermott Will & Emery LLP

20080019178 - Electronic device including a memory array and conductive lines: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of... Agent: Larson Newman Abel Polansky & White, LLP

20080019180 - Selective program voltage ramp rates in non-volatile memory: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered... Agent: Vierra Magen/sandisk Corporation

20080019179 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080019181 - Multi-level operation in nitride storage memory cell: A method for programming a multi-level nitride storage memory cell capable of storing different programming states corresponding to multiple different threshold voltage levels includes providing a variable resistance capable of providing a plurality of different resistance values; connecting a drain side of the nitride storage memory cell to a selected... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080019183 - Method of programming flash memory device: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a... Agent: Myers Bigel Sibley & Sajovec

20080019182 - Semiconductor memory device and control method of the same: A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080019184 - Semiconductor memory device: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address... Agent: Mcdermott Will & Emery LLP

20080019185 - Compensating for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen Marcus & Deniro LLP

20080019187 - Memory device and method for verifying information stored in memory cells: A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The... Agent: Slater & Matsil LLP

20080019186 - System that compensates for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen/sandisk Corporation

20080019188 - Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells: Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080019189 - Method of high-performance flash memory data transfer: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data... Agent: Anderson, Levine & Lintel L.L.P.

20080019190 - Nonvolatile semiconductor memory: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080019191 - Nonvolatile memory and method of driving the same: The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh memory transistor. Further, according to the present invention, the period... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080019192 - Memory and multi-state sense amplifier thereof: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current... Agent: Birch Stewart Kolasch & Birch

20080019193 - Compensating for coupling based on sensing a neighbor using coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent: Vierra Magen Marcus & Deniro LLP

20080019194 - Semiconductor memory device: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080019195 - Non-volatile semiconductor memory device and semiconductor memory device: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block... Agent: Mcdermott Will & Emery LLP

20080019196 - High-performance flash memory data transfer: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data... Agent: Anderson, Levine & Lintel Fbo Sandisk Corporation

20080019197 - Read command triggered synchronization circuitry: A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting... Agent: Ropes & Gray LLP Patent Docketing 39/361

20080019198 - Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (amb) for repairing dram: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access... Agent: Stuart T Auvinen

20080019199 - Semiconductor memory and test method for the same: In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspondingly to each complementary sub bit... Agent: Mcdermott Will & Emery LLP

20080019200 - Integrated circuit chip with improved array stability: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g.,... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080019201 - Semiconductor memory device and control method thereof: A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference appearing on a bit line pair; a power supply line pair including first and second power supply lines for supplying... Agent: Sughrue Mion, PLLC

20080019202 - Memory array with a delayed wordline boost: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a... Agent: Texas Instruments Incorporated

20080019204 - Apparatus and method for supplying power in semiconductor device: Provided is directed to an apparatus and method of supplying power in a semiconductor memory device which supplies an external voltage of high level at the beginning operation which current consumption is rapidly increased and then supplies an internal voltage of a target level, but the external voltage is supplied... Agent: Marshall, Gerstein & Borun LLP

20080019206 - Integrated circuit having a memory with low voltage read/write operation: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells... Agent: Freescale Semiconductor, Inc. Law Department

20080019203 - Semiconductor device: A semiconductor device comprises a board; a semiconductor chip; a memory controller operative to control the semiconductor chip; and a power supply chip having a capacitor. The semiconductor chip is stacked on the board. The memory controller and the power supply chip are stacked on the semiconductor chip. The capacitor... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080019205 - Semiconductor device: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.... Agent: Miles & Stockbridge PC

20080019207 - Semiconductor memory device: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a... Agent: Young & Thompson

20080019208 - High density row ram for column parallel cmos image sensors: A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a single block of memory for storing signals processed by the ADCs. The ADCs process signals received from one group of columns of pixels and,... Agent: Dickstein Shapiro LLP

20080019209 - Access time adjusting circuit and method for non-volatile memory: An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance status of the non-volatile memory under an operation clock and output the performance status. An access time controlling... Agent: Jianq Chyun Intellectual Property Office

  
01/17/2008 > patent applications in patent subcategories. USPTO class listing

20080013359 - Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled... Agent: Neil Steinberg

20080013354 - Low cost high density rectifier matrix memory: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.... Agent: Goodwin Procter LLP Patent Administrator

20080013356 - Multi-bank memory: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.... Agent: Schwegman, Lundberg & Woessner, P.A.

20080013355 - Selective oxidation of silicon in diode, tft and monolithic three dimensional memory arrays: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell... Agent: Vierra Magen/sandisk Corporation

20080013358 - Non-volatile semiconductor memory device: A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are... Agent: Buchanan, Ingersoll & Rooney PC

20080013357 - Semiconductor memory device and arrangement method thereof: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged... Agent: Marger Johnson & Mccollom, P.C.

20080013360 - Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage: The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below... Agent: Vierra Magen/sandisk Corporation

20080013361 - Test method for ferroelectric memory: A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080013364 - Method of making non-volatile memory cell with embedded antifuse: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at... Agent: Foley And Lardner LLP Suite 500

20080013363 - Operation method of nonvolatile memory device induced by pulse voltage: A threshold switching operation method of a nonvolatile memory device may be provided. In the threshold switching operation method of a nonvolatile memory a pulse voltage may be supplied to a metal oxide layer of the nonvolatile memory device. Accordingly, it may be possible to operate the nonvolatile memory device... Agent: Harness, Dickey & Pierce, P.L.C

20080013362 - Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range; In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change... Agent: F. Chau & Associates, LLC

20080013365 - High efficiency portable archive: A high efficiency portable archive implements a storage system running on a virtualization layer to archive point-in-time versions of a raw data set and the storage system itself as a virtual system on archive media. The high efficiency portable archive can be implemented in a variety of computer architectures. The... Agent: Workman Nydegger

20080013367 - Compact and highly efficient dram cell: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a... Agent: Mcandrews Held & Malloy, Ltd

20080013366 - Device and method having a memory array storing each bit in multiple memory cells: A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row... Agent: Trask Britt, P.C./ Micron Technology

20080013368 - Semiconductor integrated circuit device: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between... Agent: Stanley P. Fisher Reed Smith LLP

20080013369 - Magnetic tunneling junction based logic circuits an methods of operating the same: MTJ cell based logic circuits and MTJ cell drivers having improved operating speeds compared to the conventional art, and operating methods thereof are described. An MTJ cell driver may include a lower electrode, an MTJ cell on the lower electrode, an upper electrode on the MTJ cell, and first through... Agent: Harness, Dickey & Pierce, P.L.C

20080013370 - Reading phase change memories to reduce read disturbs: Read disturbs in phase change memories may be reduced by progressively reducing the read pulse falling edges. This may reduce the possibility of quenching and inadvertent amorphization of at least a portion of the bit. As a result, in some embodiments, read disturbs may be reduced.... Agent: Trop Pruner & Hu, PC

20080013371 - Non-volatile semiconductor storage device: A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080013374 - Method for programming of multi-state non-volatile memory using smart verify: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate... Agent: Vierra Magen/sandisk Corporation

20080013373 - Methods of operating a non-volatile memory device: Example embodiments provide a method of operating a nonvolatile memory device in a multi-bit mode, which may operate at a low operating current and may be more integrated. In example embodiments, a first buried electrode may be used as a first bit line and a second buried electrode may be... Agent: Harness, Dickey & Pierce, P.L.C

20080013372 - Program control circuit of flash memory device having mlc and method thereof: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.... Agent: Marshall, Gerstein & Borun LLP

20080013375 - Memory system: A memory system includes a read only memory (ROM) which stores first data, a master control unit which generates a first address for the first data, a random access memory (RAM) which stores second data used to modify the first data, and a comparison unit which accesses the ROM and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080013376 - Memories, memory compiling systems and methods for the same: A method of compiling a memory for layout by computation includes inputting memory specification, determining a disposition structure of input/output pads with reference to the memory specification, and creating a layout of the memory in accordance with the determined disposition structure of the input/output pads. A memory includes a plurality... Agent: Harness, Dickey & Pierce, P.L.C

20080013377 - Non-volatile memory devices including dummy word lines and related structures and methods: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing... Agent: Myers Bigel Sibley & Sajovec

20080013378 - Method and circuit for electrically programming semiconductor memory cells: A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target programming state by the... Agent: Seed Intellectual Property Law Group PLLC

20080013379 - Method and apparatus for reading data from nonvolatile memory: Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080013381 - Sense amplifier with reduced area occupation for semiconductor memories: A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of... Agent: Graybeal Jackson Haley LLP Suite. 350

20080013380 - Shifting reference values to account for voltage sag: A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is... Agent: Fish & Richardson P.C.

20080013382 - Current sensing for flash: A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing process that places a current source to provide current to the bit line. The voltage level of the bit line is then set by the current... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20080013384 - Concurrent programming and program verification of floating gate transistor: A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to... Agent: Larson Newman Abel Polansky & White, LLP

20080013383 - Modular design of multiport memory bitcells: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read... Agent: Lsi Corporation

20080013385 - Asynchronous semiconductor memory: An asynchronous pseudo SRAM having compatibility with asynchronous SRAMs. A read request or a write request of data is provided at arbitrary timing to the asynchronous pseudo SRAM, the asynchronous pseudo SRAM includes a memory cell array comprising dynamic memory cells; an array control circuit that is activated in response... Agent: International Business Machines Corporation Intellectual Property Law

20080013386 - Method, system and related synchronizer for controlling data synchronization in fifo memories: A system for detecting during write/read operations the status of a FIFO memory having N memory locations includes a first and a second Gray-code counter each configured to take values out of 2*N possible values. The first and second Gray-code counters are configured to be initialized to a value J,... Agent: Hogan & Hartson LLP

20080013387 - Automatic regulation method for the reference sources in a non-volatile memory device and corresponding memory device: A method and a relative automatic regulation device regulate the reference sources in a non-volatile memory device, for example a flash memory. The method includes the following steps: providing, in the memory device, a regulation device of the reference sources and at least one start command for the entry in... Agent: Seed Intellectual Property Law Group PLLC

20080013388 - Method and apparatus for wordline redundancy control of memory in an information handling system: A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of... Agent: Mark P. Kahler

20080013390 - Memory array architecture and method for high-speed distribution measurements: A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained therefrom. Based upon the measured response, a... Agent: Slater & Matsil LLP

20080013389 - Random access memory including test circuit: A random access memory including input pads and a test circuit. The input pads are configured to receive a row address and a column address. The test circuit is configured to receive the row address and the column address via the input pads and to receive mask bits. The test... Agent: Dicke, Billig & Czaja

20080013391 - Random access memory that selectively provides data to amplifiers: A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. The first circuit is... Agent: Dicke, Billig & Czaja

20080013392 - Semiconductor memory device: An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the... Agent: Sughrue Mion, PLLC

20080013393 - Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal... Agent: Hewlett Packard Company

20080013396 - Memory card having multiple interfaces and reset control method thereof: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function... Agent: Lee & Morse, P.C.

20080013394 - Power control circuit: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second terminal coupled to the node... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20080013395 - Memory device with control circuit for regulating power supply voltage: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the... Agent: Ibm Corporation

20080013397 - Semiconductor memory device and arrangement method thereof: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged... Agent: Marger Johnson & Mccollom, P.C.

20080013398 - Dual-addressed rectifier storage device: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed... Agent: Goodwin Procter LLP Patent Administrator

  
01/10/2008 > patent applications in patent subcategories. USPTO class listing

20080007986 - One-time programmable devices including chalcogenide material, electronic systems including the same and methods of operating the same: A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching... Agent: Myers Bigel Sibley & Sajovec

20080007985 - Antifuse circuit with well bias transistor: An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor is coupled to the terminal and includes a first gate terminal coupled to receive a first select signal. The bias transistor is coupled between the substrate... Agent: Williams, Morgan & Amerson

20080007987 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080007988 - Non-volatile memory device including variable resistance material and method of fabricating the same: Provided is a non-volatile memory device including a variable resistance material and method of fabricating the same. The non-volatile memory device may include a lower electrode, an intermediate layer on the lower electrode including one material selected from the group consisting of HfO, ZnO, InZnO, and ITO, a variable resistance... Agent: Harness, Dickey & Pierce, P.L.C

20080007989 - Programming methods to increase window for reverse write 3d cell: A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the... Agent: Foley And Lardner LLP Suite 500

20080007992 - Multi-state sense amplifier: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a... Agent: Birch Stewart Kolasch & Birch

20080007990 - Scalable magnetic random access memory device: Techniques for data storage are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free... Agent: Michael J. Chang, LLC

20080007993 - Semiconductor memory device: A semiconductor memory device comprises writing means for performing a first writing action for shifting an electric resistance of a variable resistance element from a first state to a second state by applying a first voltage between both ends of a memory cell and a gate potential to a gate... Agent: Morrison & Foerster LLP

20080007991 - Reversed magnetic tunneling junction for power efficient byte writing of mram: A magnetoresistive memory device comprises magnetoresistive cells, each cell comprising a free magnetic layer and a fixed magnetic layer. The device furthermore comprises a bit line for each magnetoresistive cell and digit lines. Each digit line is common to a number of magnetoresistive cells and is positioned in a direction... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080007994 - Synthetic anti-ferromagnetic structure with non-magnetic spacer for mram applications: A toggle MTJ cell is disclosed that has a nearly balanced SAF free layer with two major sub-layers separated by an anti-parallel coupling layer. Within each major sub-layer, there is a plurality of minor sub-layers wherein adjacent minor sub-layers are separated by a parallel coupling layer. The parallel coupling layer... Agent: Saile Ackerman LLC

20080007995 - Memory cell having a switching active material, and corresponding memory device: A memory device having at least one resistively switching memory cell is disclosed. In one embodiment, the memory cell includes a volume of switching active material and a pair of electrodes being galvanically coupled to the volume of switching active material, wherein the pair of electrodes is adapted to send... Agent: Dicke, Billig & Czaja

20080007996 - Magnetic storage device: A magnetic storage device comprises an array of magnetic memory cells (50). Each cell (50) has, in electrical series connection, a magnetic tunnel junction (MTJ) (30) and a Zener diode (40). The MTJ (30) comprises, in sequence, a fixed ferromagnetic layer (FMF) (32), a non-magnetic spacer layer (33), a tunnel... Agent: Miles & Stockbridge PC

20080007997 - Pmc memory with improved retention time and writing speed: The invention concerns a PMC memory comprising a memory cell (4, 6, 8, 10) and means (16, 18, 20) for heating the cell when being written into the memory.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080007998 - Single-poly eeprom cell and method for formign the same: A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method comprises providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of... Agent: J.c. Patents, Inc. Suite 250

20080007999 - Nonvolatile memory device with nand cell strings: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating... Agent: Volentine & Whitt PLLC

20080008000 - Reverse coupling effect with timing information: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20080008001 - Semiconductor device and boot method for the same: A semiconductor device is designed to provide an access control for a memory that includes a plurality of storage regions storing the same boot programs comprised of a set of program data. The semiconductor device is provided with a memory controller for reading out the program data from the storage... Agent: Young & Thompson

20080008003 - Non-volatile memory device: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is... Agent: Mills & Onello LLP

20080008002 - Electronic device comprising non volatile memory cells with optimized programming and corresponding programming method: A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local bit-lines and respectively enabled by a first... Agent: Bryan A. Santanelli

20080008004 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080008005 - Operation methods for a non-volatile memory cell in an array: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20080008006 - Programming method for nand eeprom: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one... Agent: Leffert Jay & Polglaze, P.A.

20080008007 - Semiconductor memory device, and read method and read circuit for the same: In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation. The reset state of a bit line is canceled when selected and connected to a read... Agent: Mcdermott Will & Emery LLP

20080008008 - Methods for programming and reading nand flash memory device and page buffer performing the same: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells... Agent: Oliff & Berridge, PLC

20080008009 - Nonvolatile memory system, semiconductor memory, and writing method: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080008010 - High bandwidth datapath load and test of multi-level memory cells: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The... Agent: Trop Pruner & Hu, PC

20080008011 - Circuit and method of controlling input/output sense amplifier of a semiconductor memory device: An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having... Agent: Mills & Onello LLP

20080008012 - Implementation of a fusing scheme to allow internal voltage trimming: Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20080008013 - Semiconductor device having a sense amplifier: A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080008014 - Semiconductor memory device: A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that changes a gate-source voltage of the overdrive transistor step by step.... Agent: Young & Thompson

20080008015 - Architecture, system and method for compressing repair data in an integrated circuit (ic) design: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored... Agent: Shreen K. Danamraj, Esq. Danamraj & Youst, P.C.

20080008016 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively,... Agent: Scully Scott Murphy & Presser, PC

20080008017 - High-performance memory and related method: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging... Agent: North America Intellectual Property Corporation

20080008018 - Low voltage operation dram control circuits: Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drain transistors coupled to the sense or restore signals and driven by gate... Agent: John P. O'banion O'banion & Ritchey LLP

20080008019 - High speed read-only memory: A high speed read-only memory (ROM). Data stored in a memory cell in the ROM array is provided to a sense amplifier in a differential form. Two transistors storing complementary logic states form a memory cell and store a data bit. One transistor has a source terminal connected to a... Agent: Texas Instruments Incorporated

20080008020 - Memory device with programmable control for activation of read amplifiers: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane,... Agent: Graybeal Jackson Haley LLP

20080008021 - Method for recognizing and verifying fifo structures in integrated circuit designs: First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural analysis includes performing seed based recognition by identifying logic elements that indicate the existence of candidate FIFO circuitry and then exploring the candidate circuitry... Agent: Sughrue Mion, PLLC

20080008022 - Semiconductor memory device and operating method: A semiconductor memory device and its operating method are disclosed. The semiconductor memory device includes; a memory cell array including a plurality of memory cells selected in relation to a plurality of word lines and a plurality of bit lines, an address decoder selecting at least one word line in... Agent: Volentine & Whitt PLLC

20080008023 - Memory device, and method for operating a memory device: A memory device, in particular to a DRAM, and a system comprising a memory device is disclosed. Further, the invention relates to a method for operating a memory device. According to an embodiment of the invention, a memory device is provided, including: a first chip select pin, and a second... Agent: Dicke, Billig & Czaja

20080008024 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks #0 to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two... Agent: Sughrue Mion, PLLC

Previous industry: Electric power conversion systems
Next industry: Agitating


######

RSS FEED for 20140410: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.



Results in 1.17581 seconds

PATENT INFO