Static information storage and retrieval inventions 12/07

20070297207 - Methods and apparatus for content addressable memory arrays including shared match lines: Embodiments of the present invention provide content addressable memory (CAM) arrays that include shared match lines. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070297208 - Semiconductor memory device: A semiconductor memory device includes a plurality of sense amplifiers each supplying a higher write potential and a lower write potential to each of memory cells; a driver circuit supplying the higher write potential to each of the sense amplifiers; a driver circuit supplying the lower write potential to each... Agent: Sughrue Mion, PLLC

20070297209 - System and method for adjusting offset compensation applied to a signal: In one embodiment of the present invention, a method for adjusting a signal includes receiving an input data signal. The method also includes applying an offset compensation to the input data signal to generate an output signal. The method further includes, using a clock signal, sampling the output signal to... Agent: Baker Botts L.L.P.

20070297210 - Semiconductor memory device and writing method thereof: A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the power supply circuit and the write line, and a first register which connects to the write line, receives a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297211 - Holographic data support and method for production thereof: The invention relates to a data support (1) with a core layer (15) and at least one adjacent layer (14a), laminated to the core layer and a corresponding production method, said core layer being embodied from a holographic data store in the form of a volume hologram (5). The surface... Agent: Darby & Darby P.C.

20070297212 - Reducing the effect of write disturbs in polymer memories: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may... Agent: Timothy N. Trop Trop, Pruner & Hu, P.C.

20070297213 - Forming a carbon layer between phase change layers of a phase change memory: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized... Agent: Trop Pruner & Hu, PC

20070297214 - Semiconductor device: To provide a semiconductor device in which power consumption at the time of an anti-collision operation is reduced. A semiconductor device includes an arithmetic circuit, a storage device, and circuits for transmitting and receiving signals to and from the outside. The arithmetic circuit includes a central processing unit and a... Agent: Eric Robinson

20070297215 - Semiconductor memory device and method of operating the semiconductor memory device: A pair of memory nodes, a capacitor of which one end is connected to the memory nodes, and a switch part which is connected to the other end of the capacitor, and changes a connection state of the other end of the capacitor when a semiconductor memory device operates at... Agent: Mcginn Intellectual Property Law Group, PLLC

20070297216 - Self-assembly of molecular devices: A method for selectively assembling a molecular device on a substrate comprises contacting the first substrate with a solution containing molecular devices; impeding bonding of the molecular devices to the substrate such that application of a voltage potential to the substrate results in assembly of the molecular device on the... Agent: Winstead PC

20070297217 - Method and circuit arrangement for operating a volatile random access memory as a detector: A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random access memory. The method includes interrupting a supply voltage for the at least one area of the random access memory during a time period,... Agent: Dickstein Shapiro LLP

20070297220 - Magnetoresistive element and magnetic memory: A magnetoresistive includes a first magnetic reference layer having a fixed magnetization direction, a magnetic free layer having a magnetization direction which is changeable by being supplied with spin polarized electrons, a second magnetic reference layer having a fixed magnetization direction, a first intermediate layer provided between the first magnetic... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297219 - Magnetoresistive memory cell, methods of programming a magnetoresistive memory cell and methods of reading a magnetoresistive memory cell: A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external... Agent: Slater & Matsil LLP

20070297218 - Magnetic tunnel junction with enhanced magnetic switching characteristics: A semiconductor device formed between a wordline and a bitline comprises a growth layer, an antiferromagnetic layer formed on the growth layer, a pinned layer formed on the antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, and a free layer formed on the tunnel barrier. The wordline... Agent: Ryan, Mason & Lewis, LLP

20070297221 - Memory cell programmed using a temperature controlled set pulse: A memory device includes a phase change memory cell and a circuit. The circuit is for programming the memory cell to a selected one of more than two states by applying a temperature controlled set pulse to the memory cell.... Agent: Dicke, Billig & Czaja

20070297222 - Mram cell using multiple axes magnetization and method of operation: A magnetic random access memory cell includes a free layer structure and a reference layer structure including an anti-ferromagnetic layer structure pinning the magnetization orientation of the reference layer structure, the reference layer structure having a higher magnetic coercivity and being magnetically polarizable bidirectional and parallel to more than one... Agent: Slater & Matsil LLP

20070297223 - Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins: A method and system for providing a magnetic memory is described. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each... Agent: Strategic Patent Group, P.C.

20070297225 - High voltage switching circuit: A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and, an enhancement mode NMOS transistor. A control circuit generates first and second control signals. A first control signal controls the enhancement mode NMOS transistor and a logical combination of both control signals... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070297227 - Multi-level cell memory structures with enlarged second bit operation window: Multi-level cell memory devices comprise a charge trapping structure with an enlarged second bit operation window formed by hole injection through a gate electrode or substrate for producing multiple logic levels on each storage side of the charge trapping structure. A hole injection process is conducted through either a gate... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070297229 - Flash memory device including multi-buffer block: A flash memory device comprises a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits... Agent: Volentine & Whitt PLLC

20070297228 - Nonvolatile memory device: A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070297230 - Non-volatile memory structure: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line... Agent: Rosenberg, Klein & Lee

20070297224 - Mos based nonvolatile memory cell and method of operating the same: A non-volatile memory cell formed on a sidewall of MOS transistor and method of operating the same are disclosed. The MOS based non-volatile memory cell is formed in the n-well and compatible with CMOS processes comprising a selecting gate, two ONO spacers, a p+ source/drain, and a p extended source... Agent: Jianq Chyun Intellectual Property Office

20070297231 - Non-volatile memory structure: A nonvolatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead of storing or removing electrons from a floating gate, the programmable conductor is switched between its low and high resistive states to operate the flash memory cell.... Agent: Dickstein Shapiro LLP

20070297232 - Nonvolatile semiconductor memory: According to one embodiment, a nonvolatile semiconductor memory comprising: a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297233 - Nand flash memory and data programming method thereof: A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297234 - Non-volatile memory and method with bit line to bit line coupled compensation: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070297226 - Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages: A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at... Agent: Vierra Magen/sandisk Corporation

20070297237 - Memory control circuit, microcomputer, and data rewriting method: A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that is read from a memory address where the write data is written; a comparison result storage unit storing a... Agent: Foley And Lardner LLP Suite 500

20070297235 - Method of forming a programmable voltage regulator and structure therefor: In one embodiment, a programmable voltage regulator stores data representing a programmable configuration of the regulator. The regulator is configured to verify the validity of the stored data before using it to control the operation of the programmable voltage regulator.... Agent: Bradley J. Botsch Semiconductor Components Industries, LLC

20070297236 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a collective processing unit; and a data state judgment circuit configured... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297238 - Voltage regulator for flash memory device: Provided is a voltage regulator of a flash memory device. Embodiments of the invention provide a voltage regulator that is configured to regulate either an internal pumping voltage or an external high voltage. In embodiments of the invention, the voltage regulator includes two switches having different switching current characteristics: when... Agent: Volentine & Whitt PLLC

20070297239 - Memory device with a nonvolatile memory array: A memory device having a nonvolatile memory array, at least one driver for programming the memory array, which driver is connected to the memory array in order to drive a programming potential, and a drive circuit for controlling the at least one driver, wherein the drive circuit has at least... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070297240 - Methods and structures for expanding a memory operation window and reducing a second bit effect: Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070297241 - Method and structure for operating memory devices on fringes of control gate: Charge trapping memory devices and methods are described for increasing a second bit operation window by a fringe-induced effect. The fringe-induced effect occurs in areas underneath a word line so that when a hole injection method is applied to a memory device, hole charges are stored in a charge trapping... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070297242 - Negative potential discharge circuit and method thereof: A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated... Agent: Harness, Dickey & Pierce, P.L.C

20070297243 - Memory structures for expanding a second bit operation window: Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070297245 - System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages: A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at... Agent: Vierra Magen/sandisk Corporation

20070297244 - Top dielectric structures in memory devices and methods for expanding a second bit operation window: Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070297246 - Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased... Agent: Macpherson Kwok Chen & Heid LLP

20070297247 - Method for programming non-volatile memory using variable amplitude programming pulses: Non-volatile storage elements are programmed using a series of voltage waveforms, where each waveform includes different portions with different amplitudes. For example, the amplitudes can vary as a decreasing staircase or ramp. Storage elements which are to be programmed to the highest level are programmed using the entire waveform, while... Agent: Vierra Magen/sandisk Corporation

20070297248 - System and method for adjusting compensation applied to a signal using filter patterns: In one embodiment of the present invention, a method for adjusting a signal includes applying at least one of a loss compensation for frequency-dependent distortion and an offset compensation for DC-offset distortion to a data signal before or after the distortion occurs to generate an output signal, the data signal... Agent: Baker Botts L.L.P.

20070297249 - Low-power sram memory cell: An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective... Agent: The Webb Law Firm, P.C.

20070297250 - Data processing apparatus and method using fifo device: In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal... Agent: Mills & Onello LLP

20070297252 - Integrated circuit having memory array including ecc and/or column redundancy, and method of programming, controlling and/or operating same: An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry... Agent: Neil Steinberg

20070297251 - Semiconductor memory device having memory block configuration: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the... Agent: Mcdermott Will & Emery LLP

20070297254 - Method to identify or screen vmin drift on memory cells during burn-in or operation: A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (Vt) of said transistor to change. The... Agent: Texas Instruments Incorporated

20070297255 - Semiconductor memory tester: There is implemented a semiconductor memory tester capable of efficiently conducting a test on a fast memory by programming according to parameters of a device without being attended by complex program handling. The semiconductor memory tester for determining pass/fail on a memory device under test is characterized in comprising a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070297253 - Measuring circuit for qualifying a memory located on a semiconductor device: A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070297256 - Systems and methods for data transfers between memory cells: Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier... Agent: Law Offices Of Mark L. Berrier

20070297257 - Semiconductor memory device capable of canceling out noise development: A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20070297260 - Controlling execution of additional function during a refresh operation in a semiconductor memory device: A semiconductor memory device includes a mode register, an additional function executer, and an additional function controller. The mode register activates an additional function control signal when a mode register set code indicates that an additional function is to be executed concurrently with a refresh operation. The additional function controller... Agent: Law Office Of Monica H Choi

20070297259 - Memory: A memory includes an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation, a refresh division control portion dividing the refresh operation into a read operation and a rewrite operation and an address determination portion... Agent: Ditthavong Mori & Steiner, P.C.

20070297258 - Semiconductor memory device and self-refresh method therefor: A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070297261 - Apparatus and method of generating power up signal of semiconductor integrated circuit: An apparatus for generating a power up signal for a semiconductor memory chip includes a temperature information providing unit that outputs a control voltage corresponding to predetermined temperature information. A power up signal generating unit generates the power up signal based at least on one of an external voltage or... Agent: Venable LLP

20070297262 - Semiconductor memory device having stacked gate including charge accumulation layer and control gate and test method thereof: A semiconductor memory device includes a memory cell, a word line, a bit line, a column gate, and a power supply decode circuit. The memory cell has a first MOS transistor including a charge accumulation layer and a control gate. The bit line is connected to a drain of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070297263 - Semiconductor memory device capable of controlling potential level of power supply line and/or ground line: Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control... Agent: Mcdermott Will & Emery LLP

20070297264 - Memory cell access circuit: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors.... Agent: Downs Rachlin Martin PLLC

20070297265 - Nonvolatile memory, apparatus and method for determining data validity of the same: A nonvolatile memory including a memory cell that stores data in a plurality of pages included in a block according to a voltage applied to a memory cell is provided. The nonvolatile memory includes a block that includes a first page including first data that stores data recorded by a... Agent: Sughrue Mion, PLLC

20070297266 - Synchronous global controller for enhanced pipelining: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to... Agent: Mcandrews Held & Malloy, Ltd

20070297267 - Portable electronic device and coupling device for the same: Disclosed is a coupling device for coupling first and second units with each other in a portable apparatus having the first and second units and a rotation axis. The device included a first coupling member having a rotational coupling portion connected to the first unit so that the rotational coupling... Agent: Knobbe Martens Olson & Bear LLP

20070297268 - Random access memory including multiple state machines: A random access memory including multiple state machines and selection circuitry. The multiple state machines include a first state machine and a second state machine, and possibly more state machines. The first state machine is configured to provide first signals to control the random access memory and provide first command... Agent: Dicke, Billig & Czaja

20070297269 - Memory and control unit: A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an... Agent: Ditthavong Mori & Steiner, P.C.

20070297270 - Semiconductor integrated circuit device: The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port... Agent: Miles & Stockbridge PC

20070291524 - Nanoscale content-addressable memory: A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and configurable switches between the key nanowires and the value nanowires. The combination... Agent: Akerman Senterfitt

20070291525 - Memory card connector: A compact memory card connector with an extended communication distance is provided. This connector has a loading port at its one end, through which a memory card can be accommodated therein. The connector is equipped with a base made of an electrical insulating material, a plurality of contacts arranged on... Agent: Kratz, Quintos & Hanson, LLP

20070291526 - Structure for a non-volatile memory device: System for a memory device. An electronic device includes a non-volatile memory array. The non-volatile memory array includes a first transistor and a second transistor. The first and second transistors have a shared doped region. A first word line is formed along a first axis. The first word line includes... Agent: Slater & Matsil, L.L.P.

20070291527 - Memory apparatus: A memory apparatus is provided that includes a storage element configured to store and retain information based on the state of an electric resistance, and a circuit element connected in series to the storage element as a load. In the memory apparatus, a resistance value is set to one of... Agent: Bell, Boyd & Lloyd LLP

20070291528 - Method and apparatus for improving sram cell stability by using boosted word lines: The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′)... Agent: Scully Scott Murphy & Presser, PC

20070291529 - Semiconductor memory device: According to some preferred embodiments of the present invention, a semiconductor memory device includes an array of memory cells and plural pairs of complementary bit lines, each pair of the complementary bit lines being connected to the memory cells arranged in the same column. The array is divided into plural... Agent: Watchstone P+d, PLC

20070291531 - Mram with a write driver and a method therefor: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell.... Agent: Freescale Semiconductor, Inc. Law Department

20070291532 - Semiconductor integrated circuit device and magnetic memory device capable of maintaining data integrity: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is... Agent: Buchanan, Ingersoll & Rooney PC

20070291530 - Separate write and read access architecture for a magnetic tunnel junction: A magnetoresistive device is provided with separate read and write architecture. In one embodiment, a magnetic tunnel junction (MTJ) has a nonmagnetic nonconductive barrier layer sandwiched between two ferromagnetic conducting layers. A first read line having a first resistance is coupled to a first ferromagnetic layer and a second read... Agent: Honeywell International Inc.

20070291533 - Phase change memory device and fabrication method thereof: The invention provides a phase change memory device comprising a stacked structure disposed on a substrate. The stacked structure comprises a first electrode, a second electrode overlying the first electrode and an insulating layer interposed between the first and the second electrodes. A memory spacer is formed on part of... Agent: Quintero Law Office, PC

20070291534 - An electronic communication device with a dynamic multifunctional module: The invention relates to a dynamic multifunctional module and to an electronic communication device comprising a main body part, a sliding body part, said parts being connected together with sliding contact, and a dynamic multifunctional module, the dynamic multifunctional module being joint from one edge to the main body part... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070291535 - Multi-chip switch based on proximity communication: A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070291538 - Clock synchronized non-volatile memory device: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070291537 - Microprocessor boot-up controller, nonvolatile memory controller, and information processing system: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070291539 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070291540 - Microprocessor boot-up controller, nonvolatile memory controller, and information processing system: A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070291541 - An apparatus and associated method for making a virtual ground array structure that uses inversion bit lines: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.... Agent: Baker & Mckenzie LLP Patent Department

20070291542 - Programming method for nand flash: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells utilizing a drain-side self boost, modified drain-side self boost or local self boost process that increases the pass voltage (Vpass_high) on a word line on the source line... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20070291543 - Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines: Non-volatile storage elements are programmed using counter-transitioning waveform portions on neighboring word lines which reduce capacitive coupling to a selected word line. In one approach, the waveform portions extend between pass or isolation voltages of a boosting mode, which are applied during a programming pulse on the selected word line,... Agent: Vierra Magen/sandisk Corporation

20070291544 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device in accordance with the present invention is provided with a plurality of memory cells of field effect transistor type, a source bias control circuit, and a drain bias control circuit. The source bias control circuit variably sets the potential of a source line connected in... Agent: Mcginn Intellectual Property Law Group, PLLC

20070291536 - Non-volatile memory device and method thereof: A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line... Agent: Harness, Dickey & Pierce, P.L.C

20070291545 - System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines: Non-volatile storage elements are programmed using counter-transitioning waveform portions on neighboring word lines which reduce capacitive coupling to a selected word line. In one approach, the waveform portions extend between pass or isolation voltages of a boosting mode, which are applied during a programming pulse on the selected word line,... Agent: Vierra Magen/sandisk Corporation

20070291546 - Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory: Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may... Agent: Vierra Magen/sandisk Corporation

20070291547 - Charge pump operation in a non-volatile memory device: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070291548 - Programming and erasing method for charge-trapping memory devices: A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to... Agent: Martine Penilla & Gencarella, LLP

20070291549 - Nonvolatile semiconductor storage apparatus and readout method: A semiconductor storage apparatus includes a plurality of data cells arranged in rows and columns. The data cells have MOS transistors having different types of operating characteristics to store data according to the types of the MOS transistors. Bit lines extend to the respective columns of data cells. The stored... Agent: Nixon Peabody, LLP

20070291550 - Method and apparatus for high voltage operation for a high performance semiconductor memory device: For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference... Agent: Ingrassia Fisher & Lorenz, P.C.

20070291551 - Nonvolatitle memory array and method for operating thereof: A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is... Agent: J C Patents, Inc.

20070291552 - Runtime flash device detection and configuration for flash data management software: A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally re-configurable to match the driving and management requirements of the particular memory device. This allows for a limited number of operating system versions to be produced and maintained... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070291553 - Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same: A data output circuit for an integrated circuit memory device includes a control circuit that is configured to generate a plurality of clock signals responsive to at least a portion of a memory column address, and a multiplexer circuit that is configured to output memory data received on input terminals... Agent: Myers Bigel Sibley & Sajovec

20070291554 - Memory with clock-controlled memory access and method of operating the same: An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data... Agent: Edell, Shapiro & Finnan, LLC

20070291555 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system... Agent: Mcdermott Will & Emery LLP

20070291556 - Programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory: Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may... Agent: Vierra Magen/sandisk Corporation

20070291557 - Stacked semiconductor device: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle,... Agent: Sughrue Mion, PLLC

20070291558 - Data strobe signal generator for generating data strobe signal based on adjustable preamble value and semiconductor memory device with the same: A data strobe signal generator according to the present invention includes a control unit, a pulse delay unit, a clock generator, and a data strobe output unit. The control unit generates a CAS latency signal and a preamble signal. The pulse delay unit delays a pulse signal for predetermined time... Agent: Lowe Hauptman Ham & Berner, LLP

20070291559 - Semiconductor device with delay section: In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the... Agent: Young & Thompson

20070291560 - Method and system for improving reliability of memory device: A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070291561 - Sense-amplifier assist (saa) with power-reduction technique: The present invention provides an apparatus and method to reduce the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring Sense Amplifier Assist (SAA) circuitry. In particular, the present invention is an apparatus and method that limits the implementation of the SAA circuitry... Agent: Connolly Bove Lodge & Hutz LLP (ibm Microelectronics Division)

20070291562 - Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070291563 - Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information: A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method... Agent: Brinks Hofer Gilson & Lione/sandisk

20070291564 - Semiconductor device: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large... Agent: Miles & Stockbridge PC

20070291565 - Architecture and method for nand flash memory: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20070291566 - Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen/sandisk Corporation

20070291567 - System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen/sandisk Corporation

20070291568 - Apparatus and method for controlling refresh operation of semiconductor integrated circuit: A semiconductor memory integrated circuit for controlling a refresh operation includes: a first period generating unit that generates a first periodic signal having an uniformed period; a second period generating unit that generates a second periodic signal according to a first control signal; a period generation control unit that generates... Agent: Venable LLP

20070291569 - Non-volatile storage apparatus and a control method thereof: Storage apparatus can support various memory units with different standards based on the method which drives the power control-and-switch circuit in the power management unit according to a control signal caused by the ID code of a memory unit to control the second booster for further increasing the level of... Agent: Rosenberg, Klein & Lee

20070291571 - Increasing the battery life of a mobile computing system in a reduced power state through memory compression: Embodiments of the invention are generally directed to systems, methods, and apparatuses for increasing the battery life of a mobile computing system through memory compression. In some embodiments, an integrated circuit includes compression logic to compress at least a portion of the data in volatile memory independent of an operating... Agent: Intel Corporation C/o Intellevate, LLC

20070291570 - Method and apparatus for managing behavior of memory devices: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed... Agent: Dickstein Shapiro LLP

20070291572 - Clock circuit for semiconductor memory: A memory component includes at least one memory bank array, a first and a second region, a clock tree, and a clock control circuit. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it... Agent: Dicke, Billig & Czaja

20070291573 - Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same: An apparatus includes a control unit for generating an input control signal to select a global input/output line to which data is transmitted. A repeater receives data from the global input/output line to output the data to a global input/output line corresponding to the input control signal. A plurality of... Agent: Venable LLP

20070291574 - Method for manufacturing electro-optical device and electro-optical device: A method for manufacturing an electro-optical device which has first and second electrodes, an electro-optical layer interposed between the first and second electrodes and a plurality of pixel regions arranged in a plane, and performs display by transmitting light through each of colored layers provided correspondingly to each of the... Agent: Workman Nydegger

20070291575 - Integrated circuit memory devices that support selective mode register set commands and related methods: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address... Agent: Myers Bigel Sibley & Sajovec

20070291576 - Address latch circuit of semiconductor memory device: An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second... Agent: Ladas & Parry LLP

20070291577 - System with controller and memory: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... Agent: Sughrue Mion, PLLC

20070285957 - Magnetic shielding for magnetic random access memory: A memory assembly comprises a substrate that incorporates magnetic shielding, a magnetic random access memory die supported by the substrate, and an encapsulation matrix that includes magnetic shielding that is disposed over the magnetic random access memory die.... Agent: Myers Bigel Sibley & Sajovec

20070285958 - Methods of creating a dictionary for data compression: Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the... Agent: Sughrue Mion PLLC Uspto Customer No With Ibm/svl

20070285959 - Memory element and semiconductor device: The memory element includes a first conductive layer, a second conductive layer, a layer containing a compound which can exhibit liquid crystallinity which is interposed between the first conductive layer and the second conductive layer, and a layer containing an organic compound which is interposed between the first conductive layer... Agent: Eric Robinson

20070285962 - Phase change memory device and fabrication method thereof: A phase change memory device is disclosed. A first columnar electrode and a second columnar electrode are provided, both arranged horizontally. A phase change layer is interposed between the first columnar electrode and the second columnar electrode, electrically connecting both thereof, wherein the entirety of the phase change layer is... Agent: Quintero Law Office, PC

20070285961 - Semiconductor memory apparatus and method of driving the same: A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data stored in the unit cell. A threshold voltage control unit controls the threshold voltage of the switching MOS transistor.... Agent: Venable LLP

20070285960 - Single-mask phase change memory element: A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070285972 - Semiconductor memory device: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second... Agent: Nixon & Vanderhye, PC

20070285963 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, each having memory cells, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285964 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings connecting bit lines to the read/write circuit; and third vertical wirings connecting word lines to the read/write... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285965 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285966 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate to have a stack structure of a variable resistance element and an access element, the variable resistance element storing a high resistance state or a low resistance state in a non-volatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285967 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285968 - Resistance change memory device: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285969 - Resistance change memory device: A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285970 - Resistance change memory device: A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285971 - Resistance change memory device: A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285973 - Storage device: The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285974 - Semiconductor device: In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070285975 - Semiconductor device: In a memory using spin transfer torque, state of the spin is made unstable by applying a weak pulse before rewriting to reduce rewrite current. Reading of high-speed operation is performed with current in a regime where the current becomes non-linearly increases corresponding to the pulse width to suppress disturb.... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070285976 - Intergrated circuit having a precharging circuit: A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device... Agent: Dicke, Billig & Czaja

20070285977 - Thin film magnetic memory device suitable for drive by battery: After a digit line is charged to a power supply voltage by turn-on of a first switching element, the first switching element is turned off and a second switching element is turned on, whereby the digit line is connected to a ground voltage. Similarly, in order to feed data write... Agent: Buchanan, Ingersoll & Rooney PC

20070285978 - Magnetic memory and method of spin injection: According to this spin injection method, since a spin transfer torque assisted by an external magnetic field acts, a magnetization direction can be changed with a small current, and since the magnetization direction of a magnetosensitive layer can be controlled by just reducing the external magnetic field strength in the... Agent: Oliff & Berridge, PLC

20070285979 - Dynamic ram storage techniques: Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each... Agent: Townsend And Townsend And Crew LLP/ 015114

20070285980 - Semiconductor memory device: A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070285981 - Defective block handling in a flash memory device: A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines which rows of each memory block is defective and maps any further access to those rows to the redundant memory block. During an erase operation... Agent: Leffert Jay & Polglaze, P.A.

20070285982 - Memory array having a programmable word length, and method of operating same: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body... Agent: Neil Steinberg

20070285983 - Semiconductor memory device and manufacturing method of the same: The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate... Agent: Miles & Stockbridge PC

20070285984 - Data processing device: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the... Agent: Miles & Stockbridge PC

20070285985 - Flash memory device adapted to prevent read failures due to dummy strings: In a NAND flash memory device, a dummy NAND string is arranged between a plurality of normal NAND strings. A dummy bit line connected to the dummy NAND string is formed and/or controlled such that when program voltages are applied to the normal NAND strings, memory cells within the dummy... Agent: Volentine & Whitt PLLC

20070285986 - In-circuit vt distribution bit counter for non-volatile memory devices: Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range... Agent: Dillon & Yudell LLP

20070285988 - Bitline exclusion in verification operation: Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.... Agent: Leffert Jay & Polglaze, P.A.

20070285987 - Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time: Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the... Agent: Mcdermott Will & Emery LLP

20070285989 - Column decoding system for semiconductor memory devices implemented with low voltage transistors: A column decoding system (140, 150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070285990 - Semiconductor device and method for compensating voltage drop of a bit line: Provided are a semiconductor device and a method for compensating for a voltage drop of a bit line. The semiconductor device includes at least one monitoring bit line and at least one main memory bit line, and monitors a voltage of the at least one monitoring bit line after a... Agent: F. Chau & Associates, LLC

20070285991 - Semiconductor memory: A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating... Agent: Buchanan, Ingersoll & Rooney PC

20070285992 - Semiconductor memory device and method of controlling semiconductor memory device: A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite... Agent: Arent Fox LLP

20070285994 - Semiconductor memory device: Reducing power consumption of a semiconductor memory device having a serial interface is disclosed. After parallel read-out data from a memory-cell matrix 14 are held in a data latch 17, the parallel read-out data are selected sequentially by a serial output selector 18 according to timing signals SL0-SL15 from a... Agent: Nixon Peabody, LLP

20070285993 - Systems and methods for common instance handling of providers in a plurality of frameworks: Systems and methods are provided for handling instances of providers in a plurality of frameworks. An instance of a first provider is created and registered to store a first change to a buffer. An instance of a second provider is created and registered to store a second change to the... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.

20070285995 - Memory device capable of detecting its failure: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for... Agent: Ladas & Parry LLP

20070285996 - Shared memory synchronization systems and methods: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070285997 - Memory system: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data... Agent: Miles & Stockbridge PC

20070285998 - Semiconductor memory apparatus: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response... Agent: Venable LLP

20070285999 - Sensing circuit for semiconductor memories: A sensing circuit is provided. The sensing circuit is adapted to determine when a cell current flowing trough a selected memory cell exceeds a reference current during an evaluation phase of a sensing operation. The sensing circuit is adapted to be coupled to at least one selected memory cell through... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070286000 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman

20070286001 - Semiconductor integrated circuit with memory redundancy circuit: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data... Agent: Stanley P. Fisher Reed Smith LLP

20070286002 - Method for writing to multiple banks of a memory device: In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and... Agent: Trask Britt, P.C./ Micron Technology

20070286003 - Temperature gain compensation system and method for disc label laser etching process: A temperature gain compensation system for disk label laser etching process contains a servo device, a DSP, a driver IC, and a temperature compensator. A temperature sensor in the servo device transmits a temperature signal to the temperature compensator. Then the temperature compensator obtains a temperature difference and calculates a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070286004 - Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh: A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the... Agent: Mcdermott Will & Emery LLP

20070286005 - Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are... Agent: Borden Ladner Gervais LLP Anne Kinsman

20070286006 - Method and apparatus for drain pump operation: A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain... Agent: Ingrassia Fisher & Lorenz, P.C.

20070286007 - High-voltage generating circuit including charge transfer switching circuit for selectively controlling body bias voltage of charge transfer device: Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor... Agent: Harness, Dickey & Pierce, P.L.C

20070286008 - Method and apparatus for reduced power cell: The invention relates to reduced power cells. Some embodiments of the invention provide a memory circuit that has a storage cell. The storage cell contains several electronic components and an input. The electronic components receive a reduced voltage from the input to the cell. The reduced voltage reduces the current... Agent: Adeli Law Group, A Professional Law Corporation

20070286009 - Serial memory interface: A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the... Agent: Unity Semiconductor Corporation

20070286011 - Memory device having data input and output ports and memory module and memory system including the same: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices... Agent: Volentine & Whitt PLLC

20070286010 - Identical chips with different operations in a system: In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only provide signals, and the control circuitry is to control whether the third ports are to only receive... Agent: Blakely Sokoloff Taylor & Zafman

20070286012 - Method for controlling data output timing of memory device and device therefor: Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS latency, wherein the... Agent: Ladas & Parry LLP

20070279959 - Metal line layout in a memory cell: A memory cell is provided having polysilicon gates 2 running in a first direction. A sequence of layers metal lines are provided including layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed data lines 6 running in that second direction and then... Agent: Nixon & Vanderhye, PC

20070279960 - Memory system and semiconductor integrated circuit: A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time, When power is turned on, the set data that... Agent: Mcdermott Will & Emery LLP

20070279962 - High density memory array for low power application: A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate... Agent: Dicke, Billig & Czaja

20070279963 - Semiconductor memory: The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279961 - Providing a reference voltage to a cross point memory array: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug.... Agent: Unity Semiconductor Corporation

20070279966 - 8t sram cell with higher voltage on the read wl: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry... Agent: Texas Instruments Incorporated

20070279965 - Method and apparatus for avoiding cell data destruction caused by sram cell instability: Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a... Agent: SprinkleIPLaw Group

20070279964 - Sram split write control for a delay element: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay... Agent: Honeywell International Inc.

20070279967 - High density magnetic memory cell layout for spin transfer torque magnetic memories utilizing donut shaped transistors: A method and system for providing and using a magnetic storage cell and magnetic memory is described. The method and system include providing a magnetic element and providing a selection device. The magnetic element is programmable to a first state by a first write current driven through the magnetic element... Agent: Strategic Patent Group, P.C.

20070279973 - Magnetic memory: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When... Agent: Oliff & Berridge, PLC

20070279972 - Memory: A memory including a memory element having a memory layer that retains information based on a magnetization state of a magnetic material, and a conductor electrically connected to the memory element is provided. In the memory, a magnetization pinned layer is provided for the memory layer through an intermediate layer,... Agent: Bell, Boyd & Lloyd, LLP

20070279968 - Method and system for providing a magnetic memory structure utilizing spin transfer: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element... Agent: Strategic Patent Group, P.C.

20070279970 - Nonvolatile memory with data clearing functionality: A nonvolatile memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive memory bit. The memory includes toggle circuitry for altering the resistive states of memory cells within the memory without changing the logical states of the memory cells.... Agent: Honeywell International Inc.

20070279969 - Intrusion detection apparatus and method: An apparatus and method to detect intrusion into a protected enclosure without requiring electrical power. The invention consists of an array of at least two magnetic memory elements, each of which has two electronically-readable stable states in the presence of a bias magnetic field, and a means for providing the... Agent: Raytheon Company, (eo/e04/n119) Intellectual Property & Licensing

20070279971 - Modified pseudo-spin valve (psv) for memory applications: A pseudo-spin valve for memory applications, such as magnetoresistive random access memory (MRAM), and methods for fabricating the same, are disclosed. Advantageously, memory devices with the advantageous pseudo-spin valve configuration can be fabricated without cobalt-iron and without anti-ferromagnetic layers, thereby promoting switching repeatability.... Agent: Knobbe Martens Olson & Bear LLP

20070279974 - Forming heaters for phase change memories with select devices: Rather than depositing a heater material into a pore, a heater material may be first blanket deposited over a select device. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between... Agent: Trop Pruner & Hu, PC

20070279975 - Refreshing a phase change memory: A phase change memory may be utilized in place of a dynamic random access memory in a processor-based system. In some embodiments, a chalcogenide material, used for the phase change memory, has relatively high crystallization speed so that it may be quickly programmed. Materials may be chosen which have high... Agent: Trop Pruner & Hu, PC

20070279976 - Read, write, and erase circuit for programmable memory devices: A circuit for writing, reading, and erasing a programmable device is disclosed. The programmable device includes an ion conductor and a plurality of electrodes. Electrical properties of the device are altered by applying a sufficient bias across the electrode to form a conductive region within the ion conductor. The circuit... Agent: Snell & Wilmer L.L.P. (main)

20070279977 - Semiconductor magnetic memory: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070279978 - Magnetic random access memory using single crystal self-aligned diode: A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers... Agent: Martine Penilla & Gencarella, LLP

20070279979 - Semiconductor memory device: This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279982 - Semiconductor memory device capable of correcting a read level properly: In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279983 - Semiconductor memory device and data transmission method thereof: A semiconductor memory device includes a nonvolatile memory which stores protect information, a controller which includes a system buffer and controls a physical state of the nonvolatile memory, a battery which drives the nonvolatile memory and the controller, first transmission/reception means capable of transmitting data in the nonvolatile memory to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279984 - Nonvolatile semiconductor storing device and block redundancy saving method: A nonvolatile semiconductor storing device according to the present invention comprises a block replacing means for replacing a defective block with a redundant block when a memory block in a memory array is the defective block. The block replacing means includes an address translation circuit 10 for converting an inputted... Agent: Morrison & Foerster LLP

20070279986 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to examples of the present invention includes a NAND string comprised memory cells connected in series, two select gate transistors each of which is connected to each end of the NAND string, and a write control circuit which makes a first write condition for a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279985 - System for verifying non-volatile storage using different voltages: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for... Agent: Vierra Magen/sandisk Corporation

20070279988 - Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070279987 - Non-volatile memory embedded in a conventional logic process and methods for operating same: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070279989 - Programming a non-volatile memory device: A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data.... Agent: Leffert Jay & Polglaze, P.A.

20070279980 - Reading method of a non-volatile electronic device and corresponding device: A crossed electric connection is provided between the reference terminal of at least one group of sense amplifiers of the first memory bank to an output of a subgroup of sense amplifiers of the second memory bank, and vice versa, and the subgroup of sense amplifiers associated with a memory... Agent: Seed Intellectual Property Law Group PLLC

20070279981 - Nand-structured flash memory: A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279991 - Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same: A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is then used to send out a... Agent: Rosenberg, Klein & Lee

20070279992 - Non-volatile memory and method with reduced neighboring field errors: A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070279990 - Nonvolatile memory having latching sense amplifier and method of operation: A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharging a selected bitline to a first predetermined voltage in... Agent: Freescale Semiconductor, Inc. Law Department

20070279994 - Data pattern sensitivity compensation using different voltage: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating... Agent: Vierra Magen/sandisk Corporation

20070279995 - System for performing data pattern sensitivity compensation using different voltage: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating... Agent: Vierra Magen/sandisk Corporation

20070279993 - Verify operation for non-volatile storage using different voltages: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for... Agent: Vierra Magen Marcus & Deniro LLP

20070279997 - Memory self-test circuit, semiconductor device and ic card including the same, and memory self-test method: In a semiconductor device, a self-test circuit includes a write part for writing data in a given address of a special region of a nonvolatile memory; a read part for reading the written data from the given address; a verify part for determining whether or not the written data accords... Agent: Mcdermott Will & Emery LLP

20070279996 - Method and system for refreshing a memory device during reading thereof: A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells... Agent: Seed Intellectual Property Law Group PLLC

20070279998 - Semiconductor device and semiconductor integrated circuit: semiconductor device includes a first nonvolatile memory element group which includes a plurality of first nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics, a verify circuit which detects a defective first nonvolatile memory element in the first nonvolatile memory element group, and a second nonvolatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070279999 - Nonvolatile semiconductor memory device and method of operating the same which stably perform erase operation: A nonvolatile semiconductor memory device includes a memory array and an X-decode section. The memory array includes a plurality of nonvolatile memory cells arranged in a matrix form and a plurality of word lines. The X-decode section selects a selected word line selected from the plurality of word lines, supplies... Agent: Young & Thompson

20070280000 - Method of writing data to a semiconductor memory device: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including:... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280002 - Charge-trapping memory device and methods for its manufacturing and operation: A charge-trapping memory device includes an array of non-volatile memory cells. The array has at least a first sector and a second sector. Each sector includes a multiplicity of memory cells. Each memory cell is adapted to trap an amount of charge indicative of a programming state. A control circuit... Agent: Slater & Matsil LLP

20070280001 - Method for programming and erasing an array of nmos eeprom cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits: A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments... Agent: Baker Botts, LLP

20070280003 - Non-volatile semiconductor memory device having different erase pass voltages for respective memory sectors and associated erase method: A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory cells can be erased using a first mode erase operation, which determines different erase pass voltages for the respective memory sectors by successively increasing a bank voltage applied... Agent: Volentine & Whitt PLLC

20070280004 - Nonvolatile semiconductor memory device and method of testing thereof: A method of testing a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device is provided with a memory cell of a field effect transistor type. The method includes: (A) performing erasing of the memory cell by using FN (Fowler-Nordheim) method; (B) performing programming back of the memory... Agent: Young & Thompson

20070280005 - Semiconductor storage device and semiconductor storage device driving method: A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280006 - Data processing device, data processing method, and program: A data processing device for processing time-sequence data includes a data extracting unit operable to extract time-sequence data for a predetermined time unit from time-sequence data; and a processing unit operable to obtain scores for nodes of an SOM configured from multiple nodes provided with a spatial array configuration, the... Agent: Frommer Lawrence & Haug LLP

20070280007 - Memory device, memory system and method of operating such: A memory device comprising a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070280008 - Internal voltage generator for use in semiconductor memory device: An internal voltage generator stably supplies an internal voltage in a semiconductor device. The internal voltage generator includes: a first internal voltage generating means for supplying a first internal voltage which has a level corresponding to a first reference voltage using an external voltage; a second internal voltage generating means... Agent: Mcdermott Will & Emery LLP

20070280009 - Semiconductor memory device: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280010 - Voltage stabilizer memory module: A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality... Agent: Sawyer Law Group LLP

20070280012 - Semiconductor device: In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The... Agent: Mcdermott Will & Emery LLP

20070280014 - Semiconductor device: A semiconductor device having a self test function includes a memory, a first data processing portion connected to a former stage of the memory through a first path, a second data processing portion connected to a latter stage of the memory through a second path, a failure detecting circuit for... Agent: Mcdermott Will & Emery LLP

20070280015 - Semiconductor device: Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit... Agent: Mcdermott Will & Emery LLP

20070280013 - Semiconductor memory device, memory module having the same, the test method of memory module: A semiconductor memory device according to the present invention is mounted on a memory module. The semiconductor memory device has a redundant circuit and a chip select circuit. The semiconductor memory device is allowed to be selected in the memory module by using a memory address that has been replaced... Agent: Paul J. Esatto, Jr. Scully, Scott, Murphy & Presser

20070280011 - Integrated electrical module with regular and redundant elements: An integrated electrical module has a set of regular elements and a set of redundant elements, the elements being split over at least two blocks which are individually selectable by an input address and respectively containing regular elements and redundant elements. The integrated electrical module further has two repair circuits,... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070280017 - Nonvolatile semiconductor memory device: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070280016 - Semiconductor device and method for operating a semiconductor device: One aspect relates to a semiconductor device, and to a method for operating a semiconductor device. In one case, the method includes incorporating the semiconductor device in an electronic module, and programming at least one eFuse provided on the semiconductor device after the incorporation of the semiconductor device in the... Agent: Dicke, Billig & Czaja

20070280018 - Semiconductor memory device, a local precharge circuit and method thereof: A semiconductor memory device, a local precharge circuit and a method thereof are provided. The example semiconductor memory device may include a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which... Agent: Harness, Dickey & Pierce, P.L.C

20070280019 - Apparatus for controlling activation period of word line of volatile memory device and method thereof: An apparatus for controlling an activation period of a word line of a volatile memory device is disclosed. The apparatus adjusts the activation period of the word line using a member for adjusting a pulse width of a pulse signal that activates the word line according to an operation mode... Agent: Ladas & Parry LLP

20070280020 - Semiconductor memory device having local sense amplifier: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and... Agent: Volentine & Whitt PLLC

20070280021 - Sense amplifier: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280022 - Method and apparatus for a dummy sram cell: A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second... Agent: Qualcomm Incorporated

20070280023 - Phase change memory having temperature budget sensor: A semiconductor device includes a plurality of memory cells, a temperature budget sensor, and a circuit. The circuit periodically compares a signal from the temperature budget sensor to a reference signal and refreshes the memory cells based on the comparison.... Agent: Dicke, Billig & Czaja

20070280024 - Power-up signal generator for use in semiconductor device: In an apparatus for generating a power-up signal, a mode register set (MRS) and other circuits are prevented from being reset, thereby providing stable circuit operation. A final power-up signal is not disabled even though an internal voltage generating unit is turned off at a test mode. The apparatus includes... Agent: Mcdermott Will & Emery LLP

20070280025 - Semiconductor memory device and semiconductor memory device control method: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell... Agent: Foley And Lardner LLP Suite 500

20070280026 - Low voltage memory device and method thereof: A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large... Agent: Larson Newman Abel Polansky & White, LLP

20070280027 - Memory device and method having banks of different sizes: A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored is determined by... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070280028 - Semiconductor device: An object is to realize high-capacity of a memory while reducing power consumption and making the power consumption even throughout the memory. A memory includes a plurality of memory block arranged to be symmetrically to each other. Also, a specific combination of signals among address signals supplied to the memory,... Agent: Eric Robinson

20070280029 - Connecting system between devices and connecting devices: A first pin scramble buffer selectively connects first signal lines to first connecting terminals, and a second pin scramble buffer selectively connects second signal lines to second connecting terminals. The first connecting terminals and the second connecting terminals are connected in a fixed connection relationship. A parameter generator generates and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280030 - Contention-free hierarchical bit line in embedded memory and method thereof: A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The... Agent: Larson Newman Abel Polansky & White, LLP

20070280031 - Nand type flash memory: A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070280033 - Methods and devices for regulating the timing of control signals in integrated circuit memory devices: A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the... Agent: Myers Bigel Sibley & Sajovec

20070280032 - Built-in system and method for testing integrated circuit timing parameters: A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal are generated by a test... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070280034 - System and method for performing low power dynamic trimming: A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled... Agent: Nvidia C/o Murabito, Hao & Barnes LLP