Static information storage and retrieval inventions 11/07

20070274116 - Multi-level voltage adjustment: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment,... Agent: Freescale Semiconductor, Inc. Law Department

20070274117 - Retractable card adapter: Methods and apparatus for interfacing a memory device with a host device are 5 disclosed. According to one aspect of the present invention, an apparatus which enables a non-volatile memory device to communicate with a host device includes a body and an element. The body has a boundary, and the... Agent: Winston & Strawn, LLP

20070274118 - Dynamically read fuse cell: A dynamically read fuse cell comprises a first circuit which includes a known reference resistance Rref, and a second circuit which includes a programmed fuse having a resistance Rfuse; the state of the programmed fuse is to be read. The first and second circuits receive a common “read” signal, and... Agent: Koppel, Patrick & Heybl

20070274119 - Over-driven access method and device for ferroelectric memory: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070274120 - Cbram cell with a reversible conductive bridging mechanism: According to the invention CBRAM cell is provided exhibiting a resistive switching effect offering the possibility to store multiple memory states in one cell by programming said memory cell to different resistance levels including at least a first memory state with a high resistance level representing a low-conductivity state of... Agent: Morrison & Foerster LLP

20070274121 - Multi-level memory cell having phase change element and asymmetrical thermal boundary: A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070274122 - Memory device having open bit line structure and method of sensing data therefrom: A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense... Agent: Volentine & Whitt PLLC

20070274123 - Controllable nanomechanical memory element: A memory device includes a mechanical element that exhibits distinct bistable states under amplitude modulation. The states are dynamically bistable or multi-stable with the application of a drive signal of a given frequency. The natural resonance of the element in conjunction with a hysteretic effect produces distinct states over a... Agent: Weingarten, Schurgin, Gagnebin & Lebovici LLP

20070274124 - Semiconductor memory device with improved resistance to disturbance and improved writing characteristic: A semiconductor memory device includes a first inverter ad a second inverter, a first power supply control circuit, and a second power supply control circuit. The first and second inverters constitute a memory cell and each have an input terminal and an output terminal connected crosswise to an output terminal... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070274125 - Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element: A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line.... Agent: Ryan, Mason & Lewis, LLP

20070274126 - Method and apparatus for hot carrier programmed one time programmable (otp) memory: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or... Agent: Ryan, Mason & Lewis, LLP

20070274127 - Semiconductor nonvolatile storage circuit: A semiconductor nonvolatile storage circuit capable of stably storing and holding information by preventing pseudo-writing in storing/holding FETs is realized. The semiconductor nonvolatile circuit includes a first FET MNM1 forming a source-drain path between a ground potential GND and a bit line BL; a second FET MNM2 forming a source-drain... Agent: Kratz, Quintos & Hanson, LLP

20070274128 - Method and system for programming multi-state non-volatile memory devices: A non-volatile memory system and a method for programming is provided. The memory system includes a first set of memory cells that can operate in multiple states X; and a second set of memory cells that can operate in multiple states Y; wherein the multiple state X and multiple state... Agent: Klein, O'neill & Singh, LLP

20070274129 - Data processing device: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines... Agent: Miles & Stockbridge PC

20070274130 - single poly, multi-bit non-volatile memory device and methods for operating the same: A non-volatile memory device comprises a substrate with a dielectric layer formed thereon. A control gate is formed on the dielectric layer, as are two floating gates, one on either side of the control gate. Accordingly, the non-volatile memory device can be constructed using a single poly process that is... Agent: Baker & Mckenzie LLP Patent Department

20070274131 - Non-volatile semiconductor memory device, erase method for same, and test method for same: A non-volatile semiconductor memory device includes a memory cell array and an operation control circuit. The memory cell array includes a plurality of non-volatile memory cells that are electrically rewritable. The operation control circuit controls an operation of the memory cell array in accordance with an external instruction. The operation... Agent: Arent Fox LLP

20070274132 - Discharge order control circuit and memory device: A discharge order control circuit includes a pool circuit, a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070274133 - Flash memory device and related high voltage generating circuit: In a high voltage generating circuit for a semiconductor memory device, a discharge path is cut off during a program verification period of a program operation for the device.... Agent: Volentine & Whitt PLLC

20070274134 - Method and apparatus for improving storage performance using a background erase: Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy... Agent: Trask Britt, P.C./ Micron Technology

20070274135 - Low power and low timing jitter phase-lock loop and method: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070274136 - Semiconductor integrated circuit device: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable... Agent: Miles & Stockbridge PC

20070274137 - Memory card, data driving method thereof, and memory card system including the same: A memory card including a pad, a drive circuit activating the pad in accordance With an input signal, and a controller regulating a drive voltage level and a drive point of an output signal generated from the drive circuit in accordance with a voltage level of the output signal of... Agent: F. Chau & Associates, LLC

20070274138 - Reference voltage generating circuit: In this reference voltage generating circuit, the first current generating circuit generates the first constant current irrespective of the power supply voltage, when temperature is constant. When temperature changes, the magnitude of the first current changes according to the change. The second current generating circuit generates a second current depending... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070274139 - Semiconductor memory device and semiconductor device: A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a... Agent: Stanley P. Fisher Reed Smith LLP

20070274140 - A novel sram cell design to improve stability: The present invention relates to a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access... Agent: Scully Scott Murphy & Presser, PC

20070274141 - Non volatile memory device architecture and corresponding programming method: A non volatile memory device architecture, suitable for speeding up and synchronize the programming steps of the cells in particular of the Flash-Nor type, of the type comprising a matrix of memory cells organized into rows and columns, at least one group of these columns being selected by at least... Agent: Graybeal Jackson Haley LLP Suite. 350

20070274142 - Method and device of generating test circuit for semiconductor device: The test circuit generating method comprises the steps of: a first step for obtaining memory information containing structural information of the memory; a second step for obtaining failure judgment bit information that designates a judgment target bit as a target of failure judgment from entire output bits of the memory;... Agent: Mcdermott Will & Emery LLP

20070274143 - Semiconductor device, electronic equipment and equipment authentication program: A semiconductor device judges the justice of electronic equipment with authentication information of the electronic equipment to which peculiar ID information is given. The semiconductor device includes: an equipment authentication section for judging the justice of a second electronic equipment with the authentication information obtained from the second electronic equipment... Agent: Mcdermott Will & Emery LLP

20070274144 - Semiconductor integrated circuit device: In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is... Agent: Miles & Stockbridge PC

20070274145 - Refresh control circuit in semiconductor memory apparatus and method of controlling period of refresh signal using the same: A refresh control circuit includes a temperature detecting unit that detects the temperature and generates a temperature detecting voltage, a control unit that generates a plurality of control signals, a digital converting unit that converts the temperature detecting voltage into a plurality of bits of digital code and outputs a... Agent: Venable LLP

20070274146 - Tras adjusting circuit for self-refresh mode in a semiconductor device: A tRAS adjusting circuit extends an active operation in a self-refresh operation. The tRAS adjusting circuit includes: a self-refresh sensing unit for receiving a self-refresh signal and a refresh signal and generating a sensing signal; a first extension unit for extending an enable interval of an active operation pulse; a... Agent: Ladas & Parry LLP

20070274147 - Integrated semiconductor memory and method for operating an integrated semiconductor memory: An integrated semiconductor memory that has at least one temperature measuring element and repeatedly carries out a temperature measurement during the operation of the semiconductor memory, wherein the semiconductor memory repeats the temperature measurement at instants corresponding to a measuring frequency of the temperature measuring element. According to an embodiment... Agent: Slater & Matsil, L.L.P.

20070274149 - Semiconductor integrated circuit: A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory... Agent: Mcdermott Will & Emery LLP

20070274148 - Semiconductor memory device, and data transmitting/receiving system: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output... Agent: Mcdermott Will & Emery LLP

20070274150 - Non-volatile memory control: Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a... Agent: Leffert Jay & Polglaze, P.A.

20070268730 - Memory device driving circuit: A memory device driving circuit is disclosed which drives a memory device including a first electrode, a second electrode, and a memory layer interposed between the first electrode and the second electrode. The memory device driving circuit may include a main driver connected to the memory device, to drive the... Agent: Harness, Dickey & Pierce, P.L.C

20070268731 - Layout compiler: For methods of creating pluralities of semiconductor test structure layouts from a graphical specification, systems include a GUI to draw objects representing shapes of such layout, and to parameterize those objects to size and interrelate those objects. The GUI supports placement of cells in hierarchical layers. The graphical specification is... Agent: Morrison & Foerster LLP

20070268733 - Magnetic storage device: A magnetic storage device includes magnetoresistance effect elements. First and second write lines extend along a first direction. Current flows in the first and second write lines only in the first direction and a second direction opposite to the first direction, respectively. A third write line extends along a third... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070268732 - Method and apparatus providing non-volatile memory with reduced cell capacitive coupling: A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The... Agent: Dickstein Shapiro LLP

20070268734 - Thermoplastic plastic and method for producing the same: A method for producing thermoplastic plastic capable of grasping information concerning the production process even after distribution. In a plurality of production processes including fusion of thermoplastic plastic 90, an information presenting substance 91 is added to the thermoplastic plastic sequentially and dispersed therein in each of the production process,... Agent: Kratz, Quintos & Hanson, LLP

20070268735 - Method and apparatus for compensating for variances of a buried resistor in an integrated circuit: A method and apparatus that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.... Agent: Ibm Microelectronics Intellectual Property Law

20070268737 - Nonvolatile memory device: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore,... Agent: Mcdermott Will & Emery LLP

20070268736 - On-chip heater and methods for fabrication thereof and use thereof: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200°... Agent: Scully, Scott, Murphy & Presser, P.C.

20070268738 - Methods and apparatus to provide voltage control for sram write assist circuits: Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method disclosed herein includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write assist circuit further includes... Agent: Texas Instruments Incorporated

20070268739 - Nanowire memory device and method of manufacturing the same: A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode;... Agent: Sughrue Mion, PLLC

20070268740 - Ultra low power sram cell design: A semiconductor SRAM cell is provided and includes two back-to-back inverters and two p-channel (PMOS) access transistors. In one preferred embodiment the sources of two pull down n-channel (NMOS) transistors are connected to the drain of the ground NMOS transistor, which is connected to ground. During write operation the ground... Agent: Kean, Miller, Hawthorne, D'armond, Mccowan & Jarman, L.L.P.

20070268741 - Non-volatile memory cell and methods thereof: A non-volatile storage element disposed at an integrated circuit is disclosed. The storage element includes a first resistive element having a first magnetic tunnel junction (MTJ) element, a first node coupled to the first resistive element, a second resistive element having of a second MTJ element, a second node coupled... Agent: Larson Newman Abel Polansky & White, LLP

20070268742 - Memory architecture and cell design employing two access transistors: An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070268743 - Magnetic memory layers thermal pulse transitions: A ferromagnetic thin-film based digital memory having a bit structures therein a magnetic material film in which a magnetic property thereof is maintained below a critical temperature above which such magnetic property is not maintained, and may also have a plurality of word line structures each with heating sections located... Agent: Kinney & Lange, P.A.

20070268744 - Memory system with switch element: A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line... Agent: Ishimaru & Zahrt LLP

20070268745 - Method of storing data in a multi-bit-cell flash memory: In writing to a block, of a flash memory, that includes pages with different write access or read access speeds, after writing first data to a first page that has fast access, at least one page that has slow access is skipped to write second data to a second page... Agent: Mark M. Friedman

20070268746 - Nonvolatile memory device performing 2-bit operation and method of manufacturing the same: A nonvolatile memory device includes active regions extending in a word line direction in a semiconductor substrate and defined in a first zigzag pattern; gates extending in the word line direction and formed in a second zigzag pattern that repeatedly intersects the active regions in symmetry with the first zigzag... Agent: Lee & Morse, P.C.

20070268747 - Static noise-immune sram cells: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load... Agent: Slater & Matsil, L.L.P.

20070268748 - Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards: A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to... Agent: Myers Bigel Sibley & Sajovec

20070268749 - Method for operating non-volatile memory device: A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to... Agent: Volentine & Whitt PLLC

20070268751 - Flash memory device and related high voltage generating circuit: In a flash memory device, a high voltage generating circuit generates a high voltage and receives the high voltage as a switching voltage for controlling a voltage dividing circuit.... Agent: Volentine & Whitt PLLC

20070268750 - Semiconductor memory device: A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070268752 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells... Agent: Townsend And Townsend And Crew, LLP

20070268753 - Methods of operating bandgap engineered memory: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height;... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070268754 - Recycling partially-stale flash blocks using a sliding window for multi-level-cell (mlc) flash memory: A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of... Agent: Stuart T Auvinen

20070268755 - Memory circuit: A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory... Agent: Nixon & Vanderhye, PC

20070268756 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070268757 - High voltage detecting circuit for semiconductor memory device and method of controlling the same: Provided are a boosted voltage detecting circuit capable of reducing the consumption of current and reducing ripple in boosted voltage during a self-refresh operation of a semiconductor memory device, and a method of controlling the same. One embodiment of the boosted voltage detecting circuit includes a feedback unit feeding back... Agent: Marger Johnson & Mccollom, P.C.

20070268758 - Memory array with psedudo single bit memory cell and method: In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The... Agent: Marshall, Gerstein & Borun LLP (intel)

20070268759 - Systems for and methods of asset management in a waste management service environment: One embodiment of the present invention includes an identification mechanism, such as a radio frequency identification (RFID) tag or barcode, associated with a waste container. The identification mechanism contains an identifier that can be used to identify the waste container, and that can be read by a vehicle with an... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070268761 - Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same: An integrated circuit device (for example, a logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory)), including (a) a memory cell array having a plurality of memory cells arranged in (i) a plurality of normal rows of memory cells... Agent: Neil Steinberg

20070268760 - Semiconductor memory in which fuse data transfer path in memory macro is branched: A semiconductor device includes a memory macro and fuse box. The fuse box includes a clock generator, a plurality of first data latch circuits which latch fuse data, and serially transfer the fuse data upon receiving transfer clocks, and a clock counter which counts the transfer clocks, and generates a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070268762 - Semiconductor memory and method for testing the same: A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time and by which a test cost is reduced and a method for testing such a semiconductor memory. The plurality of CRs hold operation mode information. When a CR control circuit detects... Agent: Arent Fox LLP

20070268763 - Method for controlling precharge timing of memory device and apparatus thereof: A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making... Agent: Ladas & Parry LLP

20070268764 - Low voltage sense amplifier and sensing method: Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier.... Agent: Kimton N.eng, Esq. Dorsey & Whitney LLP

20070268765 - Integrated circuit memory device having dynamic memory bank count and page size: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070268766 - Semiconductor memory and refresh cycle control method: A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for... Agent: Arent Fox LLP

20070268767 - Circuit and method for controlling self-refresh cycle: The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor... Agent: Ladas & Parry LLP

20070268768 - Semiconductor memory: A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the... Agent: Arent Fox LLP

20070268769 - Semiconductor memory device with reduced current consumption: A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power... Agent: Arent Fox LLP

20070268772 - Semiconductor memory and operating method of same: An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon receipt of the next access... Agent: Arent Fox LLP

20070268770 - Semiconductor memory device: A memory device with global lines being used for other applications when the global lines are not in use is provided. The memory device includes: a plurality of banks; a global input/output line for transferring data input/output signals of the plurality of banks in a normal operation; and a bank... Agent: Blakely Sokoloff Taylor & Zafman

20070268771 - Semiconductor memory device: If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of... Agent: Miles & Stockbridge PC

20070268774 - High voltage transfer circuit and row decoder circuit comprising a high voltage transfer circuit: Embodiments of the invention provide a high voltage transfer circuit, a row decoder circuit comprising the high voltage transfer circuit, and a non-volatile semiconductor memory device comprising the high voltage transfer circuit. In one embodiment, the invention provides a high voltage transfer circuit of a semiconductor memory device comprising a... Agent: Volentine & Whitt PLLC

20070268773 - Programming a non-volatile memory device: A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070268776 - Semiconductor memory device and test method thereof: When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used... Agent: Sughrue Mion, PLLC

20070268777 - Integrated semiconductor memory device with clock generation: A memory device can be operated in a first operating state and a second operating state, where read access to memory cells can be performed in the first operating state. The memory device includes an activatable clock generator circuit to generate a clock signal. The clock generator circuit can be... Agent: Edell, Shapiro & Finnan, LLC

20070268775 - Nand system with a data write frequency greater than a command-and-address-load frequency: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070263423 - Three-dimensional memory device incorporating segmented array line memory array: A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on... Agent: Zagorin O'brien Graham LLP (023)

20070263424 - Serial bus controller using nonvolatile ferroelectric memory: A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention,... Agent: Heller Ehrman LLP

20070263425 - Memory arrangement: A memory arrangement is disclosed. In one embodiment, the control device includes a plurality of memory arrays for storing data and a control device for controlling the transfer of data between the plurality of memory arrays and external circuits. In one embodiment, the control device is arranged on a different... Agent: Dicke, Billig & Czaja

20070263428 - Semiconductor memory device having layout area reduced: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a... Agent: Mcdermott Will & Emery LLP

20070263427 - General purpose register circuit: A general purpose register circuit that stores and outputs desired data as required by a program stored in a storage device, has a memory cell which is connected to a word line and a bit line for writing and reading of the data; and a multiplexer circuit which is connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070263426 - Optical flip-flop circuit: A flip-flop circuit of the present invention includes a first switch and a second switch which are connected in series to each other. The first switch includes: two input ports upon which light source light and signal light are incident; two output ports for outputting an optical output; and a... Agent: Wenderoth, Lind & Ponack, L.L.P.

20070263429 - Memory element and memory: A memory element including a memory layer that retains information based on a magnetization state of a magnetic material is provided. In the memory element, a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons are... Agent: Bell, Boyd & Lloyd, LLP

20070263431 - Magnetic memory device and method of fabricating the same: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer... Agent: Myers Bigel Sibley & Sajovec

20070263430 - Method for switching magnetic random access memory elements and magnetic element structures: A method for storing data in a magnetic memory element of an array of elements which avoids inadvertent switching of other elements is disclosed. First and second magnetic fields are applied to a selected magnetic element for a first time interval to switch the element into an intermediate state where... Agent: Connolly Bove Lodge & Hutz, LLP

20070263432 - Capacitive single- electron transistor: The invention is a sensitive measuring instrument, which is principally applied to quantum computation, especially to measurement of quantum bits consisting of superconducting micro and nano-structures. The state of a quantum bit is expressed as the voltage-time integral over a circuit component. Phase measurement is performed by measuring the capacitance... Agent: OpticusIPLaw, PLLC

20070263433 - Semiconductor device: Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.... Agent: Stanley P. Fisher Reed Smith LLP

20070263434 - Magnetic tunnel junction device and writing/reading for said device: The device successively comprises a first electrode (12), a magnetic reference layer (1), a tunnel barrier (3), a magnetic storage layer (4) and a second electrode (13). At least one first thermal barrier is arranged between the storage layer (4) and the second electrode (13) and is formed by a... Agent: Oliff & Berridge, PLC

20070263435 - Multiport semiconductor memory device: In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD−Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports... Agent: Mcdermott Will & Emery LLP

20070263441 - Analog interface for a flash memory die: A flash disk controller includes an input operable to receive analog signals from a flash memory die. The flash memory die includes multiple flash memory cells. The analog signals represent data values stored in the flash memory cells. An analog-to-digital conversion module is coupled to the input to convert received... Agent: Fish & Richardson P.C.

20070263439 - Dynamic cell bit resolution: A system and method, including computer software, is used to write to a flash memory device that includes multiple memory cells. One or more of the memory cells are written at a first resolution corresponding to a first number of bits of data. A signal to write at a second... Agent: Fish & Richardson P.C.

20070263440 - Multi-chip package for a flash memory: An electronic system includes a flash memory die having multiple flash memory cells. Each flash memory cell is operable to store at least four bits of data. A second die includes a controller for accessing the flash memory cells. DRAM is used by the controller to temporarily store data. An... Agent: Fish & Richardson P.C.

20070263442 - Off-die charge pump that supplies multiple flash devices: A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive... Agent: Fish & Richardson P.C.

20070263438 - Method for reading nand memory device and memory cell array thereof: A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in... Agent: Oliff & Berridge, PLC

20070263443 - Method, apparatus, and system for providing initial state random access memory: A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial... Agent: Dickstein Shapiro LLP

20070263444 - Non-volatile memory system with end of life calculation: A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory's expected remaining lifetime in real time units (i.e., hours... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070263445 - Non-volatile memory cell array: One aspect of the invention relates to a non-volatile memory cell array and a fabrication method thereof. The non-volatile memory cell array includes first wordlines running in parallel along a first direction as well as second wordlines running in parallel along a second direction. Said first wordlines provide gate electrodes... Agent: Dicke, Billig & Czaja

20070263446 - Method for programming nand flash memory device and page buffer performing the same: A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from... Agent: Oliff & Berridge, PLC

20070263447 - Static semiconductor memory: A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control... Agent: Mcdermott Will & Emery LLP

20070263448 - Operating method of a non-volatile memory: A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are... Agent: Jianq Chyun Intellectual Property Office

20070263449 - Method and apparatus for programming flash memory: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.... Agent: Dickstein Shapiro LLP

20070263436 - Method and apparatus to improve nonvolatile memory data retention: Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, reference memory corresponding to the data memory is used to determine whether to refresh the data memory.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070263437 - Method and apparatus to improve nonvolatile memory data retention: Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, monitor reference currents in addition to a normal reference current are used to determine whether to refresh the data memory.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070263450 - Non-volatile memory and method with shared processing for an aggregate of read/write circuits: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070263452 - Method of programming flash memory device: At the time of a program of a NAND flash memory device, a re-program is performed on a cell connected to the last word line after program and program verification are completed. Thus, threshold voltage distributions of the cell connected to the last word line can be controlled to have... Agent: Marshall, Gerstein & Borun LLP

20070263451 - Method of verifying flash memory device: A method of verifying a flash memory device includes discharging memory cell strings respectively connected to an even bit line and an odd bit line. Next, a voltage is applied to the memory cell strings respectively connected to the even bit line and the odd bit line, thus precharging the... Agent: Marshall, Gerstein & Borun LLP

20070263453 - Method and apparatus for generating read and verify operations in non-volatile memories: Method and apparatus for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current wherein a voltage derived from the first... Agent: Trask Britt, P.C./ Micron Technology

20070263454 - Maintenance operations for multi-level data storage cells: Systems and methods, including computer software, for reading data from a flash memory cell involve detecting voltages from a group of memory cells. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from a plurality of... Agent: Fish & Richardson P.C.

20070263455 - Iterative memory cell charging based on reference cell value: Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group... Agent: Fish & Richardson P.C.

20070263456 - Inverter non-volatile memory cell and array system: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be... Agent: Merchant & Gould PC

20070263457 - Flash memory device and erase method thereof: A flash memory device and an erase method thereof, in which the size of a memory cell block can be selectively changed during an erase operation. The flash memory device includes a plurality of memory cell blocks, an X-decoder, and a plurality of block selection units. The X-decoder decodes block... Agent: Lowe Hauptman Ham & Berner, LLP

20070263458 - Memory device including multiplexed inputs: Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by... Agent: Carr & Ferrell LLP

20070263459 - Method and apparatus for output driver calibration: An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by generating a first variable count in response to comparing a reference voltage to a first voltage at a calibration terminal when an external load is connected. A first pull-up impedance circuit... Agent: Trask Britt, P.C./ Micron Technology

20070263460 - Dll with reduced size and semiconductor memory device including dll and locking operation method of the same: A DLL with a reduced size, a semiconductor memory device including the DLL and a locking operation method of the DLL that includes a phase detector, a delay line, a delay controller, a delay circuit and an output buffer. The phase detector detects phase difference between input clock signals and... Agent: Lowe Hauptman Ham & Berner, LLP

20070263461 - Methods and devices for preventing data stored in memory from being read out: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.... Agent: Harness, Dickey & Pierce, P.L.C

20070263462 - Nand architecture memory devices and operation: Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory... Agent: Leffert Jay & Polglaze, P.A.

20070263463 - Low power rom: A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word lines, a column decoder for selecting a desired bit line of the plurality of... Agent: Townsend And Townsend And Crew, LLP

20070263464 - Independent polling for multi-page programming: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required... Agent: Schwegman, Lundberg & Woessner, P.A.

20070263465 - Precharge circuit of semiconductor memory apparatus: Disclosed is a precharge circuit of a semiconductor apparatus. The precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal,... Agent: Venable LLP

20070263466 - Semiconductor memory device: When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge... Agent: Mcdermott Will & Emery LLP

20070263467 - Row address control circuit in semiconductor integrated circuit and method of controlling row address using the same: Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank active signal to generate a bank active pulse signal; a refresh mode input circuit combining the bank active pulse signal... Agent: Venable LLP

20070263468 - Internal voltage generation circuit for semiconductor device: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first... Agent: Blakely Sokoloff Taylor & Zafman

20070263469 - Two levels of voltage regulation supplied for logic and data programming voltage of a memory device: Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash... Agent: Fish & Richardson P.C.

20070263470 - Techniques for reducing leakage current in memory devices: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is... Agent: Fletcher Yoder (micron Technology, Inc.)

20070263471 - Circuit and method for reducing power in a memory device during standby modes: A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes... Agent: Trask Britt, P.C./ Micron Technology

20070263472 - Process environment variation evaluation: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of... Agent: Hoffman, Warnick & D'alessandro LLC

20070263473 - Dual mode digital multimedia connector: The present disclosure relates to a portable storage device that can communicate with different types of host devices. In some embodiments, the portable storage device receives digital media content via a multi-mode device port and exports a derivative of the digital media content (for example, a media stream) via the... Agent: Mark M. Friedman

20070263474 - Memory with level shifting word line driver and method thereof: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having... Agent: Larson Newman Abel Polansky & White, LLP

20070263475 - Using common mode differential data signals of ddr2 sdram for control signal transmission: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output... Agent: Cantor Colburn LLP - IBM Rochester Division

20070263476 - Methods and apparatus for inline characterization of high speed operating margins of a storage element: A method for inline characterization of at least one high speed operating margin of a storage element is provided. An output of at least one latch of the integrated circuit device is transitioned from a first output logic state to a second output logic state. The storage element is accessed... Agent: Ryan, Mason & Lewis, LLP

20070258276 - Nand flash memory with boosting: A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up... Agent: Winston & Strawn, LLP

20070258277 - Matchline sense circuit and method: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit... Agent: Mosaid Technologies Incorporated

20070258278 - Memory module and methods for making and using the same: A memory module includes a first printed circuit board, wherein some of the memory chips in each of first and second ranks of memory chips are assembled on one side of the printed circuit board and others of the first and second ranks are assembled on the other side of... Agent: Edell, Shapiro & Finnan, LLC

20070258279 - Thin film phase-change memory: A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If... Agent: Stout, Uxa, Buyan & Mullins LLP

20070258280 - Securing an integrated circuit: Securing an integrated circuit, including fabricating the integrated circuit to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and setting, by the security circuitry when power is first applied... Agent: Ibm (roc-blf)

20070258281 - Magnetic memory device: A magnetic memory device comprises a magnetic tunnel junction (MTJ) having a ferromagnetic free layer, and exhibits a first, relatively high resistance state, and a second, relatively low resistance state. To write to the magnetic memory device a current IMTJ is driven through the MTJ. For a first duration, the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070258282 - Magnetic memory device and method of writing data in the same: A magnetic memory device includes a magnetoresistance element which has first and second ends. First data is written into the magnetoresistance element by an electric current flowing from the first end to the second end. Second data is written into the magnetoresistance element by an electric current flowing from the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070258283 - Magnetic memory device, method for writing magnetic memory device and method for reading magnetic memory device: The magnetic memory device comprises: a memory cell including two magnetoresistive effect elements serially connected to each other, and a select transistor connected to a connection node between the two magnetic resistant devices, a bit line connected to the connection node of the magnetoresistive effect elements via the select transistor,... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070258284 - Methods and apparatus for thermally assisted programming of a magnetic memory device: A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so... Agent: Baker & Mckenzie LLP Patent Department

20070258285 - Non-volatile memory: A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-variable region comprises a first semiconductor layer of a... Agent: Rabin & Berdo, PC

20070258286 - Boosting methods for nand flash memory: A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up... Agent: Winston & Strawn, LLP

20070258288 - Flash programmer for programming nand flash and nor/nand combined flash: A method and system for implementing NAND programming of flash devices during in-circuit testing is described. A flash programmer may receive a program file from an in-circuit tester and device information from a NAND flash device, including information regarding bad cells. The flash programmer converts the program file to account... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070258287 - Mimicking program verify drain resistance in a memory device: A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified Vpass voltage that is determined in response to a predetermined drain resistance. In one embodiment, the... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20070258289 - Method of programming and erasing a p-channel be-sonos nand flash memory: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070258290 - Systems and methods for improved programming of flash based devices: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device... Agent: Baker & Mckenzie LLP Patent Department

20070258291 - Methods and apparatus for implementing bit-by-bit erase of a flash memory device: A NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate the NAND Flash memory device. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable a bit-by-bit programming... Agent: Baker & Mckenzie LLP Patent Department

20070258292 - Data/strobe encoding scheme circuit and data/strobe encoding method: In a data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through different lines, changes respectively in the data and the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a succeeding-stage circuit operating on a second clock... Agent: Sughrue Mion, PLLC

20070258293 - Data output circuit for semiconductor memory apparatus: A plurality of first drivers outputs a plurality of data based on first control signals. A second driving unit generates a second control signal synchronized with data output cycles of the first drivers using the first control signals. An amplitude correcting unit corrects an amplitude of the second control signal... Agent: Venable LLP

20070258294 - Semiconductor storage apparatus: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing into the memory cells is requested.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070258295 - Method of high-performance flash memory data transfer: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data... Agent: Anderson, Levine & Lintel L.L.P.

20070258297 - Method and apparatus for accessing nonvolatile memory with read error by changing read reference: The read reference of a nonvolatile memory integrated circuit is changed in response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070258296 - Method and apparatus for in-system redundant array repair on integrated circuits: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing... Agent: Scully Scott Murphy & Presser, PC

20070258298 - Parallel programming of flash memory during in-circuit test: A method and system for parallel programming flash devices during in-circuit testing is described. A parallel processing device is located in a test fixture of an In-Circuit Tester (ICT) for each printed circuit board (PCB) connected to the test fixture. The parallel processing device controls the communications between the ICT... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070258299 - Semiconductor memory apparatus having noise generating block and method of testing the same: Disclosed are a semiconductor memory apparatus and a method of testing the same. The semiconductor memory apparatus includes memory banks, each of which includes a plurality of memory cells, a peripheral circuit unit that includes a plurality of circuit groups around the memory banks, and a noise generating block that... Agent: Venable LLP

20070258300 - Functional verification of synchronized signals using random delays: A method and system for verifying synchronized signals if provided. The method may include receiving a signal from a first clock domain for synchronization. Further, a random number for the received signal may be generated and a reset signal imposed for utilization as a reference point for the received signal... Agent: Lsi Corporation

20070258301 - Reading circuit for semiconductor memory: A reading circuit for reading semiconductor memory cells, adapted to be coupled to at least one memory cell and to at least one reference cell through a respective bit line, the reading circuit including: a pre-charge circuit for pre-charging the bit lines to a predefined voltage during a pre-charge phase... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070258302 - Negative voltage discharge scheme to improve snapback in a non-volatile memory: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The... Agent: Dickstein Shapiro LLP

20070258303 - Semiconductor memory device: A semiconductor memory device including a memory cell array which has a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs which transfer data among the memory cells, a sense amplifier bank which includes a plurality of sense amplifiers, the plurality of sense amplifiers... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070258304 - Method and system for preventing noise disturbance in high speed, low power memory: A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the signal from the sense amplifier. A first source of timing signals generates a first timing signal... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070258306 - Method for refreshing a non-volatile memory: A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an... Agent: Honeywell International Inc.

20070258305 - Determining relative amount of usage of data retaining device based on potential of charge storing device: A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device.... Agent: Hoffman, Warnick & D'alessandro LLC

20070258307 - Memory circuit and method for refreshing dynamic memory cells: A memory circuit comprises a memory cell array with dynamic memory cells arranged on word lines and bit lines, a selection unit providing selection information and a refresh circuit selecting the memory cells in each case in dependence on the selection information and refreshing the selected memory cells so that... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070258308 - Software refreshed memory device and method: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory... Agent: Dickstein Shapiro LLP

20070258311 - Mos electric fuse, its programming method, and semiconductor device using the same: A programming method of a MOS electric fuse including preparing, as a fuse element, a MOS transistor which has a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070258309 - Securing an integrated circuit: Securing an integrated circuit, including fabricating the integrated circuit so that the integrated circuit includes at least one efuse that is intended to be always blown during operation of the integrated circuit and the integrated circuit includes security circuitry capable of blowing the efuse and of performing other security related... Agent: Ibm (roc-blf)

20070258310 - Semiconductor integrated circuit: There is provided a fuse module that holds trimming information for an internal oscillation circuit module. The fuse module includes information-writing fuse circuits to which trimming information is written depending on whether an information-writing fuse is blown; a reference fuse circuit for determining whether the information-writing fuse has been blown;... Agent: Miles & Stockbridge PC

20070258312 - Memory cell array with multiple drivers: Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are provided with a plurality of wordlines. Memory cells of the row are activated and updated by separated wordlines. In an application of display... Agent: Texas Instruments Incorporated

20070258313 - Dual port random-access-memory circuitry: Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port... Agent: G. Victor Treyz

20070258314 - Driving method based on a binary architecture: A driving method for driving a peripheral device, based on a binary architecture, includes loading a description file by the middleware according to the device ID of the peripheral device; parsing the description file to generate driving instructions by the middleware; and driving the peripheral device by the driving instructions,... Agent: Pai Patent & Trademark Law Firm

20070253232 - Storage apparatus, and method for performing fault recovery of storage apparatus: The storage apparatus includes a plurality of storage devices for storing information, a control unit controlling the storage device, a switching unit switching a connection between the storage device and the control unit, and a network different from the connection by the switching unit and connecting the storage device and... Agent: Staas & Halsey LLP

20070253236 - Semiconductor memory device comprising memory element programming circuits having different programming threshold power supply voltages: A semiconductor memory device has first and second AF programming circuits having low and high AF programming threshold power supply voltages, respectively. In a process where a large majority of programming is carried out in the semiconductor memory device alone, the second AF programming circuit is used. In a module... Agent: Mcginn Intellectual Property Law Group, PLLC

20070253234 - Memory array with readout isolation: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external... Agent: Goodwin Procter LLP Patent Administrator

20070253233 - Semiconductor memory device and method of production: A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that... Agent: Slater & Matsil LLP

20070253235 - Low-voltage ic-circuit: The invention regards an IC-circuit construction where the circuit is partitioned into power consuming sub-circuits (1,6) and where ground voltage level (VHH) in the power supply of a first sub-circuit (1) is used as the supply voltage level in a second sub-circuit (6). According to the invention a voltage control... Agent: Birch Stewart Kolasch & Birch

20070253237 - Semiconductor memory with resistance change element: A semiconductor memory includes a memory cell as a resistance change element and a switching element which are connected in series and a read word line connected to a control terminal of the switching element. In addition, the semiconductor memory includes a circuit which executes an auto-close operation for causing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070253238 - Semiconductor memory device with information loss self-detect capability: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070253240 - Fault tolerant asynchronous circuits: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.... Agent: Jlb Consulting, Inc. C/o Intellevate

20070253239 - Read-preferred sram cell design: A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and... Agent: Slater & Matsil, L.L.P.

20070253241 - Method for accessing data on magnetic memory: A method for accessing data on a magnetic memory is provided, wherein the data is accessed in a toggle mode. A first current line and a second current line are used for providing operation currents. The data accessing method includes a data changing operation for changing a data stored in... Agent: Jianq Chyun Intellectual Property Office

20070253242 - Page mode access for non-volatile memory arrays: An array of non-volatiel memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry... Agent: Dykas, Shaver & Nipper, LLP

20070253245 - High capacity low cost multi-stacked cross-line magnetic memory: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.... Agent: Law Offices Of Imam

20070253244 - Magnetic random access memory: An apparatus and methods for a non-volatile magnetic random access memory (MRAM) device that includes a word line, a bit line, and a magnetic thin film memory element located at an intersection of the word and bit lines. The magnetic thin film memory element includes an alloy of a rare... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070253243 - Memory array having memory cells formed from metallic material: Solid-state memories are disclosed that are comprised of cross-point memory arrays. The cross-point memory arrays include a first plurality of electrically conductive lines and a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines. The memory arrays also include a plurality of memory... Agent: Duft Bornsen & Fishman, LLP

20070253246 - Thin film magnetic memory device provided with program element: A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external-laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a... Agent: Mcdermott Will & Emery LLP

20070253247 - Non-volatile memory device with single transistor memory cell: A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell includes a floating gate transistor having a control gate, a floating gate separated dielectrically from the control gate, a drain connection and a source connection.... Agent: Davidson, Davidson & Kappel, LLC

20070253249 - Multi-bit nonvolatile memory device and related programming method: In a method of programming a nonvolatile memory device comprising a plurality of n-valued nonvolatile memory cells arranged in a matrix, wherein n is a natural number greater than or equal to two (2), the method comprises; programming i-valued data to three or more memory cells contiguously arranged along a... Agent: Volentine & Whitt PLLC

20070253250 - Semiconductor memory device which stores plural data in a cell: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3).... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070253251 - Ic module and cellular phone: In a SIM card having a flash memory chip, a memory controller chip, and contact/contactless card interfaces, the memory controller chip has a function of executing user authentication of a host equipment, executes processing of data transmitted through the contactless IC card interface (executing reading or writing of data to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070253252 - Memory cell repair using fuse programming method in a memory device: A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of defective memory cells of the main array are determined. These locations are stored in the fuse memory cells by erasing predetermined locations in... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20070253253 - Multiple select gates with non-volatile memory cells: Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series... Agent: Brooks, Cameron & Huebsch , PLLC

20070253254 - Non-volatile semiconductor memory device: 2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070253248 - Method for programming a reference cell: A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference... Agent: Empk & Shiloh, LLP

20070253255 - Memory device, method for sensing a current output from a selected memory cell and sensing circuit: A memory device, a method for sensing a current output and a sensing circuit are disclosed. In one embodiment, a first voltage is supplied at least to a drain and a source terminal of a neighboring memory cell before sensing, and the first voltage is applied to a source terminal... Agent: Dicke, Billig & Czaja

20070253256 - Memory voltage cycle adjustment: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an... Agent: Edward J. Brooks Iii Brooks & Cameron, PLLC

20070253257 - Electrically alterable non-volatile memory cells and arrays: Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in... Agent: Chih-hsin Wang

20070253258 - Methods to resolve hard-to-erase condition in charge trapping non-volatile memory: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070253259 - Recording device and hdd built-in recording device: Disclosed are a recording device and an HDD built-in recording device each of which can curtail a use area of nonvolatile memory to be used even with the nonvolatile memory having a limit in the number of times of rewriting. In this HDD built-in recording device, a microcomputer 14 judges... Agent: Yokoi & Co., U.s.a., Inc.

20070253260 - Integrating the internet system of mediation of financial loans, purchase of goods and providing services: An Internet based system and method for mediation of financial loans, purchasing goods and providing services between consumers and providers which employs a mediator therebetween. The system employs a public communication network such as the Internet, to interconnect at least one mediator between at least one creditor, and a client.... Agent: Donn K. Harms Patent & Trademark Law Center

20070253261 - Electronic device, data transfer controlling program thereof, and circuit chip: The present invention relates to data transfer to an external storage device disposed on or connected to an electronic device and can accelerate the data transfer. The present invention relates to an electronic device (portable terminal device) connected or disposed with an external storage device, includes a transmission channel connected... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070253262 - Method and apparatus for early write termination in a semiconducutor memory: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive... Agent: Coats & Bennett/qimonda

20070253264 - Integrated semiconductor memory with a test function and method for testing an integrated semiconductor memory: An integrated semiconductor memory with a test function comprises a bit line pair having a first end and a second end. A voltage generation circuit having a first connection and a second connection is coupled to the first end of the bit line pair. A plurality of memory cells are... Agent: Slater & Matsil, L.L.P.

20070253263 - Nonvolatile memory device with test mechanism: A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a... Agent: Richard P. Berg, Esq. C/o Ladas & Parry

20070253265 - Bitline leakage limiting with improved voltage regulation: Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging period, voltage on the bitlines is regulated with the second regulation... Agent: Edell, Shapiro & Finnan, LLC

20070253266 - Semiconductor device and programming method: The present invention provides a semiconductor device and a control method thereof, the semiconductor device including: a bit line connected to a memory cell; a voltage control circuit controlling a voltage supplied from a voltage source to the bit line; a differential amplifier circuit providing the control voltage to the... Agent: Murabito, Hao & Barnes LLP

20070253267 - Semiconductor memory device: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting... Agent: Sughrue Mion, PLLC

20070253270 - Semiconductor memory device performing self refresh operation: The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command... Agent: Blakely Sokoloff Taylor & Zafman

20070253269 - Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are... Agent: Borden Ladner Gervais LLP

20070253268 - Dynamic random access memory with fully independent partial array refresh function: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing.... Agent: Smart & Biggar P.o. Box 2999, Station D

20070253271 - Refresh period generating circuit: A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature;... Agent: Mcdermott Will & Emery LLP

20070253273 - Memory: A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage... Agent: Ditthavong Mori & Steiner, P.C.

20070253274 - Memory: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first... Agent: Ditthavong Mori & Steiner, P.C.

20070253272 - Semiconductor memory device capable of executing high-speed read: A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070253275 - Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic: Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is... Agent: Ibm Corporation (jvm)

20070253276 - Method of preventing dielectric breakdown of semiconductor device and semiconductor device preventing dielectric breakdown: A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit. The semiconductor device may further include a seal... Agent: Oliff & Berridge, PLC

20070253277 - Semiconductor integrated circuit device, data processing system and memory system: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and... Agent: Stanley P. Fisher Reed Smith LLP