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Static information storage and retrieval October listing of patent apps 10/07

20070247885 - Content addressable memory: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than... Agent: Mcdermott Will & Emery LLP

20070247887 - Semiconductor device having non-volatile memory and method of fabricating the same: A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell transistor gates of first and second memory... Agent: Mills & Onello LLP

20070247884 - Attribute cache memory: A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a subset of a memory address, the word decoder... Agent: Zilka-kotab, PC

20070247886 - Memory circuit: A memory includes a plurality of memory arrays. Each of the plurality of memory arrays includes a plurality of sub-arrays. A plurality of power supply conductors are provided over the memory for supplying power to the plurality of memory arrays. When accessing the memory to simultaneously read a plurality of... Agent: Freescale Semiconductor, Inc. Law Department

20070247888 - Non-volatile memory cell: A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal... Agent: Larson Newman Abel Polansky & White, LLP

20070247889 - Semiconductor memory device: A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly... Agent: Wenderoth, Lind & Ponack L.L.P.

20070247890 - Nano-vacuum-tubes and their application in storage devices: The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.... Agent: Goodwin Procter LLP Patent Administrator

20070247891 - Over-driven access method and device for ferroelectric memory: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070247894 - Method of driving storage device: A method of driving a storage device including a variable resistance element in which resistance value is changed reversibly between a high resistance state and a low resistance state by applying voltages with different polarities between two electrodes is provided. The storage device includes a plurality of memory cells formed... Agent: Bell, Boyd & Lloyd, LLP

20070247892 - Circuit and a method of determining the resistive state of a resistive memory cell: A method and a circuit are disclosed for determining the resistive state of a resistive memory cell being read. The method includes determining the resistive state of the memory cell being read by comparing a current dependent on the resistive state of the memory cell being read with a reference... Agent: Dicke, Billig & Czaja

20070247895 - Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is... Agent: Dickstein Shapiro LLP

20070247893 - Non-volatile memory architecture employing bipolar programmable resistance storage elements: A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of... Agent: Ryan, Mason & Lewis, LLP

20070247896 - Static random access memory cell with improved stability: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and... Agent: Ryan, Mason & Lewis, LLP

20070247897 - Partitioned random access and read only memory: A magnetic memory and a method of operating the memory are described. The memory includes memory cells that may each include a magnetoresistive bit. The memory cells may each be coupled to a current driver. Each current driver may be inhibited so that it does not output a current. Inhibiting... Agent: Honeywell International Inc.

20070247898 - Memory having storage locations within a common volume of phase change material: A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change material for accessing a second storage... Agent: Dicke, Billig & Czaja

20070247899 - Programming a normally single phase chalcogenide material for use as a memory or fpla: A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the... Agent: Trop Pruner & Hu, PC

20070247900 - 3-parameter switching technique for use in mram memory arrays: Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070247901 - Mesoscopic magnetic body having circular single magnetic domain structure, its production method, and magnetic recording device using the same: The present invention provides a mesoscopic magnetic body comprising a tabular ferromagnetic body whose planar shape has an axis of symmetry, but which is not symmetric in the direction perpendicular to the axis of symmetry, and wherein the magnetic body shows a circular single domain structure upon removal of the... Agent: Klarquist Sparkman, LLP

20070247902 - Method for operating a single-poly single-transistor non-volatile memory cell: A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM... Agent: North America Intellectual Property Corporation

20070247904 - Nano-enabled memory devices and anisotropic charge carrying arrays: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the... Agent: Nanosys Inc.

20070247905 - Method and apparatus to protect nonvolatile memory from viruses: An apparatus, system, method, and article for protecting nonvolatile memory from viruses are described. The apparatus may include a nonvolatile memory comprising one or more protected storage areas. The nonvolatile memory may be arranged to transform buffered information to be programmed in the protected areas and to program transformed information... Agent: Kacvinsky LLC C/o Intellevate

20070247906 - Fin type memory cell: A Fin-type memory cell according to an example of the present invention includes a fin-shaped active area, a floating gate along a side surface of the fin-shaped active area, and two control gate electrodes arranged in a longitudinal direction of the fin-shaped active area, and sandwiching the floating gate.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070247907 - Reduction of leakage current and program disturbs in flash memory devices: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a negative substrate bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. The... Agent: Ingrassia Fisher & Lorenz, P.C.

20070247911 - Method of measuring a channel boosting voltage in a nand flash memory device: In a method of measuring a channel boosting voltage, a threshold voltage of a pass disturbance is measured in accordance with change of a pass voltage applied to a selected cell under the condition that the pass voltage having a certain level is provided to a cell not selected of... Agent: Townsend And Townsend And Crew, LLP

20070247912 - Semiconductor memory device improved in data writing: A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070247909 - Method and system for flash memory devices: Method and system for memory devices is provided. The system includes a plurality of non-volatile storage elements connected in a string between a source side element and a drain side element; a plurality of bit lines, wherein each bit line is connected to a plurality of non-volatile storage elements; and... Agent: Klein, O'neill & Singh, LLP

20070247913 - Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device: Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper... Agent: Buchanan, Ingersoll & Rooney PC

20070247910 - Nand erase block size trimming apparatus and method: A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string. The separator elements can be... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20070247908 - Read operation for nand memory: Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070247915 - Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for a general-purpose cmos technology with thick gate oxide: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The... Agent: Fliesler Meyer LLP

20070247914 - Non-volatile memory in cmos logic process and method of operation thereof: A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070247916 - Systems for variable reading in non-volatile memory: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are... Agent: Vierra Magen/sandisk Corporation

20070247917 - Method for programming a memory device suitable to minimize floating gate coupling and memory device: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said... Agent: Graybeal Jackson Haley LLP

20070247903 - Reading circuit and method for a nonvolatile memory device: Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20070247918 - Semiconductor integrated circuit: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold... Agent: Miles & Stockbridge PC

20070247920 - Data processing apparatus: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After... Agent: Miles & Stockbridge PC

20070247919 - Non-volatile memory architecture and method, in particular of the eeprom type: A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix.... Agent: Graybeal, Jackson, Haley LLP

20070247921 - Scalable high performance non-volatile memory cells using multi-mechanism carrier transport: A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070247922 - A reliable method for erasing a flash memory: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the... Agent: Jianq Chyun Intellectual Property Office

20070247925 - Method for programming multi-level nitride read-only memory cells: A method of programming data regions in a nitride read-only memory cell that, in an erased state, exhibits a low Vt value by first programming a data region that is to be programmed to a highest Vt value. Remaining data regions in the nitride read-only memory cell are programmed in... Agent: Stout, Uxa, Buyan & Mullins LLP

20070247923 - Methods for erasing and programming memory devices: A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for... Agent: Ingrassia Fisher & Lorenz, P.C.

20070247924 - Methods for erasing memory devices and multi-level programming memory device: A memory includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions into a substrate to erase the... Agent: Ingrassia Fisher & Lorenz, P.C.

20070247926 - Rfid device having nonvolatile ferroelectric memory device: An RFID device is provided to perform a pumping operation when a read or write operation of a memory cell is performed to reduce current consumption. The RFID device includes an analog block, a digital block, and a memory block including at least one ferroelectric capacitor, and a voltage pumping... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070247927 - Data generator having stable duration from trigger arrival to data output start: A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal... Agent: William K. Bucher Tektronix, Inc.

20070247928 - Flash memory device: A flash memory device includes a normal memory cell array for storing data, a normal page buffer for inputting data to the normal memory cell array or reading data stored in the normal memory cell array, one or more reference memory cell blocks for storing reference data, one or more... Agent: Townsend And Townsend And Crew, LLP

20070247929 - Memory device and method of operating such: A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070247930 - Dual chip package: The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage;... Agent: Volentine & Whitt PLLC

20070247931 - Internal voltage generator for a semiconductor memory apparatus: An internal voltage generator for a semiconductor memory apparatus, including: a reference voltage generator that outputs a reference voltage. A driver controller receives the reference voltage and generating a driver control signal using the reference voltage. An amplifier circuit amplifies the driver control signal. And, a driver outputs an internal... Agent: Venable LLP

20070247932 - Shift register circuit and image display comprising the same: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070247934 - High-performance flash memory data transfer: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data... Agent: Anderson, Levine & Lintel L.L.P.

20070247933 - Method of high-performance flash memory data transfer: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data... Agent: Anderson, Levine & Lintel L.L.P.

20070247935 - Clocked memory system with termination component: A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to... Agent: Shemwell Mahamedi LLP

20070247937 - Information processing system for calculating the number of redundant lines optimal for memory device: An information processing system of the invention has a database in which test results for a plurality of memory devices mounted on a wafer are stored and a computer for analyzing the test results. The computer includes a data retrieval section for retrieving a test result from the database; and... Agent: Sughrue Mion, PLLC

20070247936 - Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture: An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit... Agent: Texas Instruments Incorporated

20070247938 - Separate sense amplifier precharge node in a semiconductor memory device: A method and memory device are provided in which sense nodes of a sense amplifier in a semiconductor memory device are internally precharged independent of equalize and precharge operations on bitlines of a memory array associated with the sense amplifier.... Agent: Edell, Shapiro & Finnan, LLC

20070247942 - Circuit and method for controlling sense amplifier of semiconductor memory apparatus: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense... Agent: Venable LLP

20070247940 - High speed sensing amplifier for an mram cell: A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070247939 - Mram array with reference cell row and methof of operation: A magnetoresistive random access memory (MRAM) avoids difficulties with write disturb by electrically isolating the portion of the array with data from the portion with reference signals while providing fast read speeds by simultaneously enabling the word line having the reference cells and the selected word line. For high speed... Agent: Freescale Semiconductor, Inc. Law Department

20070247941 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070247943 - Magnetic memory device and method for reading the same: A magnetic memory device comprises a plurality of bit lines BL; memory cells MC disposed at the respective plurality of bit lines, and each including a magnetoresistive effect element MTJ whose resistance value is changed with changes of magnetization direction, and a select transistor Tr connected to the magnetoresistive effect... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070247944 - Integrated semiconductor memory with refreshing of memory cells: An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored... Agent: Edell, Shapiro & Finnan, LLC

20070247946 - Bulk erase tool: A bulk erase tool is provided. The bulk erase tool includes first polarity top and bottom main erase magnets. Additionally, the bulk erase tool includes second polarity top and bottom main erase magnets. The bulk erase tool also includes first polarity top and bottom cancel magnets at portions of the... Agent: Wagner, Murabito & Hao LLP Two North Market Street

20070247948 - Bulk erase tool for erasing perpendicularly recorded media: A bulk erase tool for erasing perpendicularly recorded media is provided. The bulk erase tool includes a first polarity erase magnet and a second polarity erase magnet offset from the first polarity erase magnet. In so doing, the offset between the first polarity erase magnet and the second polarity erase... Agent: Wagner, Murabito & Hao LLP

20070247945 - Method for providing a bulk erase tool having a portion of reduced field strength: A method for providing a bulk erase tool having a portion of reduced field strength is provided. A bulk erase tool is received. The bulk erase tool has a first polarity top main magnet, a first polarity bottom main magnet, a second polarity top main magnet and a second polarity... Agent: Wagner, Murabito & Hao LLP

20070247947 - Method for utilizing a bulk erase tool to erase perpendicularly recorded media: A method for utilizing a bulk erase tool to erase perpendicularly recorded media is provided. A bulk erase tool having a first polarity erase magnet and a second polarity erase magnet is received. An offset is provided between the first polarity erase magnet and the second polarity erase magnet, wherein... Agent: Wagner, Murabito Hao LLP Third Floor

20070247949 - Semiconductor memory device and refresh method for the same: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even... Agent: Arent Fox PLLC

20070247950 - Memory device with reduced stand-by mode power consumption: The present invention discloses a memory device. In one embodiment of the present invention, the memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines. At least one word line decoder is coupled to the word... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070247951 - Semiconductor memory apparatus capable of reducing ground noise: A semiconductor memory apparatus includes a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array, a ground power supply pad that is supplied with a ground power through a ground line, a switch that connects the... Agent: Venable LLP

20070247952 - Semiconductor memory device and semiconductor integrated circuit device: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections... Agent: Miles & Stockbridge PC

20070247953 - Memory control method and apparatuses: A memory control method, a memory controller, and a memory device implementing the method are provided. The memory controller controls the memory device comprising a plurality of banks, and a first row in a bank is activated for access. The memory controller receives a request for access of a second... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070247954 - Memory device with shared reference and method: A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for... Agent: Davidson, Davidson & Kappel, LLC

20070247955 - Method for initializing a memory: A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the... Agent: Seed Intellectual Property Law Group PLLC

20070247956 - Semiconductor memory device: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the... Agent: Arent Fox PLLC

20070247958 - Column selection signal generator for semiconductor memory: A column selection signal generator includes a timing generating unit that enables a column selection signal using a read or write command at timing according to a time control signal, a timing control unit that generates the timing control signal to control the enable timing of the column selection signal,... Agent: Venable LLP

20070247959 - Semiconductor memory device: With a semiconductor memory device according to the invention, it is possible to perform level shift of a word driver by a change in voltage at a line for a word driver P-channel control signal connected to a P-channel transistor, without a change in size of the P-channel transistor and... Agent: Steptoe & Johnson LLP

20070247957 - Method for generating and adjusting selected word line voltage: A method for generating a selected word line voltage is provided. In this method, a constant voltage that is substantially independent of a temperature change is generated. Additionally, a current that varies in proportion to a temperature is generated. To generate the selected word line voltage, the current is converted... Agent: Winston & Strawn, LLP

20070247961 - Memory controller with staggered request signal output: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in... Agent: Shemwell Mahamedi LLP

20070247962 - Semiconductor integrated circuit device, data processing system and memory system: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and... Agent: Stanley P. Fisher Reed Smith LLP

20070247960 - System and method to synchronize signals in individual integrated circuit components: A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase... Agent: Coats & Bennett/qimonda

20070247963 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242493 - Match sensing circuit for a content addressable memory device: A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all other cell match... Agent: Texas Instruments Incorporated

20070242494 - Memory array with readout isolation: Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.... Agent: Goodwin Procter LLP Patent Administrator

20070242495 - Programmable read-only memory: A programmable read-only memory comprises a memory cell or a plurality of such cells arranged as an array. Each memory cell comprises a transistor, such as a MOS TFT. An electronic switch allows the control electrode, such as the gate, to be substantially electrically isolated during a programming mode so... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20070242496 - Nor and nand memory arrangement of resistive memory elements: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory... Agent: Edell, Shapiro & Finnan, LLC

20070242497 - Dynamic control of back gate bias in a finfet sram cell: The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based... Agent: Hoffman, Warnick & D'alessandro LLC

20070242499 - Semiconductor integrated circuit device and trimming method of semiconductor integrated circuit device: This disclosure concerns a LSI comprising two bit lines; two input nodes; sense nodes transmitting a signal difference input to the two input nodes; an output node outputting the amplified signal; a current adjustment gate adjusting an amount of current flowing through one of the two sense nodes; a latch... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242498 - Sub-threshold static random access memory: A static random access memory is configured for operation at sub-threshold voltage levels. A bistable circuit is supplemented by buffer circuitry configured to improve read performance and float circuitry to improve write performance.... Agent: James W. Wiegand

20070242502 - Memory element and memory: A memory element is provided. The memory element includes a memory layer that retains information based on a magnetization state of a magnetic material, in which a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons... Agent: Bell, Boyd & Lloyd, LLP

20070242501 - Structure and access method for magnetic memory cell and circuit of magnetic memory: A magnetic memory cell, used in a magnetic memory device, includes a stacked magnetic pinned layer, serving as a part of the base structure. The stacked magnetic pinned stacked layer has a top pinned layer and a bottom pinned layer, between which there is a sufficient large magnetic coupling force... Agent: Jianq Chyun Intellectual Property Office

20070242500 - Method and apparatus providing high density data storage: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material... Agent: Dickstein Shapiro LLP

20070242503 - Phase change memory device using multiprogramming method: A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver... Agent: Volentine & Whitt PLLC

20070242504 - Shunted phase change memory: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions... Agent: Trop Pruner & Hu, PC

20070242505 - Magnetic memory device and method for driving the same: The magnetic memory device comprises a magnetoresistive effect element 54 including a magnetic layer 42 having a magnetization direction pinned in a first direction, a non-magnetic layer 50 formed on the magnetic layer 42, and a magnetic layer 52 formed on the non-magnetic layer 50 and having a first magnetic... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070242506 - Semiconductor memory device storing redundant replacement information with small occupation area: Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the... Agent: Leydig Voit & Mayer, Ltd

20070242507 - Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage... Agent: Hoffman, Warnick & D'alessandro LLC

20070242508 - Low power balance code using data bus inversion: A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data... Agent: Lee & Morse, P.C.

20070242509 - Apparatus for reducing the impact of program disturb during read: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation

20070242511 - Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same: An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the... Agent: Zagorin O'brien Graham LLP (023)

20070242510 - Reducing the impact of program disturb during read: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation

20070242512 - Non-volatile semiconductor memory devices with lower and upper bit lines sharing a voltage control block, and memory cards and systems having the same: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common... Agent: Myers Bigel Sibley & Sajovec

20070242513 - Static random access memory (sram) cells: The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless,... Agent: Hoffman, Warnick & D'alessandro LLC

20070242515 - Multiple select gate architecture with select gates of different lengths: The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled... Agent: Leffert Jay & Polglaze, P.A.

20070242514 - Nand-structured nonvolatile memory cell: A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory... Agent: Townsend And Townsend And Crew, LLP

20070242517 - Nonvolatile semiconductor memory device which stores multivalue data: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242516 - Semiconductor storage apparatus: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: cell arrays, each having a plurality of memory cells connected to a pair of first and second bit lines; and sense amplifiers, each being provided corresponding to the pair of first and second bit lines and sensing... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242518 - Method for programming a block of memory cells, non-volatile memory device and memory card device: A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected... Agent: Slater & Matsil LLP

20070242519 - Method of erasing data in non-volatile semiconductor memory device while suppressing variation: According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address... Agent: Mcdermott Will & Emery LLP

20070242521 - Semiconductor flash memory: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a... Agent: Leydig Voit & Mayer, Ltd

20070242520 - Voltage regulator having a low noise discharge switch for non-volatile memories, in particular for discharging word lines from negative voltages: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070242522 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation

20070242523 - Non-volatile memory and operating method thereof: An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage... Agent: J.c. Patents, Inc.

20070242524 - Reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent: Vierra Magen/sandisk Corporation

20070242525 - Method for erasing flash memories and related system thereof: A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the... Agent: North America Intellectual Property Corporation

20070242529 - Method and apparatus for accessing contents of memory cells: The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit... Agent: Adeli Law Group, A Professional Law Corporation

20070242528 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit line, a circuit for applying a second voltage to unselected bit lines and word lines, a circuit... Agent: Nixon & Vanderhye, PC

20070242527 - Semiconductor memory device for storing multilevel data: In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242526 - Semiconductor memory and read method of the same: wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which a relationship Vd>Vg−Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070242530 - Memory controller for supporting double data rate memory and related method: A memory controller includes a first data converter for converting incoming data into a first data in which a bit width of the incoming data and a bit width of the first data corresponds to a first ratio; a second data converter for converting the incoming data into a second... Agent: North America Intellectual Property Corporation

20070242533 - Memory access apparatus: A memory access apparatus reading data from a memory, the memory including a terminal that address information is input to, a terminal that a clock signal changing at a predetermined cycle is input to, a terminal that a read command is input to, and a terminal that outputs data stored... Agent: SocalIPLaw Group LLP

20070242531 - Write apparatus for ddr sdram semiconductor memory device: A writing apparatus of a semiconductor memory device includes a pulse generator, a latch unit and an output latch unit. The pulse generator outputs a first pulse every rising edge of a data strobe pulse and a second pulse every falling edge of the data strobe pulse, respectively. The latch... Agent: Lowe Hauptman Ham & Berner, LLP

20070242532 - Integrated circuit memory device having delayed write timing based on read response time: An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070242536 - Reference potential generating circuit and semiconductor memory device having the same: A reference potential generating circuit has a current mirror amplifier (CM11) supplied with an input reference potential and a feedback level, an output transistor (QP11) supplied with an output of the current mirror amplifier as an input and producing an output reference potential as an output, a monitoring portion (R11... Agent: Mcginn Intellectual Property Law Group, PLLC

20070242534 - Memory with charge storage locations: A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected... Agent: Freescale Semiconductor, Inc. Law Department

20070242535 - Semiconductor memory device and defect remedying method thereof: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070242537 - Radiation-hardened memory element with multiple delay elements: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM... Agent: Honeywell International Inc.

20070242538 - Apparatus and methods for determining memory device faults: A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the... Agent: Barnes & Thornburg LLP

20070242539 - Semiconductor memory device: A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the... Agent: Mcdermott Will & Emery LLP

20070242540 - Semiconductor memory device with temperature sensing device and operation thereof: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage... Agent: Mcdermott Will & Emery LLP

20070242542 - Memory: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to... Agent: Mcdermott Will & Emery LLP

20070242541 - Sense amplifier with reduced current consumption for semiconductors memories: A sensing circuit for a semiconductor memory, comprising at least one detecting amplifier, said detecting amplifier comprising: a first circuital branch adapted to be electrically run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current,... Agent: Graybeal, Jackson, Haley LLP

20070242543 - Dram bitline precharge scheme: Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing phase, the voltage of one of the pair of complementary bitlines is adjusted from VDD to a reference level.... Agent: Borden Ladner Gervais LLP

20070242547 - Self refresh operation of semiconductor memory device: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to... Agent: Blakely Sokoloff Taylor & Zafman

20070242545 - Semiconductor memory device: Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a... Agent: Mcdermott Will & Emery LLP

20070242546 - Semiconductor memory device: A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes... Agent: Sughrue Mion, PLLC

20070242544 - Method and system for providing directed bank refresh for volatile memories: A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform... Agent: Qualcomm Incorporated

20070242548 - Programmable semiconductor device: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic... Agent: International Business Machines Corporation Dept. 18g

20070242550 - Device and method of controlling operation of a flash memory: A flash memory device including a non-volatile memory for storing information; a power switch for controlling operation of the non-volatile memory; and a controller that operates the power switch to alternately provide and deny power to the non-volatile memory.... Agent: Mark M. Friedman

20070242549 - System and method for controlling constant power dissipation: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined... Agent: Slater & Matsil LLP

20070242551 - User selectable banks for dram: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is... Agent: Leffert Jay & Polglaze, P.A.

20070242552 - Dual-plane type flash memory device having random program function and program operation method thereof: A dual-plane type flash memory device having a random program function and program operation method thereof. The flash memory device includes a first plane, a second plane, a first X-decoder, and a second X-decoder. The first plane includes first memory blocks sequentially arranged in a row direction. The second plane... Agent: Lowe Hauptman Ham & Berner, LLP

20070242553 - Multi-port memory device with serial input/output interface and control method thereof: A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an... Agent: Blakely Sokoloff Taylor & Zafman

20070242554 - Multi-port semiconductor device and method thereof: A multi-port semiconductor device and method thereof are provided. In an example, the multi-port memory device may include a clock generating unit receiving an external clock signal having a given frequency and a given phase, the clock generating unit generating a plurality of local clock signals by adjusting at least... Agent: Harness, Dickey & Pierce, P.L.C

20070242555 - Word-line driver for memory devices: A word-line driver has an input from a word-line decoder and an output to drive a word-line. The word-line driver comprises a plurality of inverters connected in series between the input and output including a first and a second inverter with a first node designating an output of the first... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070242556 - Semiconductor device using dynamic circuit: The present invention provides a semiconductor device having a plurality of functional blocks and a select signal generation circuit for supplying a select signal to a functional block to be operated out of the plurality of blocks. A clock generation unit in the function clock, to which the select signal... Agent: Staas & Halsey LLP

20070242557 - Control circuit of power supply unit, power supply unit and control method thereof: To provide a control circuit of power supply unit, power supply unit and control method thereof capable of setting and adjusting a voltage value of output voltage flexibly corresponding to an instruction from outside, a voltage adjusting portion AD for adjusting first voltage setting information inputted from outside to real... Agent: Arent Fox PLLC

20070236978 - Non-volatile reactive magnetic memory device (remm): The present invention introduces a solid state magnetic memory concept which is based on the different inductive reactance an inductance composed of a conductor wire surrounded by magnetic material exhibits at different parts of its magnetization curve. A current pulse is used to either read or write the logic information... Agent: Jannier M. Roiz

20070236979 - Nonvolatile ferroelectric memory: According to an aspect of the invention, there is provided a nonvolatile ferroelectric memory, including a ferroelectric capacitor composed of a ferroelectric film sandwiched by capacitor electrodes made of a conductive material, a cell capacitor block stacked a plurality of the capacitor electrodes and the ferroelectric film of the ferroelectric... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236980 - Ferroelectric random access memory: Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one end side in a column direction every four cell blocks sequentially adjacent to each... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236981 - Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse: A nonvolatile memory cell includes a layer of a resistivity-switching metal oxide or nitride compound, the metal oxide or nitride compound including one metal, and a dielectric rupture antifuse formed in series. The dielectric rupture antifuse may be either in its initial, non-conductive state or a ruptured, conductive state. The... Agent: Patent Dept., Sandisk Corporation

20070236985 - Semiconductor memory device: A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts serving as information cells used for storing data, the remaining parts as reference cells used for driving a reference current; three or more bit line... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236982 - Asymmetrical memory cells and memories using the cells: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control... Agent: Ryan, Mason & Lewis, LLP

20070236983 - Integrated circuit memory with write assist: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as... Agent: Nixon & Vanderhye, PC

20070236984 - Sram with read assist: A Static Random Access Memory (SRAM) matrix with a read assist is described. The read assist reduces the probability associated with an SRAM matrix becoming upset by a radiation event. Each SRAM cell within the SRAM matrix includes an active delay for increasing Single Event Upset (SEU) tolerance. The described... Agent: Honeywell International Inc.

20070236986 - Voltage controlled static random access memory: A design structure comprising a static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240′, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as... Agent: Downs Rachlin Martin PLLC

20070236987 - Phase change memory devices and systems, and related programming methods: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied... Agent: Volentine & Whitt PLLC

20070236989 - Common word line edge contact phase-change memory: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of... Agent: Stout, Uxa, Buyan & Mullins LLP

20070236988 - Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same: A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed in electrical contact with the first electrode.... Agent: Dla Piper US LLP

20070236991 - Program time adjustment as function of program voltage for improved programming speed in programming method: In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced.... Agent: Davis Wright Tremaine LLP

20070236990 - Programming method to reduce word line to word line breakdown for nand flash: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20070236992 - Self-boosting method with suppression of high lateral electric fields: In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070236993 - Self-boosting system with suppression of high lateral electric fields: In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070236995 - In-circuit emulation system with a programming function: An in-circuit emulation system with a programming function includes a system power supply, a DC/DC converter, a processing device, a programmer socket and a connector. The system power supply produces a first DC voltage. The DC/DC converter converts the first DC voltage into a second DC voltage and a third... Agent: Bacon & Thomas, PLLC

20070236994 - Program and erase methods with substrate transient hot carrier injections in a non-volatile memory: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070236997 - Non-volatile semiconductor memory device: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236996 - Portable data storage apparatus: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and... Agent: F. Chau & Associates, LLC

20070236998 - Nonvolatile semiconductor memory device which stores multivalue data: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070236999 - Reference current generating circuit of nonvolatile semiconductor memory device: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070237000 - Reference current generating circuit of nonvolatile semiconductor memory device: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070237001 - Flash memory device with reduced drain stresses: A non-volatile memory device (100) is provided. Said memory device includes a matrix (105) of memory cells (110(i,j)) arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070237002 - Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory: A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070237003 - Flash memory programming and verification with reduced leakage current: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A... Agent: Ingrassia Fisher & Lorenz, P.C.

20070237004 - Method of erasing an eeprom device: The present application addresses the problem arising during the erasure of EEPROMs where the FN tunnelling erase cycle is not self-limiting. Existing methods address this problem by employing monitoring algorithms. However, these algorithms slow the erase procedure time. The present application provides an alternative method for erasing an EEPROM cell... Agent: Wolf Greenfield & Sacks, P.C.

20070237005 - Split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first... Agent: Dla Piper US LLP

20070237006 - Method for generating soft bits in flash memories: Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references... Agent: Mark M. Friedman

20070237007 - Memory controller: A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070237008 - Program time adjustment as function of program voltage for improved programming speed in memory system: In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced.... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070237009 - Methods and apparatus for improved memory access: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070237010 - Method and system for reading data from a memory: Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070237011 - Nand string with a redundant memory cell: The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled non-volatile memory cells to a source line, a drain select line for selectively coupling one or more strings of series-coupled non-volatile memory cells to one or... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070237012 - Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070237013 - Indirect measurement of negative margin voltages in endurance testing of eeprom cells: An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled... Agent: Schneck & Schneck

20070237014 - Semiconductor memory device and method of controlling the semiconductor memory device: It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system,... Agent: Arent Fox PLLC

20070237015 - Semiconductor memory device and dynamic latch refresh method thereof: A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070237017 - Apparatus and method of detecting refresh cycle of semiconductor memory: An apparatus for detecting a refresh period of a semiconductor memory includes a signal generating unit that generates a plurality of signal pairs, each of which includes one among a plurality of first reference signals that are respectively generated with the same timing as first to (N−1)-th pulses of a... Agent: Venable LLP

20070237016 - Memory: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this... Agent: Mcdermott Will & Emery LLP

20070237018 - Programmable cell: A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode,... Agent: Larson Newman Abel Polansky & White, LLP

20070237019 - Data output circuit of semiconductor memory apparatus and method of controlling the same: The data output circuit for a semiconductor memory apparatus includes a plurality of pads in which a range of use is determined such that the respective pads are used exclusively in each of at least two kinds of unit data output modes or used commonly in all of the at... Agent: Venable LLP

20070237020 - Write control circuitry and method for a memory array configured with multiple memory subarrays: Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070237021 - Memory with clocked sense amplifier: In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during successive memory... Agent: Freescale Semiconductor, Inc. Law Department

20070230229 - Solid state pre-charge module: A solid state pre-charge module includes a relay, a transistor connected to the relay and a solid state device connected to the transistor. The solid state device controls switching of the transistor.... Agent: Lisa B. Vaccarelli Tyco Electronics Corporation

20070230231 - Memory system: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first... Agent: Arent Fox PLLC

20070230230 - Memory module, system and method of making same: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices.... Agent: Trask Britt, P.C./ Micron Technology

20070230232 - Memory transistor gate oxide stress release and improved reliability: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long... Agent: Perkins Coie LLP Patent-sea

20070230233 - Information recording apparatus and information recording method, information reproducing method and fade-in memory: An information recording apparatus comprises a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled... Agent: Dickstein Shapiro LLP

20070230234 - Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word... Agent: Banner & Witcoff, Ltd.

20070230235 - Semiconductor device: It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is a feature of the invention that... Agent: Eric Robinson

20070230236 - Semiconductor storage device: A semiconductor storage device comprises a memory cell array having memory cells arranged in a matrix, each memory cell mainly composed of a flip-flop formed of a pair of cross-coupled inverters, a first wiring configured to each row and each column of the memory cell array and connected to a... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070230240 - Phase change memory device and related programming method: A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set... Agent: Volentine & Whitt PLLC

20070230239 - Phase change memory devices and program methods: A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver... Agent: Volentine & Whitt PLLC

20070230237 - Phase change memory fabricated using self-aligned processing: A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line... Agent: Dicke, Billig & Czaja

20070230238 - Phase change memory fabricated using self-aligned processing: A memory includes transistors in rows and columns providing an array and conductive lines in columns across the array. The memory includes phase change elements contacting the conductive lines and self-aligned to the conductive lines. Each phase change element is coupled to one side of a source-drain path of a... Agent: Dicke, Billig & Czaja

20070230241 - Nanomechanical switching device: A nanomechanical device includes a nanostructure, such as a MWNT, located between two electrodes. The device switches from an OFF state to an ON state by extension of at least one inner shell of the nanostructure relative to at least one outer shell of the nanostructure upon an application of... Agent: Foley And Lardner LLP Suite 500

20070230242 - Methods of forming magnetic random access memory devices including contact plugs between magnetic tunnel junction structures and substrates: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the... Agent: Myers Bigel Sibley & Sajovec

20070230243 - Memory array with readout isolation: Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a... Agent: Goodwin Procter LLP Patent Administrator

20070230244 - Non-volatile programmable memory cell for programmable logic array: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor,... Agent: Sierra Patent Group, Ltd.

20070230246 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device comprises a redundant memory cell to store address data of a defect cell in a memory cell array. A first decoder circuit is given a first drive voltage to provide a control signal to the redundant memory cell. A dummy memory cell has a threshold... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070230245 - Semiconductor storage device: A semiconductor storage device according to the present invention comprises one or more memory planes 8 comprising a plurality of memory blocks 9, and a block selection circuit for decoding an block address signal for selecting the memory block 9 from the memory plane 8 to select the memory block,... Agent: Morrison & Foerster LLP

20070230247 - Trapping storage flash memory cell structure with undoped source and drain regions: Methods of Manufacturing a Nitride Trapping EEPROM Flash memory are described where each memory cell uses Si-FIN to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070230248 - High voltage generation and regulation circuit in a memory device: An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070230249 - Verification method for nonvolatile semiconductor memory device: The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mahler, Ltd.

20070230250 - Methods for improved program-verify operations in non-volatile memories: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070230251 - Nonvolatile semiconductor memory: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is... Agent: Hansen Huang Technology Law Group, LLP

20070230252 - Row selector for a semiconductor memory device: A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path adapted to bias the corresponding word line to a programming voltage when said corresponding word line... Agent: Bryan A. Santarelli

20070230253 - Non-volatile semiconductor memory with page erase: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070230254 - Method for deleting data from nand type nonvolatile memory: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data... Agent: Eric Robinson

20070230256 - Method and apparatus for filtering output data: Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.... Agent: Leffert Jay & Polglaze, P.A.

20070230257 - Method and apparatus for filtering output data: Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.... Agent: Leffert Jay & Polglaze, P.A.

20070230255 - Semiconductor memory device: A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070230258 - Semiconductor memory device for controlling bit line sense amplifying operation using row and column addresses: A semiconductor memory device includes a memory cell block for charging and discharging data into corresponding bit lines when an active command is inputted and any one of a plurality of word lines is enabled; a driving section for supplying a predetermined voltage to a pull-up node and a pull-down... Agent: Ladas & Parry LLP

20070230259 - Buffer circuit and buffer control method: A buffer circuit includes a storage unit having a first storage capacity that stores data based on a write request inputted from an outside and outputs the data in an order in which the data was written, based on a read request inputted from the outside. And a second storage... Agent: Mcginn Intellectual Property Law Group, PLLC

20070230260 - Automatic shutdown or throttling of a bist state machine using thermal feedback: A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is... Agent: Scully Scott Murphy & Presser, PC

20070230261 - Nonvolatile semiconductor memory device and method for testing the same: A nonvolatile semiconductor memory device includes transistor-based memory cells. Each memory cell has a first and a second source/drain region, a channel region separating the first and the second source/drain region, a storage layer and a control gate. The control gates of the memory cells are connected to word lines.... Agent: Edell, Shapiro & Finnan, LLC

20070230262 - Semiconductor memory: A semiconductor memory including a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair through a switching element capable of ON/OFF switching in response to a value of a column selection signal and a precharge circuit for controlling... Agent: Mcdermott Will & Emery LLP

20070230263 - Nonvolatile semiconductor memory: A regular sense amplifier and a defect-information sense amplifier are provided for each regular sector and each defect-information sector, respectively. This can prevent an excess load from being applied to a read path, and minimize the access time. A write amplifier is provided in common to the regular sector, the... Agent: Arent Fox PLLC

20070230264 - Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof: A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the... Agent: Arent Fox PLLC

20070230265 - Semiconductor storage device and refresh control method therefor: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal... Agent: Foley And Lardner LLP Suite 500

20070230266 - Methods of ddr receiver read re-synchronization: One embodiment of the invention provides a method for reading data. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detecting a first time... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda