Static information storage and retrieval inventions 09/07

20070223264 - Memory device with read data from different banks: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing... Agent: Blakely Sokoloff Taylor & Zafman

20070223263 - System and method for re-routing signals between memory system components: A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub controller through any... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070223265 - Fifo memory device with non-volatile storage stage: A FIFO memory device (300) comprises a storage device (321) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device (300) also comprises an input stage (315) which is a volatile FIFO and comprises a plurality of volatile storage elements. The input... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070223266 - One-time-programmable (otp) memory device and method for testing the same: An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial threshold voltage. Each memory cell is programmed to have a first threshold voltage larger than a maximum value of the initial threshold... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070223267 - Arrangement and method for controlling a micromechanical element: The invention concerns an arrangement for controlling a non-volatile memory arrangement for a circuit comprising: a micromechanical element coupled to a substrate; the micromechanical element being responsive to deflection means arranged on the substrate to control the movement of the micromechanical element between one or more stable states. In addition,... Agent: Cantor Colburn, LLP

20070223268 - Memory: A memory capable of operating at a high speed is obtained. This memory includes memory cells arranged on the intersectional positions between bit lines and word lines respectively. A read operation and a first and second rewrite operations performed when reading data of the memory cells are started by changing... Agent: Mcdermott Will & Emery LLP

20070223269 - Spin-injection magnetic random access memory: A spin-injection magnetic random access memory according to an embodiment of the invention includes a magnetoresistive element having a magnetic fixed layer whose magnetization direction is fixed, a magnetic recording layer whose magnetization direction can be changed by injecting spin-polarized electrons, and a tunnel barrier layer provided between the magnetic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070223270 - High write selectivity and low power magnetic random access memory and method for fabricating the same: A low-power magnetic random access memory (MRAM) with high write selectivity is provided. Write word lines and pillar write word lines covered with a magnetic material are disposed in an zigzag relation, solving the magnetic interference problem generated by cells adjacent to the pillar write word line in the magnetic... Agent: Birch Stewart Kolasch & Birch

20070223271 - Semiconductor memory device and semiconductor device group: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070223272 - Semiconductor memory device: This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070223274 - Complex memory chip: A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070223275 - Nonvolatile semiconductor storage device: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank... Agent: Miles & Stockbridge PC

20070223277 - Flash memory: A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070223276 - Non-volatile memory wih controlled program/erase: A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes determining whether each cell in the portion of the NVM passes a first margin level, if not determining which one of... Agent: Freescale Semiconductor, Inc. Law Department

20070223278 - Memory device with variable trim settings: A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to... Agent: Williams, Morgan & Amerson

20070223279 - Semiconductor integrated circuit device: A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further... Agent: Amin, Turocy & Calvin, LLP

20070223280 - Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070223273 - Nonvolatile semiconductor memory device including a cell string with dummy cells: A non-volatile semiconductor memory device includes a memory array having a cell string. The cell string includes a plurality of normal memory cells, a ground selection transistor gated so as to provide a source voltage to the normal memory cells, at least two dummy cells connected between a normal memory... Agent: Volentine & Whitt PLLC

20070223281 - Flash memory device and read operation method thereof: A flash memory device having a function of selectively changing a precharge voltage for a sensing node and a read operation method thereof. The flash memory device includes a memory cell array, a precharge voltage generator, and a plurality of page buffers. The memory cell array includes a plurality of... Agent: Lowe Hauptman Berner, LLP

20070223283 - Word line driving circuit putting word line into one of high level, low level and high impedance: A word line driving circuit has a main word driver for producing first and second main word driver output signals and a subsidiary word driver for driving a word line. The subsidiary word driver has a load transistor supplied with the first main word driver output signal and a driver... Agent: Young & Thompson

20070223282 - Ultra low power non-volatile memory module: An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using conventional supply voltages, thereby minimizing power consumption... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070223284 - Integrated circuit having a memory arrangement: An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as... Agent: Dicke, Billig & Czaja

20070223286 - Memory management device and memory device: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070223285 - Method of erasing flash memory: Some embodiments include converting a plurality of memory cells into a first logic state, and converting the plurality of memory cells into a second logic state only if a leakage occurs after the plurality of memory cells are converted into the first logic state. Other embodiments including additional apparatus, systems,... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070223288 - Circuit and method for adjusting threshold drift over temperature in a cmos receiver: A receiver for use in a device such as a memory device is provided. The receiver circuit is located on the same integrated circuit as a temperature sensor (or other sensor). A data receiver and strobe receiver are coupled to the temperature sensor. A latch receives a data input from... Agent: Slater & Matsil LLP

20070223287 - Pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same: A pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same. The pipe latch circuit includes a selection signal generator and a pipe latch unit. The selection signal generator generates input selection signals in response... Agent: Mayer, Brown, Rowe & Maw LLP

20070223289 - High voltage switch circuit having boosting circuit and flash memory device including the same: A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in... Agent: Townsend And Townsend And Crew, LLP

20070223290 - Low power multi-chip semiconductor memory device and chip enable method thereof: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.... Agent: Volentine & Whitt PLLC

20070223292 - Method for column redundancy using data latches in solid-state memories: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070223291 - Method for remote redundancy for non-volatile memory: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070223293 - Parallel read for front end compression mode: Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of data lines required for transmitting compressed test data. Data lines effectively freed up due to compression of test data read from one bank... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070223295 - Flash memory device having a function for reducing data input error and method of inputting the data in the same: A flash memory device has a precharging section for precharging adequately in advance internal data lines included in an Y-decoder section whenever a process of inputting data into page buffer is performed, error in a second process of inputting data may be reduced by preventing the maintenance of data loaded... Agent: Townsend And Townsend And Crew, LLP

20070223294 - Fast access memory architecture: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a... Agent: Texas Instruments Incorporated

20070223297 - Semiconductor storage device: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array... Agent: Young & Thompson

20070223296 - Bitline isolation control to reduce leakage current in memory device: A semiconductor memory device and method are provided in which leakage current of the memory device is reduced. A sense amplifier is isolated from a memory array that has an anomalous bitline leakage when the memory array is not selected.... Agent: Edell, Shapiro & Finnan, LLC

20070223298 - Differential and hierarchical sensing for memory circuits: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal... Agent: Wayne L. Ellenbogen Ryan, Mason & Lewis, LLP

20070223299 - Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070223300 - Portable electronic apparatus with a power saving function and method: A portable electronic apparatus with a power saving function is provided. A preferred embodiment of the apparatus includes a first data storage (11), a temp data storage (12), a power unit (14), a power control unit (13), and a CPU (15). The CPU is for sending a control instruction to... Agent: North America Intellectual Property Corporation

20070223301 - Dram power bus control: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070223302 - Reducing leakage current in memory device using bitline isolation: A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory... Agent: Edell, Shapiro & Finnan, LLC

20070217244 - High performance and scalable width expansion architecture for fully parallel cams: A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM device of the serial cascade arrangement receives a portion of the... Agent: Texas Instruments Incorporated

20070217245 - 6f² dram cell design with 3f-pitch folded digitline sense amplifier: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active... Agent: Williams, Morgan & Amerson

20070217246 - Semiconductor memory device: In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired... Agent: Stevens, Davis, Miller & Mosher, LLP

20070217247 - Shared sense amplifier for fuse cell: An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality of fuse cells to asynchronously sense one or more voltages output by the plurality of fuse... Agent: Schwabe, Williamson & Wyatt, P.C.

20070217248 - Standby circuitry for fuse cell: An apparatus, a method, and a system for a fuse cell are disclosed herein. In various embodiments, a fuse cell may comprise a standby circuitry to reduce a voltage drop across a fuse device.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070217250 - Memory device: There is provided a memory device including a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a... Agent: Arent Fox PLLC

20070217249 - Semiconductor memory: A semiconductor memory that includes a memory cell array by which power consumption can be reduced and that enables a reduction in circuit area. In the memory cell array, each of capacitor plate lines is arranged so as to connect with ferroelectric memory cells in a same row, and each... Agent: Arent Fox PLLC

20070217251 - Fuse cell having adjustable sensing margin: An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070217252 - Memory cell, memory with a memory cell, and method for writing data in a memory cell: A memory cell having a programmable solid state electrolyte layer, a writing line and a controllable switch that is arranged between the solid state electrolyte layer and the writing line. The controllable switch has a control input that is connected with a selecting line and the switch also has a... Agent: Dicke, Billig & Czaja

20070217253 - Non-volatile phase-change memory device and associated program-suspend-read operation: A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read... Agent: Volentine & Whitt PLLC

20070217254 - Semiconductor memory: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction... Agent: Miles & Stockbridge PC

20070217256 - Magnetic recording element: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic... Agent: Rossi, Kimms & Mcdowell LLP.

20070217255 - Method for measuring hysteresis curve and anisotropic energy of magnetic memory unit: A method for measuring hysteresis curves and anisotropic energy of magnetic memory units is disclosed. It comprises gradually applying different magnetic fields to a single-layer or a multilayer magnetic structure (such as a MRAM memory unit) by extra ordinary Hall effect, and recording the variation of the Hall voltage to... Agent: Rosenberg, Klein & Lee

20070217257 - Synchronization of read and verify operations that may be carried out at the same time over distinct partitions of a flash memory: A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070217258 - Bit symbol recognition method and structure for multiple bit storage in non-volatile memories: Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to... Agent: Macpherson Kwok Chen & Heid LLP

20070217259 - Tracking cells for a memory system: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust... Agent: Vierra Magen/sandisk Corporation

20070217260 - Semiconductor memory device and its operation method: A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The read... Agent: Rader Fishman & Grauer PLLC

20070217261 - Semiconductor memory device: A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines and a main bit line in an activated memory array to be connected all the time. With this configuration, it... Agent: Mcdermott Will & Emery LLP

20070217262 - Segmented column virtual ground scheme in a static random access memory (sram) circuit: A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a... Agent: Gowling Lafleur Henderson LLP

20070217263 - Memory array incorporating memory cells arranged in nand strings: An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary... Agent: Zagorin O'brien Graham LLP (023)

20070217264 - Substrate electron injection techniques for programming non-volatile charge storage memory cells: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070217265 - Low-voltage reading device in particular for mram memory: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070217266 - Static random access memory: SRAM cell includes a four-terminal diode as a read device wherein the first terminal is connected to a read word line, the second terminal is connected to a storage device through a resistor, the third terminal is floating, and the fourth terminal is connected to one of two bit lines;... Agent: Juhan Kim

20070217267 - Method of operating flash memory cell: A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked... Agent: Jianq Chyun Intellectual Property Office

20070217268 - Semiconductor memory chip: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having... Agent: Edell, Shapiro & Finnan, LLC

20070217269 - Semiconductor memory device and driving method of semiconductor memory device: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070217270 - Synchronous semiconductor memory device having on-die termination circuit and on-die termination method: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having... Agent: Volentine & Whitt PLLC

20070217272 - Memory device and relative control method: A single job memory device includes an array of memory cells, row and column decoders and first and second charge pump voltage regulators controlled by respective first and second control circuits that supply the row and column decoders at least during write operations of data in the array of memory... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070217271 - Variable reference voltage circuit for non-volatile memory: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to... Agent: Blakely Sokoloff Taylor & Zafman

20070217273 - Phase-change random access memory: A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of... Agent: F. Chau & Associates, LLC

20070217274 - Nonvolatile memory system and method for controlling nonvolatile memory: A nonvolatile memory system includes a drive voltage generator to generate a drive voltage on the basis of a power supply voltage; a plurality of normal memory cells serving as a nonvolatile memory storing data by accumulating charge of a polarity according to the data to be stored in a... Agent: William S. Frommer, Esq. Formmer Lawrence & Haug LLP

20070217275 - Semiconductor device for driving a current load device and a current load device provided therewith: In a D/I conversion section of the semiconductor device for driving a light emission display device, a precharge circuit is provided at the rear of each 1-output D/I conversion section. A precharge signal PC is input into the precharge circuit. The D/I conversion section has two output blocks internally thereof,... Agent: Scully Scott Murphy & Presser, PC

20070217276 - Fuse latch circuit, semiconductor device and semiconductor memory system: A data storing fuse element unit includes a plurality of fuse elements, stores data in the respective fuse elements in a bit unit in accordance with presence and absence of cutting of fuse elements, and a latch circuit unit latches the stored data by the bit unit. A logic information... Agent: Amin, Turocy & Calvin, LLP

20070217277 - Apparatus and method for reducing the leakage current of memory cells in the energy-saving mode: The energy consumption of a static memory cell, which may be connected to a first bit line and a second bit line of a bit line pair by means of transistors, is reduced in an energy-saving mode of operation by adjusting the potentials on each of the bit lines of... Agent: Dickstein Shapiro LLP

20070217278 - Semiconductor memory, memory system, and operation method of memory system: A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates... Agent: Arent Fox PLLC

20070217279 - Memory having storage means: A memory capable of inhibiting a non-selected cell from disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, for applying voltages of opposite directions to the first... Agent: Arent Fox PLLC

20070217280 - System and method for reducing latency in a memory array decoder circuit: A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of the present invention includes a memory array decoder circuit. The memory array decoder comprises a level-shifting NAND-gate operative to receive a plurality of... Agent: Texas Instruments Incorporated

20070211509 - Integrated semiconductor memory: An integrated semiconductor memory has memory cells, with at least one pair of bit lines which comprises a first bit line and a second bit line, and with at least one sense amplifier which has the first bit line and the second bit line connected to it. The bit lines... Agent: Slater & Matsil LLP

20070211510 - Low resistance plate line bus architecture: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the... Agent: Texas Instruments Incorporated

20070211511 - Read-only memory using linear passive elements: A read-only memory (ROM) is disclosed that uses the presence or absence of linear passive electrical elements, such as resistors or capacitors, to encode zeros and ones, permitting a large-area ROM to be fabricated, possibly on a flexible substrate. The ROM includes a substrate, a plurality of row conductors insulated... Agent: Patent Docket Administrator Lowenstein Sandler P.C.

20070211512 - Ferroelectric memory device: A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070211514 - Memory circuit, method for operating a memory circuit, memory device and method for producing a memory device: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070211513 - Memory device and method for operating such a memory device: Memory device and method for operating a memory device is disclosed. In one embodiment, the memory device has at least one memory cell including an active material, a current supply line, and a first switching device for switching a first current from the current supply line through the active material.... Agent: Dicke, Billig & Czaja

20070211515 - Resistive memory arrangement: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular,... Agent: Dicke, Billig & Czaja

20070211516 - Semiconductor storage device: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save... Agent: Freescale Semiconductor, Inc. Law Department

20070211519 - Memory cells in double-gate cmos technology provided with transistors with two independent gates: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070211520 - Non-volatile memory device and related system and method: An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070211521 - Semiconductor memory device: According to an aspect of the invention, there is provided, a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor formed at a high potential power supply side and a first N-channel MOS transistor formed at a low potential power supply side, a second... Agent: SprinkleIPLaw Group

20070211518 - Static random access memory device having a high-bandwidth and occupying a small area: An SRAM device is disclosed, which comprises a plurality of rows of SRAM cells and a line-buffer SRAM cell. Each row of SRAM cells is controlled by a word line. The line-buffer SRAM cell is coupled to the rows of SRAM cells and controlled by a read enable line. The... Agent: Baker & Mckenzie LLP Patent Department

20070211517 - System and method for operating a memory circuit: A first gate of a multi-gate transistor within a pass gate can be provided with a bias voltage to alter the bias point of the multi-gate transistor. The bias point can be controlled differently during different phases of memory cell operation and the bias point can provide operational improvements during... Agent: Larson Newman Abel Polansky & White, LLP

20070211522 - Magnetic random access memory: A magnetic random access memory according to an embodiment of the present invention comprises first and second write lines which cross each other, and a magnetoresistive element whose center point is not overlapped onto a cross portion of the first and second write lines, wherein a center line of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070211523 - Magnetic random access memory: A magnetic memory includes a diode as an access device instead of MOS transistor and a magnetoresistive storage serves as a storage element, wherein the diode has four terminals, the first terminal is connected to a read word line, the second terminal serves as a storage node, the third terminal... Agent: Juhan Kim

20070211524 - Readout circuit of magnetic memory: In an example, a determination circuit 5 determines whether an input waveform is a first waveform (=0) or a second waveform (=1). When magnetization switching is caused during writing, the second waveform (=1) having a large voltage change is outputted, and thus the determination circuit 5 determines that the output... Agent: Oliff & Berridge, PLC

20070211525 - Magnetic switching element and signal processing device using the same: A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization... Agent: Nixon & Vanderhye, PC

20070211526 - Switch device and method: A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first... Agent: Larson Newman Abel Polansky & White, LLP

20070211527 - A real-time adaptive sram array for high seu immunity: A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity... Agent: Scully Scott Murphy & Presser, PC

20070211528 - Semiconductor memory device: A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are... Agent: Slater & Matsil LLP

20070211529 - Memory device distributed controller system: A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070211530 - Data recording method of semiconductor integrated circuit device: A data recording system of a semiconductor integrated circuit device having a memory area is disclosed. The semiconductor integrated circuit device is equipped with a memory area that includes a binary area and a multi-level area. The semiconductor integrated circuit device records, in the binary area, data transmitted from a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070211532 - Flash memory data correction and scrub techniques: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070211531 - Integrated circuit having a word line driver: An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to... Agent: Dicke, Billig & Czaja

20070211533 - Memory device and method for operating the same: A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and... Agent: Harness, Dickey & Pierce, P.L.C

20070211534 - Method for programming/erasing a non volatile memory cell device: The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070211535 - Dynamic random access memory: DRAM includes a small capacitor as a storage device, a write MOS transistor as a write device, and a diode as a read device; the diode includes four terminals, the first terminal serves as a read word line, the second terminal serves as a storage node, the third terminal is... Agent: Juhan Kim

20070211537 - Nonvolatile memory device and related programming method: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage... Agent: Volentine & Whitt PLLC

20070211536 - Programming a flash memory device: An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the... Agent: Leffert Jay & Polglaze, P.A.

20070211538 - Methods and apparatus for a non-volatile memory device with reduced program disturb: A non-volatile memory device includes a polarity of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target memory cell in the array, as well as the... Agent: Baker & Mckenzie LLP Patent Department

20070211539 - Method for resetting threshold voltage of non-volatile memory: A method for resetting threshold voltage of a non-volatile memory is provided. The method is suitable for a non-volatile memory having a plurality of memory cells. Each memory cell includes a gate and a charge trapping layer. The method includes erasing the non-volatile memory by Fowler-Nordheim (FN) tunneling effect until... Agent: Jianq Chyun Intellectual Property Office

20070211541 - Non-volatile memory device and method for programming/erasing the same: The present invention provides a SONOS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070211540 - Structures and methods for enhancing erase uniformity in a nitride read-only memory array: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070211542 - Multi-probe for writing and reading data and method of operating the same: A multi-probe for writing data to and/or reading data from a recording medium. The multi-probe includes a plurality of probes. All of the probes are working probes for writing the data to and/or reading the data from the recording medium.... Agent: Sughrue Mion, PLLC

20070211543 - Semiconductor device with non-volatile memory and random access memory: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time;... Agent: Stanley P. Fisher Reed Smith LLP

20070211544 - Semiconductor device: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation.... Agent: Miles & Stockbridge PC

20070211545 - Semiconductor memory device: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070211546 - Apparatus and method for controlling test mode of semiconductor memory: Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups... Agent: Venable LLP

20070211547 - Semiconductor device: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a... Agent: Miles & Stockbridge PC

20070211548 - Temperature determination and communication for multiple devices of a memory module: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed... Agent: Intel/blakely

20070211549 - Semiconductor memory, memory system, and operation method of semiconductor memory: A semiconductor memory executes an access operation on one of a plurality of memory blocks in response to an externally supplied access request. At this time, in response to the access request, a memory control unit executes the access operation on one of the memory blocks and a refresh operation... Agent: Arent Fox PLLC

20070211550 - Non-skipping auto-refresh in a dram: In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a first memory address bit to an unused memory address location. Using the new addressing scheme, an auto-refresh operation... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070211551 - Method for dynamic performance optimization conforming to a dynamic maximum current level: Various non-limiting exemplary embodiments are disclosed including a method for power management in a system comprising determining a maximum system current level, and allocating current to one or more operations each having a minimum operation current level and a maximum operation current level such that the total allocated current for... Agent: Empk & Shiloh, LLP

20070211553 - Semiconductor device reducing power consumption in standby mode: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is... Agent: Buchanan, Ingersoll & Rooney PC

20070211552 - Integrated semiconductor memory device: An integrated semiconductor memory device comprises: a receiver circuit for receiving a data signal, a receiver circuit for receiving a command signal, and a receiver circuit for receiving an address signal. A programmable storage unit comprises programmable elements. A current of the receiver circuits is controlled in dependence on a... Agent: Edell, Shapiro & Finnan, LLC

20070211554 - Memory with serial input-output terminals for address and data and method therefor: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of... Agent: Freescale Semiconductor, Inc. Law Department

20070211555 - Address buffer and method for buffering address in semiconductor memory apparatus: An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch input address and a clock. A synchronous... Agent: Venable LLP

20070211556 - Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof: An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an... Agent: Harness, Dickey & Pierce, P.L.C

20070211558 - Circuit and method for detecting synchronous mode in a semiconductor memory apparatus: A circuit for detecting synchronous mode in a semiconductor memory apparatus includes a control unit that controls the driving of a clock according to whether or not a valid address signal is enabled. A driving unit drives the clock according to the control of the control unit. A latch unit... Agent: Venable LLP

20070211559 - Computer system with nand flash memory for booting and storage: A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and... Agent: Marger Johnson & Mccollom, P.C.

20070211557 - Flash memory controller: An apparatus for controlling a flash memory device which includes a signal generator for generating a clock signal at an operation, a first buffer for outputting the clock signal to the flash memory device as a clock enable signal a second buffer for receiving data from the flash memory device... Agent: F. Chau & Associates, LLC

20070206397 - Low power match-line sensing circuit: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low... Agent: Borden Ladner Gervais LLP

20070206396 - Physical priority encoder: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to... Agent: Mario J. Donato, Jr. Stmicroelectronics, Inc.

20070206398 - Semiconductor memory: A semiconductor memory according to an example of the present invention is provided with a memory cell array, a plurality of word lines provided on the memory cell array, and a plurality of transfer transistors each one of which is connected to each of the plurality of word lines. Direction... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070206399 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070206400 - Write protection for computer long-term memory devices with write-once read-many blocking: A protection device provides write-once, read many capabilities for computer long-term storage devices, such as hard drives. The blocking device is placed between a host computer and a storage device. The blocking device intercepts communications between the host and the storage device and examines any commands from the host to... Agent: Steve Bress

20070206401 - Electrical fuse device with dummy cells for esd protection: An electrical fuse device includes at least one electrical fuse cell having a first switch device serially coupled with an electrical fuse representing a logic value; and at least one dummy cell having a second switch device coupled to the first switch device via a common word line, the second... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070206403 - Semiconductor memory device and semiconductor integrated circuit system: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp by a bit-line precharge circuit and... Agent: Mcdermott Will & Emery LLP

20070206402 - Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at... Agent: Slater & Matsil LLP

20070206404 - Semiconductor memory device: m

20070206406 - Spin injection write type magnetic memory device: A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070206405 - Multi-bit magnetic memory device using spin-polarized current and methods of manufacturing and operating the same: A multi-bit magnetic memory device using a spin-polarized current and methods of manufacturing and operating the same. The magnetic memory device includes a switching device and a magnetic storage node connected to the switching device, wherein the magnetic storage node includes a first magnetic layer, a second magnetic layer and... Agent: Sughrue Mion, PLLC

20070206407 - Spin based memory coupled to cmos amplifier: A nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a... Agent: J. Nicholas Gross

20070206410 - Calibration system for writing and reading multiple states into phase change memory: A phase change memory system includes M phase change memory cells, where M is an integer greater than or equal to one. A write module selectively writes at least one of the M phase change memory cells based on a write parameter. A read module selectively reads back a resistance... Agent: Harness, Dickey & Pierce P.L.C

20070206409 - Phase-change random access memory device: A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of... Agent: Volentine & Whitt PLLC

20070206408 - Phase change memory fabricated using self-aligned processing: A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each... Agent: Dicke, Billig & Czaja

20070206411 - Magnetic random access memory devices including contact plugs between magnetic tunnel junction structures and substrates and related methods: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the... Agent: Myers Bigel Sibley & Sajovec

20070206413 - Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect: A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS transistor having source/drain... Agent: Richard P. Berg, Esq. C/o Ladas & Parry

20070206412 - Semiconductor device: A nonvolatile memory device improves the accuracy of screening testing while applying a voltage at or lower than the limit of the withstand voltage of an element for high voltage in the screening testing. The nonvolatile memory device includes a high voltage production circuit that produces a high voltage, a... Agent: Rohm Co., Ltd. C/o Keating & Bennett, LLP

20070206415 - Non-volatile memory cell and non-volatile memory device using said cell: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two... Agent: Empk & Shiloh, LLP

20070206416 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in aeries together is disclosed. A select gate translator is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070206417 - Memory transistor gate oxide stress release and improved reliability: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long... Agent: Perkins Coie LLP Patent-sea

20070206418 - Nonvolatile memory: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address... Agent: Miles & Stockbridge PC

20070206414 - Method of fabricating a multi-bit memory cell: The method of fabricating a multi-bit flash memory cell begins with forming an ion implantation mask exposing a portion of a channel region in a semiconductor substrate. Ions are implanted into the exposed region thereby partially coding the threshold voltage to create one ion implanted channel region with a first... Agent: Sherr & Nourse, PLLC

20070206420 - Mode selection in a flash memory device: A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070206419 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in second... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070206421 - Read operation for non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20070206422 - Nand memory device column charging: Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070206423 - Solid-state image-capturing device, driving method thereof, camera, electric charge transfer device, driving method and driving device for driving load, and electronic equipment: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate... Agent: Rader Fishman & Grauer PLLC

20070206424 - Method for erasing non-volatile memory: A method for erasing a non-volatile memory is provided. The non-volatile memory includes a first conductive type substrate, a second conductive type well disposed in the first conductive type substrate, a first conductive type well disposed on the second conductive type well, and a memory cell disposed on the first... Agent: Jianq Chyun Intellectual Property Office

20070206425 - Semiconductor memory device: A semiconductor memory device capable of suppressing variation in a threshold voltage of a cell. A write controller monitors a write level of a cell and compares the write level with a predetermined set level (a predetermined current value) by measuring, for example, a bit line current during a write... Agent: Arent Fox PLLC

20070206426 - System for performing read operation on non-volatile storage with compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20070206427 - Internal power supply generating circuit without a dead band: An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By... Agent: Sughrue Mion, PLLC

20070206428 - High-speed phase-adjusted quadrature data rate (qdr) transceiver and method thereof: A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group... Agent: F. Chau & Associates, LLC

20070206429 - Memory component with multiple delayed timing signals: A memory component having multiple delayed timing signals. Control information specifying a write operation and write data corresponding to the write operation are each received via a separate external signal path. A timing signal is received indicating that the write data is valid write data. Signals corresponding to multiple delayed... Agent: Shemwell Gregory & Courtney LLP

20070206430 - Semiconductor memory device and test method therefor: Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first... Agent: Sughrue Mion, PLLC

20070206431 - Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed... Agent: Arent Fox PLLC

20070206432 - Microcomputer and microprocessor having flash memory operable from single external power supply: A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070206433 - Semiconductor memory device: The present invention provides a ferroelectric memory capable of arbitrarily dividing a memory block into 1T/1C type and 2T/2C type areas. A memory cell array has 1T/1C type memory cells disposed in matrix form. An address storage unit stores therein threshold memory addresses for dividing the memory cell array into... Agent: Volentine & Whitt PLLC

20070206434 - Memory with multi-page read: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.