Static information storage and retrieval inventions 08/07

20070201255 - Chalcogenide glass constant current device, and its method of fabrication and operation: The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a constant current device that maintains a constant current over an applied voltage range of at least approximately 700 mV. The invention also provides a method of changing... Agent: Dickstein Shapiro LLP

20070201256 - Semiconductor memory module and electronic apparatus including a semiconductor memory module and method for operating thereof: A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20). The first register (10) and the second register (20) each comprise a first... Agent: Slater & Matsil LLP

20070201257 - Layout techniques for read-only memory and the like: An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of... Agent: Ryan, Mason & Lewis, LLP

20070201258 - Semiconductor memory device capable of controlling drive ability of output driver: An example embodiment provides a semiconductor memory device. The semiconductor memory device may include an output driver, a delay circuit and an output driver controlling circuit. The output driver may output an external output signal in response to an internal output signal. The delay circuit may receive the internal output... Agent: Harness, Dickey & Pierce, P.L.C

20070201259 - Method and apparatus for programming and reading codes on an array of fuses: An device for programming and reading codes onto an array of binary data storage element includes: a shift register for receiving, sequentially, a binary data series to be written onto the data storage elements; and control logic circuit for determining whether or not data is to be applied to each... Agent: Edell, Shapiro & Finnan, LLC

20070201260 - Memory device with hierarchy bit line: The present invention relates to a memory device with a hierarchy bit line. In a FeRAM with folded bit lines and opened bit lines, it has a hierarchy bit line where bit line signals in two or more columns commonly share one global bit line signal. In the hierarchy bit... Agent: Ladas & Parry LLP

20070201263 - Semiconductor memory device: Included are first and second inverters 1L, 1R, a first selection transistor N1 controlling a connection of an output terminal of the first inverter 1L to a bit line 11, and a second selection transistor N2 controlling a connection of an output terminal of the second inverter 1R to a... Agent: Arent Fox PLLC

20070201261 - Independent-gate controlled asymmetrical memory cell and memory using the cell: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number... Agent: Ryan, Mason & Lewis, LLP

20070201262 - Logic sram cell with improved stability: A static random access memory (SRAM) cell with improved stability that can handle half select operations. The disclosed cell includes: a pair of cross-coupled inverters coupled to a write bit line via a pass transistor, the pass transistor including a gate coupled to a pseudo write word line; a pair... Agent: Hoffman, Warnick & D'alessandro LLC

20070201265 - High capacity low cost multi-state magnetic memory: One embodiment of the present invention includes a multi-state current-switching magnetic memory element having a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.... Agent: Law Offices Of Imam

20070201264 - Magnetic memory devices: A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular to the first metal lines. The plurality of second metal... Agent: Harness, Dickey & Pierce, P.L.C

20070201266 - High-bandwidth magnetoresistive random access memory devices: A magnetoresistive random access memory (MRAM) device includes a memory cell corresponding to one read bit line, one read word line, one write word line, and two or more write bit lines. The memory cell includes a first memory unit and a second memory unit each corresponding to a respective... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070201267 - Sense circuit for resistive memory: A memory includes a phase-change memory cell and a circuit. The phase-change memory cell can be set to at least three different states including a substantially crystalline state, a substantially amorphous state, and at least one partially crystalline and partially amorphous state. The circuit applies a first voltage across the... Agent: Dicke, Billig & Czaja

20070201268 - Spin based magnetic sensor: A spin based device can be used as a magnetic field sensor. The device uses ferromagnetic materials for implementing a variable spin resistance to a spin injected current having a particular spin value. An external magnetic field can change the magnetization state of the device by orienting the magnetization of... Agent: Peter Courture Esq.

20070201271 - Memory device with hierarchy bit line: The present invention relates to a memory device with a hierarchy bit line. In a DRAM with folded bit lines and opened bit lines, it has a hierarchy bit line where bit line signals in two or more columns commonly share one global bit line signal. In the hierarchy bit... Agent: Ladas & Parry LLP

20070201270 - Read only memory device with bitline leakage reduction: A memory chip configuration aims that reduces the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of—a n×m FET matrix, vertically running bitlines—each shared by a column in the array, horizontally running wordlines—each shared by a row in the array, horizontally running sourcelines—each shared... Agent: Docket Clerk

20070201272 - Semiconductor device: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070201273 - Back-gate controlled asymmetrical memory cell and memory using the cell: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect... Agent: Ryan, Mason & Lewis, LLP

20070201274 - Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory: A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error... Agent: Stuart T Auvinen

20070201275 - Semiconductor device and method for manufacturing the same: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070201276 - Dual-gate, non-volatile memory cells, arrays thereof, methods of manufacturing the same and methods of operating the same: Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070201277 - Nor flash memory device with a serial sensing operation and method of sensing data bits in a nor flash memory device: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially... Agent: Mills & Onello LLP

20070201278 - Method for programming memory cells including transconductance degradation detection: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises... Agent: Seed Intellectual Property Law Group PLLC

20070201279 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070201269 - Method and apparatus for protection from over-erasing nonvolatile memory cells: Methods and apparatuses for protecting charge trapping memory cells from over-erasing in response to an erase command are disclosed.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070201280 - Memory device: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by... Agent: Deniro/rambus

20070201281 - Decoding techniques for read-only memory: A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic... Agent: Ryan, Mason & Lewis, LLP

20070201283 - Boost voltage generating circuit and method thereof: A boost voltage generating circuit and method thereof. The example boost voltage generating circuit may include a voltage comparator comparing an input voltage and a reference voltage and generating a control signal based on a result of the voltage comparison, the input voltage based on a feedback boost voltage, a... Agent: Harness, Dickey & Pierce, P.L.C

20070201282 - Memory module: A memory module having an array of memory devices, mounted thereon, that operate synchronously with a clock signal, wherein provisions are made to be able to fine-tune the clock phase in accordance with its use conditions. The memory module, having an array of memory devices mounted thereon that operate synchronously... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP Kratz, Quintos & Hanson, LLP

20070201284 - Internal voltage generation control circuit and internal voltage generation circuit using the same: Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same. The internal voltage generation control circuit comprises a row active controller for enabling a first internal voltage generation control signal when a row active signal is enabled upon input of an active... Agent: Marshall, Gerstein & Borun LLP

20070201285 - Voltage pumping device: A voltage pumping device is disclosed. The device comprises a reference voltage generator for generating a reference voltage having different levels depending on whether a semiconductor device is in a self-refresh mode or not, a voltage level detector for outputting a voltage pumping enabling signal in response to the reference... Agent: Marshall, Gerstein & Borun LLP

20070201286 - Input circuit of a semiconductor memory device and method of controlling the same: An input circuit of a semiconductor memory device includes a data strobe circuit configured to buffer a data strobe signal to generate a first internal strobe signal and to generate a second internal strobe signal in response to the first internal strobe signal and an operating mode of the semiconductor... Agent: Marger Johnson & Mccollom, P.C.

20070201287 - Programmable delay introducing circuit in self timed memory: A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070201288 - Semiconductor memory device which compensates for delay time variations of multi-bit data: A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data... Agent: Volentine & Whitt PLLC

20070201289 - Embedded memory and methods thereof: An embedded memory and methods thereof are provided. The example embedded memory may include a first memory block configured to output data, selected by a first column select signal, on a first scan output line if the first memory block is determined to be non-defective and a second memory block... Agent: Harness, Dickey & Pierce, P.L.C

20070201290 - Sense amplifier circuit in semiconductor memory device and driving method thereof: Provided is a sense amplifier circuit in a semiconductor memory device in which an under-drive is applied to a switching element of a pull-down side of a sense amplifier in order to compensate for poor driving capability in the case of performing a low voltage operation. The sense amplifier circuit... Agent: Ladas & Parry LLP

20070201291 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving... Agent: Venable LLP

20070201292 - Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed... Agent: Arent Fox PLLC

20070201293 - Testing method for permanent electrical removal of an integrated circuit output: An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output driver of the respective input/output terminal. A DRAM module is disclosed having a... Agent: Trask Britt, P.C./ Micron Technology

20070201294 - Control circuit for power supply device, power supply device, and control method thereof: A control circuit for a power supply device, a power supply device, and a control method thereof are provided where the output voltages to be supplied to various devices are determined and set up to optimum levels rapidly and efficiently. A control circuit 10A in a power supply device supplies... Agent: Arent Fox PLLC

20070201295 - Low power memory architecture: A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can... Agent: Borden Ladner Gervais LLP

20070201296 - Memory arrangement: A memory arrangement includes an interface configured to transmit data in the form of data packets according to a predefined protocol. The memory arrangement includes at least two memory banks. Each memory bank includes at least one memory cell. The memory arrangement includes at least two memory bank access devices... Agent: Dicke, Billig & Czaja

20070201297 - Multi-port memory device and method of controlling the same: A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator... Agent: Harness, Dickey & Pierce, P.L.C

20070201298 - Bit line precharge in embedded memory: An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit... Agent: Larson Newman Abel Polansky & White, LLP

20070201299 - Semiconductor memory device with mos transistors each having floating gate and control gate: A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070201300 - Signal sampling apparatus and method for dram memory: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.... Agent: Lowe Hauptman Berner, LLP

20070195569 - Thin film transistor array panel for liquid crystal display and method for manufacturing the same: In a method of fabricating a liquid crystal display an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a... Agent: F. Chau & Associates, LLC

20070195570 - Serial content addressable memory: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also... Agent: Laurence H. Cooke

20070195571 - Bit line coupling: Methods and apparatus are provided. In one embodiment, a memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The... Agent: Leffert Jay & Polglaze, P.A.

20070195572 - 276-pin buffered memory module with enhanced fault tolerance: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a pluality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070195573 - Dynamic ram-and semiconductor device: A semiconductor memory includes a plurality of first regions arranged along a first direction, each of which corresponds to a memory array including a plurality of word lines, bit lines and memory cells. A plurality of second regions are provided each of which is arranged alternately with respect to each... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070195574 - Semiconductor memory device and control method thereof: This invention provides a semiconductor memory device in which standby current is suppressed to a small level. A ROM device includes memory cells for reading data corresponding to impedance between a terminal connected to bit lines and a source terminal and source power lines connected to the source terminal. In... Agent: Arent Fox PLLC

20070195575 - Semiconductor integrated circuit: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070195576 - Organic compound having functional groups different in elimination reactivity at both terminals, organic thin film, organic device and method of producing the same: (A1 to A6 each represent a hydrogen atom, a halogen atom, an alkoxy group or an alkyl group and satisfy the relationship in elimination reactivity of: A1 to A3>A4 to A6; and B represents a bivalent organic group), an organic thin film using the compound, and an organic device having... Agent: Nixon & Vanderhye, PC

20070195577 - Rfid device having nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory in an RFID device includes a plurality of word lines, and a plurality of banks each including a cell array. The cell array of one of the banks includes a region to be initialized, wherein the region includes a plurality of memory unit cells each including... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070195578 - Semiconductor memory device: A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and... Agent: Mcdermott Will & Emery LLP

20070195579 - Semiconductor memory: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling... Agent: Arent Fox PLLC

20070195581 - Method of controlling the resistance in a variable resistive element and non-volatile semiconductor memory device: The method of controlling a resistance of a variable resistive element comprises a forming step for shifting the variable resistive element from an initial state after the production to a variable resistance state capable of a stable mono-polar switching action where a variable resistive characteristic of the variable resistive element... Agent: Nixon & Vanderhye, PC

20070195580 - Memory circuit having a resistive memory cell and method for operating such a memory circuit: The invention relates to a memory circuit comprising a resistive memory cell having a selection transistor and a resistive memory element connected in series, wherein the resistive memory element is coupled to a plate potential; and a control circuit to control the selection transistor by means of an activation signal... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070195582 - Semiconductor device: A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If... Agent: Stanley P. Fisher Reed Smith LLP

20070195584 - Semiconductor memory device: A semiconductor memory device is disclosed, which includes a first SRAM cell which includes cross-connected first and second inverters having first and second nodes, a first transistor connected between a first bit line and the first node and having a gate connected to a first write word line, a second... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070195583 - Memory with five-transistor bit cells and associated control circuit: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070195586 - Magnetic memory device and methods thereof: A magnetic memory device and methods thereof are provided. The example magnetic memory device may include a transistor disposed within a given unit cell region and a magnetic tunneling junction (MTJ) element connected to the transistor, the MTJ element including an MTJ cell and first and second pad layers forming... Agent: Harness, Dickey & Pierce, P.L.C

20070195587 - Magnetic memory device using magnetic domain motion: A magnetic memory device is provided. The magnetic memory device may include a memory track in which a plurality of magnetic domains is formed so that data bits, each of which may be a magnetic domain, are stored in an array. The memory track may be formed of an amorphous... Agent: Harness, Dickey & Pierce, P.L.C

20070195588 - Magnetic memory devices using magnetic domain motion: A magnetic memory device includes a recording layer, a reference layer, a first input portion and a second input portion. The recording layer has perpendicular magnetization direction and a plurality of magnetic domains, and the reference layer corresponds to a portion of the recording layer and has a pinned magnetization... Agent: Harness, Dickey & Pierce, P.L.C

20070195589 - Thin film magnetic memory device for conducting data write operation by application of a magnetic field: A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground voltage, respectively.... Agent: Mcdermott Will & Emery LLP

20070195585 - Toggle-type magnetoresistive random access memory: A MRAM includes: first wirings, second wirings, memory cells, a second sense amplifier and a first sense amplifier. The first wirings and second wirings are extended in a first and a second direction. The memory cells are placed correspondingly to positions where the first wirings are crossed with the second... Agent: Scully Scott Murphy & Presser, PC

20070195590 - Nonvolatile semiconductor memory device and data writing method: The invention provides a data writing method for writing data sequentially in a cross-point memory cell array having a variable resistive element whose electric resistance is changed by application of an electric stress. When data is sequentially written in memory cells in the same row or column, the writing order... Agent: Nixon & Vanderhye, PC

20070195591 - Layout method of a semiconductor memory device: The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite... Agent: Volentine & Whitt PLLC

20070195594 - Magnetic memory: A magnetoresistance effect element is also located between second wiring and common wiring. The magnetoresistance effect element is electrically connected to the second wiring without a spin filter. When a reading current is supplied between the second wiring for supplying a reading current and the common wiring, since this is... Agent: Oliff & Berridge, PLC

20070195593 - Structure of magnetic memory cell and magnetic memory device: A structure of magnetic memory cell, suitable for a magnetic memory device with toggle mode access operation is provided, which includes a magnetic pinned stacked layer as a portion of a substrate structure; a tunnel barrier layer disposed on the magnetic pinned stacked layer; a magnetic free stacked layer disposed... Agent: Jianq Chyun Intellectual Property Office

20070195592 - Magnetic tunnel junction device and method of manufacturing the same: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO(001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm... Agent: Reed Smith LLP

20070195595 - Nonvolatile memory device: A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to... Agent: Mills & Onello LLP

20070195596 - Semiconductor integrated circuit device, production and operation method thereof: A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070195597 - Non-volatile memory devices that utilize mirror-image programming techniques to inhibit program coupling noise and methods of programming same: Non-volatile memory devices have improved data storage reliability resulting from mirror-image programming techniques that operate to reduce coupling noise between adjacent memory cells within a memory array. The adjacent memory cells include a first pair of memory cells and a second pair of memory cells. A program control circuit is... Agent: Myers Bigel Sibley & Sajovec

20070195598 - Accessing semiconductor memory device according to an address and additional access information: A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells... Agent: Law Office Of Monica H Choi

20070195599 - Data storage: A data storage includes a part of functioning for, when data reading operation is carried out on a storage part storing data for a case where the data storage is handled in a predetermined manner, causing predetermined data different from target data to be read out instead of the target... Agent: Staas & Halsey LLP

20070195600 - Multiple level cell memory device with single bit per cell, re-mappable memory block: A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode.... Agent: Leffert Jay & Polglaze, P.A.

20070195601 - Nonvolatile semiconductor memory device that achieves speedup in read operation: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS... Agent: Buchanan, Ingersoll & Rooney PC

20070195602 - Reducing floating gate to floating gate coupling effect: For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the... Agent: Vierra Magen/sandisk Corporation

20070195604 - Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same: A circuit for controlling a driver of a semiconductor memory apparatus includes at least one driving unit in which impedance is set according to a code value, an impedance adjusting unit that outputs a first code and a second code for setting the impedance of the at least one driving... Agent: Venable LLP

20070195603 - Minimizing effects of program disturb in a memory device: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20070195606 - Nonvolatile semiconductor memory device and method of rewriting data thereof: The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between two memory cells comprising a memory cell pair, and a writing controller for writing data to the memory cell array.... Agent: Mcdermott Will & Emery LLP

20070195605 - Row selector with reduced area occupation for semiconductor memory devices: A memory device including a plurality of memory cells, said memory cells being grouped in at least two memory sectors. In each memory sector the memory cells are arranged according to a plurality of alignments of memory cells. A respective memory cell access signal line is associated with each alignment.... Agent: Seed Intellectual Property Law Group PLLC

20070195607 - Nrom non-volatile memory and mode of operation: Operating NVM memory cell such as an NROM cell by using a combination of Fowler-Nordheim tunneling (FNT), hot hole injection (HHI), and channel hot electron (CHE) injection. In the FNT erase step, only a few cells may be verified, and in the CHE second programming step, the threshold voltage of... Agent: Empk & Shiloh, LLP

20070195608 - Germanium-silicon-carbide floating gates in memories: The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070195610 - Flash memory devices, methods of erasing flash memory devices and memory systems including the same: In a method of erasing a non-volatile memory device an electric field is applied between a plurality of word lines and a substrate to erase memory cells in a memory block simultaneously. After a first time period elapses, the electric field applied between a first portion of the plurality of... Agent: Harness, Dickey & Pierce, P.L.C

20070195609 - Non-volatile memory device and method of operation therefor: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is... Agent: Harness, Dickey & Pierce, P.L.C

20070195612 - Methods and systems for creating data samples for data analysis: Systems and methods for creating data samples for data analysis. The method includes imaging at least a portion of a first object having a target portion to generate a first image, analyzing the first image by running a first series of algorithms using the first image to generate a first... Agent: Black Lowe & Graham, PLLC

20070195611 - Programmable structure, a memory, a display and a method for reading data from a memory cell: The invention refers to an improved programmable structure, an improved memory, an improved display and an improved method for reading data from a memory cell. More particularly, embodiments of the invention provide a programmable structure and a memory, whereby a programmed state of the programmable structure and a programmed state... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070195613 - Memory module with memory stack and interface with enhanced capabilities: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory... Agent: Stattler-suh PC

20070195614 - Level shifter for low voltage operation: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20070195615 - Method and circuit for real-time calibrating data control signal and data signal: A real-time calibrating circuit comprises a first comparator, a second comparator, a phase detector, at least one control circuit, and at least one output driving circuit for driving a data control signal or a data signal, wherein the first and the second comparators compare the voltage values of two complementary... Agent: Lowe Hauptman Berner, LLP

20070195616 - Setting one or more delays of one or more cells in a memory block to improve one or more characteristics of the memory block: In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one... Agent: Baker Botts L.L.P.

20070195617 - Methods and apparatus for read/write control and bit selection with false read suppression in an sram: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate... Agent: Ryan, Mason & Lewis, LLP

20070195619 - Integrated circuit memory devices having multi-bit normal memory cells and single-bit redundant memory cells therein: A memory device includes a first memory array having a plurality of rows and columns of multi-bit DRAM cells therein. A redundant memory array is also provided having a plurality of single-bit memory cells therein. These single-bit memory cells are configured to support replacement of a first plurality of multi-bit... Agent: Myers Bigel Sibley & Sajovec

20070195618 - Memory device fail summary data reduction for improved redundancy analysis: A method and apparatus for filtering failures due to must-repair rows or columns from a memory test fail summary image includes current available redundant row failure counts respectively associated with rows of a memory device and current available redundant column failure counts associated with columns of the device. Respective failure... Agent: Verigy

20070195621 - Method and apparatus for increasing yield in a memory circuit: Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the first mode, the control circuitry is operative to apply a first signal to a selected... Agent: Ryan, Mason & Lewis, LLP

20070195620 - Semiconductor memory: In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each... Agent: Arent Fox PLLC

20070195622 - Semiconductor memory device with redundancy circuit: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address... Agent: Nixon Peabody, LLP

20070195623 - Apparatus and method for dynamically repairing a semiconductor memory: An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed... Agent: Trask Britt, P.C./ Micron Technology

20070195624 - Sense amplifier control circuit and semiconductor device using the same: A sense amplifier control circuit which can be used in a semiconductor device includes an enable signal generator for decoding a plurality of internal commands, to output a first enable signal and a second enable signal which are enabled in an active mode of a semiconductor device, a first driving... Agent: Cooper & Dunham, LLP

20070195625 - Local sense amplifier in memory device: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first... Agent: Law Office Of Monica H Choi

20070195626 - Semiconductor memory device including memory cell without capacitor: A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second word lines; and a reference memory cell... Agent: Mills & Onello LLP

20070195627 - Dynamic semiconductor memory with improved refresh mechanism: Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at... Agent: Townsend And Townsend And Crew, LLP

20070195628 - Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed... Agent: Arent Fox PLLC

20070195629 - System and method for increasing reliability of electrical fuse programming: A system and method for achieving enhanced e-fuse programming reliability. By providing an e-fuse device with redundantly coded fuse structures each with a differing fuse size dimension, reliable encoding of a fuse with a programmed bit is enhanced. That is, for each e-fuse device, each of the multiple fuse structures... Agent: Scully Scott Murphy & Presser, PC

20070195630 - Internal power voltage generating circuit in semiconductor memory device: A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a... Agent: Volentine & Whitt PLLC

20070195631 - Control system for a dynamic random access memory and method of operation thereof: A dynamic random access memory device includes an array of dynamic random access memory cells subdivided into a group of blocks. Each of the blocks of memory cells can be independently operated in either a single cell mode or a twin cell mode.... Agent: Slater & Matsil LLP

20070195632 - Semiconductor memory device having a global data bus: There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate... Agent: Blakely Sokoloff Taylor & Zafman

20070195634 - Flat panel display device and fabrication apparatus thereof and fabrication method thereof: Disclosed is a method of making a flat panel display device. The device has a first substrate, a second substrate opposing the first substrate and an array of pixels formed therebetween. A frit is interposed and interconnects between the first substrate and second substrate. The frit is melted by irradiating... Agent: Knobbe Martens Olson & Bear LLP

20070195633 - Multi-port semiconductor memory device and signal input/output method therefor: A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The... Agent: Marger Johnson & Mccollom, P.C.

20070195636 - Nonvolatile semiconductor memory device having multi-level memory cells and page buffer used therefor: A non-volatile semiconductor memory device includes a memory array having nonvolatile memory cells. The memory device also includes a page buffer coupled to the memory array through first and second common bit lines and configured to map a set of first to third bit data to threshold voltage levels of... Agent: Volentine & Whitt PLLC

20070195635 - Non-volatile memory device with page buffer having dual registers and methods using the same: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the... Agent: John S. Egbert Egbert Law Offices

20070195638 - Delay-locked loop, integrated circuit having the same, and method of driving the same: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal,... Agent: Volentine & Whitt PLLC

20070195637 - Loop filtering for fast pll locking: Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes locking a DLL... Agent: Brooks, Cameron & Huebsh , PLLC

20070189050 - Semiconductor chip and semiconductor chip package comprising semiconductor chip: Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In... Agent: Volentine & Whitt PLLC

20070189049 - Semiconductor memory module: A semiconductor memory module having a plurality of memory chips and at least one bus connecting the plurality of memory chips is provided. The bus has two branches, a first connected to a greater quantity of memory chips than a second branch.... Agent: Baker Botts L.L.P. Patent Department

20070189052 - Memory system: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical... Agent: Arent Fox PLLC

20070189051 - Semiconductor integrated circuit and ic card system: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power,... Agent: Miles & Stockbridge PC

20070189053 - Electrical fuse device based on a phase-change memory element and corresponding programming method: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus... Agent: Seed Intellectual Property Law Group PLLC

20070189054 - Setting method of chip initial state: Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070189055 - Semiconductor integrated circuit and ic card system: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power,... Agent: Miles & Stockbridge PC

20070189056 - Stacked ferroelectric memory devices, methods of manufacturing the same, ferroelectric memory circuits and methods of driving the same: A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single... Agent: Marger Johnson & Mccollom, P.C.

20070189057 - Multiple port memory having a plurality of parallel connected trench capacitors in a cell: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as... Agent: International Business Machines Corporation Dept. 18g

20070189058 - Molecular system and method for reversibly switching the same between four states: A molecular system that is reversibly switchable between four states includes two or more ends. At least three rotors and at least two stators are located between the ends. Each of the rotors is capable of rotating when under the influence of an electric field having a predetermined strength. The... Agent: Hewlett Packard Company

20070189059 - Memory device and method for reading data: The present invention relates to a memory with memory cells, wherein a memory cell comprises a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches comprise... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070189061 - Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory: Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair... Agent: W. Riyon Harding International Business Machines Corporation

20070189063 - Semiconductor integrated circuit device and method of manufacturing the same: A semiconductor integrated circuit device comprises a first transistor formed on a bulk substrate region in a semiconductor substrate and having a source or drain layer connected to a first reference voltage; and a second transistor including an impurity layer region formed on the bulk substrate region and being of... Agent: Foley And Lardner LLP Suite 500

20070189060 - Semiconductor memory: A semiconductor memory having a plurality of static random access memory cells, word lines, first and second bit lines orthogonal to the word lines, and threshold voltage control lines parallel to the word lines and each of the static random access memory cell includes the first and the second driver... Agent: Foley And Lardner LLP Suite 500

20070189062 - Sram cell controlled by flash memory cell: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A... Agent: Sierra Patent Group, Ltd.

20070189064 - Multi-state thermally assisted storage: A random access memory cell is described which is capable of storing multiple information states in a single physical bit. The basic structure combines a conventional MTJ with a reference stack that is magnetostatically coupled to the MTJ. The MTJ is read in the usual way but data is written... Agent: Stephen B. Ackerman

20070189065 - Phase-change random access memory and programming method: A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming... Agent: Harness, Dickey & Pierce, P.L.C

20070189066 - Magnetic random access memory array having bit/word lines for shared write select and read operations: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for... Agent: Mario J. Donato Stmicroelectronics, Inc.

20070189067 - Dynamic memory: Device for information storage. A preferred embodiment comprises a memory with a plurality of memory cells, with each memory cell comprising a thyristor. The thyristor has three terminals: an anode terminal coupled to a first power rail, a cathode terminal coupled to a second power rail, and a gate terminal... Agent: Slater & Matsil LLP

20070189072 - Semiconductor memory device: The semiconductor memory device according to the present invention is a semiconductor memory device configured of a non-volatile memory and a volatile memory which holds a part of the data held by the non-volatile memory, and includes: j first holding units, each of which holds an address of the data,... Agent: Greenblum & Bernstein, P.L.C

20070189071 - Single latch data circuit in a multiple level cell non-volatile memory device: A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070189073 - Programming method to reduce gate coupling interference for non-volatile memory: A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.

20070189069 - Precision non-volatile cmos reference circuit: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070189068 - Semiconductor memory device and data write and read methods thereof: A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating... Agent: Marger Johnson & Mccollom, P.C.

20070189074 - Burst read circuit in semiconductor memory device and burst data read method thereof: A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequentially sense and amplifies data stored in the... Agent: Volentine & Whitt PLLC

20070189075 - Memory circuit, drive circuit for a memory and method for writing write data into a memory: A first and second non-volatile memory transistor each have a floating gate electrode and a gate terminal. A first switch is connected between a first drain terminal and a bit line for reading out information, and a second switch is connected between a second drain terminal and the bit line.... Agent: Baker Botts, L.L.P.

20070189077 - Semiconductor memory device: A programmable non-volatile semiconductor memory device having which a sufficient operational margin with miniaturized memory cells. The memory device includes select gates 3, arranged in a first region on a substrate 1, floating gates 6, arranged in a second region, neighboring to the first region, first diffusion regions 7, arranged... Agent: Mcginn Intellectual Property Law Group, PLLC

20070189076 - Memory elements and methods of using the same: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one... Agent: Ibm Corporation Intellectual Property Law Dept. 917

20070189078 - Semiconductor flash memory: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a... Agent: Leydig Voit & Mayer, Ltd

20070189079 - Memory device with page buffer having dual registers and method of using the same: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the... Agent: Marger Johnson & Mccollom, P.C.

20070189080 - Erase operation for use in non-volatile memory: A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of sectors. The sector erase method includes erasing the memory cells of a first sector by applying... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070189070 - Nonvolatile semiconductor memory device: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070189081 - Method and apparatus for erasing memory: The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential... Agent: Williams, Morgan & Amerson

20070189082 - Method for implementing a counter in a memory with increased memory efficiency: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070189083 - Semiconductor memory device comprising two rows of pads: Embodiments of the invention provide a semiconductor memory device. In one embodiment, the invention provides a semiconductor memory device comprising a first row of pads comprising a first plurality of data input/output pads; a second row of pads comprising a second plurality of data input/output pads; and a first input/output... Agent: Volentine & Whitt PLLC

20070189084 - Reduced pin count synchronous dynamic random access memory interface: A method is provided for reducing the number of conductive interfaces required to interface to a SDRAM. One or more conductive interfaces can be used, during a cycle, to both transfer data and provide a command or an address to an SDRAM. More specifically, each of the conductive interfaces on... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070189085 - Voltage generator and methods thereof: A voltage generator and methods thereof are provided. The example voltage generator may include a voltage comparison block which generates an output voltage in response to a read command, the output voltage corresponding to a difference between a reference voltage and a determination voltage and a voltage generation block which... Agent: Harness, Dickey & Pierce, P.L.C

20070189086 - Cascade wake-up circuit preventing power noise in memory device: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in... Agent: Mills & Onello LLP

20070189087 - Method and apparatus for synchronizing data from memory arrays: According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps.... Agent: Jones Day

20070189088 - Semiconductor integrated circuit and testing method therefor: The present invention provides a semiconductor integrated circuit that is provided with an address generation circuit that selectively generates an address of a memory cell substituted by a redundancy memory cell based on a defective memory cell address retained in an address retention circuit, and a control circuit that selectively... Agent: Amin, Turocy & Calvin, LLP

20070189090 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations.... Agent: Schneck & Schneck

20070189089 - Method and apparatus for implementing high speed memory: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070189092 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations.... Agent: Schneck & Schneck

20070189091 - Noise suppression in memory device sensing: NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070189093 - High performance sense amplifier and method thereof for memory system: A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly... Agent: Townsend And Townsend And Crew, LLP

20070189094 - Semiconductor memory device: This disclosure concerns a semiconductor memory device including a memory cell including a floating body in an electrically floating state and storing therein data according to number of a plurality of majority carriers accumulated in the floating body; a dummy cell generating a reference signal based on which the data... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070189096 - Active cycle control circuit and method for semiconductor memory apparatus: An active cycle control circuit includes a refresh active control signal generation unit that generates a refresh active control signal at the same cycle as a refresh request signal at a timing earlier than the refresh request signal, a refresh standby signal output unit that outputs a refresh standby signal... Agent: Venable LLP

20070189095 - Method and apparatus for an oscillator within a memory device: An apparatus for controlling generation of pulses for refresh operations of a memory device having a pad to transfer information and to receive signals from an external interface. The apparatus includes a switch, coupled to a current source and to the pad receiving signals from the external interface. The switch... Agent: Edell, Shapiro & Finnan, LLC

20070189098 - Memory module with independently adjustable power supply: A memory module with independently adjustable power supply is disconnected from a main board of a computer using the memory module, and includes a rectification circuit provided thereon. The rectification circuit is connected to a power supply of the computer, so that a supply voltage of 12V of the power... Agent: Rosenberg, Klein & Lee

20070189097 - Methods and arrangements for enhancing power management systems in integrated circuits: Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC

20070189099 - Power efficient memory and cards: A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard device as... Agent: Leffert Jay & Polglaze, P.A.

20070189100 - Semiconductor memory: A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data... Agent: Arent Fox PLLC

20070189101 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations.... Agent: Schneck & Schneck

20070189104 - Memory device with reduced word line resistance: A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the... Agent: Law Office Of Monica H Choi

20070189102 - Sram device with reduced leakage current: The present invention discloses a memory device with a leakage current reduction feature. The memory device includes at least one memory cell for storing a value, and at least one switch module coupled to the memory cell for generating an operating voltage at various levels depending on various operation modes... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070189103 - Write latency tracking using a delay lock loop in a synchronous dram: A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070189105 - Flash memory device with rapid random access function and computing system including the same: A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address... Agent: Marger Johnson & Mccollom, P.C.

20070189106 - Selectable clock unit: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.... Agent: Dickstein Shapiro LLP

20070189107 - Nonvolatile memory and apparayus and method for deciding data validity for the same: Provided are a nonvolatile memory and an apparatus and method for deciding data validity for the same, in which validity of data stored in the nonvolatile memory can be decided. The nonvolatile memory includes a memory cell storing data bits in a plurality of pages included in a predetermined block... Agent: Sughrue Mion, PLLC

20070183180 - Option circuits and option methods of semiconductor chips: An option circuit of a semiconductor chip includes a first option circuit that is set before packaging the semiconductor chip to generate a first option signal; a second option circuit that is set after packaging the semiconductor chip to generate a second option signal; and a selection circuit configured to:... Agent: Harness, Dickey & Pierce, P.L.C

20070183178 - Semiconductor memory device: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the... Agent: Miles & Stockbridge PC

20070183179 - Semiconductor memory card, access device and method: A card information-storing portion is provided in a semiconductor memory card, and information relating to access performance such as access condition and access rate is held in the storing portion. Further, an access device acquires the held information from the semiconductor memory card to make it possible that the information... Agent: Randolph A Smith Smith Patent Office

20070183181 - Electrically programmable fuse bit: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories,... Agent: Perkins Coie LLP Patent-sea

20070183182 - Differential anti-pinch capacitive sensor: A proximity sensor for sensing an object in the path of or proximate to a closure panel such as a vehicle window. First and second electrodes encased in a non-conductive casing are mounted on the metallic structure near the closing edge of the aperture. The two electrodes define a capacitance... Agent: Clark Hill, P.C.

20070183183 - Method and device for controlling a matrix plasma display screen: A control device for a matrix plasma display screen has a row driver circuit capable of sequentially selecting the rows of the matrix and a column driver circuit, for each column of the matrix, with an individual column driver unit that has at least a first transistor of the MOS... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070183184 - Apparatus and method for manufacturing semiconductor device: The manufacturing apparatus of a semiconductor device includes a jig having a plurality of holders arranged in a row, a controller for controlling the pitch of the plurality of holders arranged in a row, a support means provided with a plurality of semiconductor integrated circuits, and a support means provided... Agent: Nixon Peabody, LLP

20070183185 - Finfet-based sram with feedback: Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor... Agent: John P. O'banion O'banion & Ritchey LLP

20070183188 - Magnetic device using magnetic domain dragging and method of operating the same: Example embodiments may provide a magnetic device using magnetic domain dragging and a method of operating the same. An example embodiment magnetic device may include a data storage cell with a free layer having a switchable magnetization direction and a plurality of adjoining magnetic domains, a reference layer formed to... Agent: Harness, Dickey & Pierce, P.L.C

20070183186 - Mram based on vertical current writing and its control method: The invention discloses a MRAM (Magnetoresistive RAM) based on vertical current writing and its control method, the operation of information writing in the MRAM unit is completed by the corporate effect of the magnetic field generated by the current parallel to the MFC unit and the other current vertical to... Agent: Lucas & Mercanti, LLP

20070183187 - Synthetic anti-ferromagnetic structure with non-magnetic spacer for mram applications: A toggle MTJ cell is disclosed that has a nearly balanced SAF free layer with two major sub-layers separated by an anti-parallel coupling layer. Within each major sub-layer, there is a plurality of minor sub-layers wherein adjacent minor sub-layers are separated by a parallel coupling layer. The parallel coupling layer... Agent: Stephen B. Ackerman

20070183189 - Memory having nanotube transistor access device: A memory cell includes a memory element and a nanotube transistor contacting the memory element for accessing the memory element.... Agent: Dicke, Billig & Czaja

20070183190 - Method for ultra-fast controlling of a magnetic cell and related devices: The present invention relates to a device and corresponding method for ultrafast controlling of the magnetization of a magnetic element. A device (100) includes a surface acoustic wave generating means (102), a transport layer (104), which is typically functionally and partially structurally comprised in said SAW generating means (102), and... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070183191 - Stacked capacitor memory: Stacked capacitor memory is realized, wherein a capacitor stores data and a diode serves as an access device instead of MOS transistor, the first terminal is connected to a word line, the second terminal is connected to the first electrode of the capacitor which serves as a storage node while... Agent: Juhan Kim

20070183192 - Memory controller operating in a system with a variable system clock: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070183197 - 3-level non-volatile semiconductor memory devices and related methods: A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured... Agent: Scott C. Hatfield Myers Bigel Sibley & Sajovec, P.A.

20070183194 - Controlling access to device-specific information: A method for providing access to device-specific information includes providing a first value to the device, and then, in the device, using a second value that is a first one-way function of the provided first value to determine a third value such that the third value is a device-specific function... Agent: Occhiuti Rohlicek & Tsao, LLP

20070183196 - Non-volatile memory device with periodic refresh and method of programming such a device: A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then... Agent: Jenkens & Gilchrist, PC

20070183195 - Voltage detecting apparatus: Providing a voltage detecting apparatus, which can detect rapidly a malfunction of a battery for a car structured by connecting a plurality of unit cells in series, a whole voltage value of both ends of a cell block corresponding a voltage detecting circuit assigned by a low-voltage CPU and a... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070183198 - Memory card and memory card system: A memory card is equipped in a host apparatus and used for data recording. The memory card has a built-in flash memory and an internal ROM, there is prestored a predetermined writable block size corresponding to a certain integral multiple of a size of an erase block. A write block... Agent: Wenderoth, Lind & Ponack L.L.P.

20070183200 - Nonvolatile semiconductor memory device provided with data register for temporally holding data in memory array: A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking the signal including the pulse every access cycle with respect to the data register when access to a... Agent: Buchanan, Ingersoll & Rooney PC

20070183199 - Page buffer circuit of flash memory device and program operation method thereof: A page buffer circuit includes a bit line selection circuit, a main register, a program transmission circuit, a temporary register, and a verification transmission circuit. The verification transmission circuit transmits data stored in the temporary register to the main register through a sensing node in response to a transmission control... Agent: Townsend And Townsend And Crew, LLP

20070183201 - Non-volatile memory device and manufacturing process: A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein,... Agent: Seed Intellectual Property Law Group PLLC

20070183204 - Nand-type nonvolatile memory devices having common bit lines and methods of operating the same: A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors,... Agent: Harness, Dickey & Pierce, P.L.C

20070183203 - Three-level non-volatile semiconductor memory devices with lower and upper bit lines sharing a voltage control block: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common... Agent: Myers Bigel Sibley & Sajovec

20070183202 - Memory array segmentation and methods: The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070183205 - Semiconductor memory device controlling program voltage according to the number of cells to be programmed and method of programming the same: A semiconductor memory device controlling a program voltage according to the number of cells to be programmed and a method of programming the same. The semiconductor memory device includes a memory cell array. A write data buffer receives write data in a predetermined unit. A program cell counter calculates the... Agent: F. Chau & Associates, LLC

20070183206 - Semiconductor nonvolatile memory device: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be... Agent: Miles & Stockbridge PC

20070183193 - Controlling a nonvolatile storage device: A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge... Agent: Wagner, Murabito & Hao LLP

20070183210 - Program method of flash memory capable of compensating read margin reduced due to charge loss: The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states... Agent: Volentine & Whitt PLLC

20070183208 - Nonvolatile semiconductor memory device and data writing method therefor: A plurality of memory cell transistors each of which has a gate structure having a floating gate electrode formed of a first conductive film and stacked on an element region surrounded by an element isolation region on a silicon substrate with a first insulating film disposed therebetween and a control... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070183209 - Thin hard drive with 2-piece-casing and ground pin standoff to reduce esd damage to stacked pcba's: A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening between the cases. The cases can be assembled with the... Agent: Stuart T Auvinen

20070183207 - Word line voltage generator and flash memory device including the same, and method of generating word line voltage thereof: A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a... Agent: Mayer, Brown, Rowe & Maw LLP

20070183213 - Nonvolatile semiconductor memory device: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one... Agent: Mcdermott Will & Emery LLP

20070183214 - Semiconductor device undergoing defect detection test: A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion... Agent: Mcdermott Will & Emery LLP

20070183212 - Semiconductor memory device: A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the... Agent: Mcginn Intellectual Property Law Group, PLLC

20070183211 - Semiconductor device and method of controlling the same: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to... Agent: Wagner, Murabito & Hao LLP Third Floor

20070183215 - Nonvolatile semiconductor memory device and method of writing data into the same: In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the... Agent: Sughrue Mion, PLLC

20070183216 - Reprogrammable nonvolatile memory devices and methods: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array.... Agent: Myers Bigel Sibley & Sajovec

20070183217 - Nonvolatile semiconductor memory device and method of rewriting data thereof: The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between two memory cells comprising a memory cell pair, and a writing controller for writing data to the memory cell array.... Agent: Mcdermott Will & Emery LLP

20070183218 - Gate driving unit and display apparatus having the same: In a gate driving unit and a display apparatus, a first gate driving circuit is connected to a first end of a plurality of gate lines, a second gate driving circuit is connected to a second end of the gate lines, and they are substantially simultaneously turned on. The first... Agent: H.c. Park & Associates, PLC

20070183219 - Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high... Agent: Marger Johnson & Mccollom, P.C.

20070183221 - Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same: An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070183222 - Semiconductor memory device: A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control... Agent: Mcginn Intellectual Property Law Group, PLLC

20070183220 - Erase operation in a flash memory device: A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070183223 - Memory block erasing in a flash memory device: The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory cells have been found, a normal memory read operation is performed in order to determine which memory cells are still programmed. A selective erase operation... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070183224 - Buffer configuration for a data replication system: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is... Agent: Knobbe Martens Olson & Bear LLP

20070183225 - Integrated semiconductor memory devices with generation of voltages: An integrated semiconductor memory device includes a clock terminal that applies an external clock signal. Read and write accesses are controlled synchronously with the external clock signal. A frequency detector is connected to the clock terminal to detect the frequency of the external clock signal. The frequency detector circuit generates... Agent: Edell, Shapiro & Finnan, LLC

20070183226 - Semiconductor integrated circuit device: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070183227 - Delay line circuit: Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are... Agent: Brooks & Cameron, PLLC

20070183229 - Multi chip package and related method: A Multi Chip Package (MCP) and a related method for enabling a cell in the MCP are provided. In one embodiment, the MCP comprises a first memory device and a second memory device storing repair address information about the first memory device.... Agent: Volentine & Whitt PLLC

20070183228 - Control signal interface circuit for computer memory modules: The present system is an electronic circuit designed for incorporation on high-speed computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast... Agent: Steptoe & Johnson LLP

20070183230 - Memory redundance circuit techniques: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can... Agent: Mcandrews Held & Malloy, Ltd

20070183231 - Method of operating a memory system: The memory system has a current source architecture that has a separate current source for each group in a block of memory. When a leaky cell is detected, a fuse between the current source and the leaky group of cells is blown and a spare group of memory is substituted... Agent: Law Office Of Dale B. Halling, LLC

20070183233 - Semiconductor integrated circuit device: There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070183232 - Semiconductor memory device: In a semiconductor memory device employing shared type sense amplifiers, entry is made to the test mode, and transfer gates, pre-charge circuits, and sense amplifiers used in the shared type sense amplifiers are controlled individually. An object bit line is placed in the high impedance state. The opposing sense amplifier... Agent: Mcginn Intellectual Property Law Group, PLLC

20070183235 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first sub bank meets the second sub bank. A first precharge section is arranged above the first... Agent: Venable LLP

20070183234 - Semiconductor memory device having reduced voltage coupling between bit lines: An enhanced semiconductor memory device capable of eliminating or minimizing a cell data flip phenomenon caused by capacitive voltage coupling between bit lines in different bit line pairs. Each memory cell is connected to a word line and between a pair of bit line. A first precharging and equalizing circuit... Agent: F. Chau & Associates, LLC

20070183236 - Circuit and method for supplying power to sense amplifier in semiconductor memory apparatus: A circuit for supplying power to a sense amplifier in a semiconductor memory apparatus includes: a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal. A power compensating unit supplies a compensation voltage input node, which is applied with... Agent: Venable LLP

20070183237 - Apparatus for sensing data of semiconductor integrated circuit: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP

20070183239 - Semiconductor memory device including plurality of memory mats: A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latch portion. The sense latch portion and the... Agent: Mcdermott Will & Emery LLP

20070183238 - Enhanced sensing in a hierarchical memory architecture: A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to... Agent: Wayne L. Ellenbogen Ryan, Mason & Lewis, LLP

20070183240 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory of virtual ground array in which a common connection of the sources and a common connection of the drains of nonvolatile memory cells arranged in rows and columns in a memory cell array are used as bit lines, the nonvolatile memory cells including: a reference cell... Agent: Mcdermott Will & Emery LLP

20070183241 - First-in first-out (fifo) memory with multi-port functionality: A memory may require buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding... Agent: Docket Clerk

20070183242 - Memory: A memory capable of suppressing increase in circuit size, reduction in a period for an original access and increase in power consumption while suppressing an imprint can be obtained. The memory includes a first count detection circuit for detecting an access frequency with respect to memory cells, a second count... Agent: Mcdermott Will & Emery LLP

20070183243 - Memory synchronization method and refresh control circuit: Rank numbers specified by a second counter are refreshed in sequence by using a count value of a first counter which is initialized by a synchronous reset signal and counts timing for performing refresh, and the rank numbers specified by a refresh rank control unit are continuously refreshed in sequence... Agent: Mcginn Intellectual Property Law Group, PLLC

20070183244 - Electric fuse circuit providing margin read function: An electric fuse circuit including a first nonvolatile memory cell connected to a first bit line, a second nonvolatile memory cell connected to a second bit line, a latch connected to the first and second bit lines, and a bias current circuit supplying one of the first and second bit... Agent: F. Chau & Associates, LLC

20070183245 - Voltage reset circuits for a semiconductor memory device using option fuse circuit and methods of resetting the same: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage... Agent: Myers Bigel Sibley & Sajovec

20070183246 - Internal voltage generation circuit of semiconductor memory device: An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level... Agent: Ladas & Parry LLP

20070183247 - Semiconductor device: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070183248 - Bank controller, information processing device, imaging device, and controlling method: A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070183249 - Command decoder circuit of semiconductor memory device: A command decoder circuit generates command signals for performing internal operations and according to external command signals, according to values of the write latency values and whether write latency is an even numbered or odd-numbered value.... Agent: Ladas & Parry LLP

20070183250 - High speed, low power, low leakage read only memory: A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such... Agent: Docket Clerk

20070183251 - Simplified power-down mode control circuit utilizing active mode operation control signals: A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in... Agent: Ladas & Parry LLP

20070177413 - Storage system and storage control device: Virtualization arrangements, including: splitting a relationship between a first and second virtual volume; receiving a differential copying request; if the differential copying request indicates to copy differential data from one of the first and second virtual volume to the other of the first and second virtual volume, (1) controlling to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070177414 - Magnetic field probe apparatus and a method for measuring magnetic field: A magnetic field probe apparatus includes a loop-like conductor and feeder lines spaced at a distance from the loop-like conductor. The shape of the loop-like conductor and the arrangement of the feeder lines are adjusted in such a manner that the resonance frequency determined by the combination of the inductance... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070177415 - High performance mass storage systems: A data access system for accessing data stored in a first and a second memory devices. The first and second memory devices have a difference of latency ΔL that constitutes a time-duration by which the first memory device starts an initial data access earlier than in the second memory device.... Agent: Jeng-jye Shau

20070177416 - Semiconductor storage device and method of fabricating the same: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first... Agent: Mcdermott Will & Emery LLP

20070177417 - High-speed capacitor leakage measurement systems and methods: Systems and methods according to aspects of the present invention are described. The systems and methods enable charging, soaking, and measuring of capacitors to be conducted quickly. Charging and soaking typically occurs in parallel and certain embodiments facilitate the measuring of capacitor leakage by sequentially disconnecting each capacitor and measuring... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070177418 - Nanoelectromechanical memory cells and data storage devices: Nanoelectromechanical (NEM) memory cells are provided. More particularly, NEM memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion in which a charge... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070177419 - Asymmetric four-transistor sram cell: An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second... Agent: Gowling Lafleur Henderson LLP

20070177421 - Magnetoresistance effect element and magnetic memory: It is made possible to cause spin inversion at a low current density which does not cause element destruction and to conduct writing with a small current. A magnetoresistance effect element includes: a magnetization pinned layer in which magnetization direction is pinned; a magnetic recording layer in which magnetization direction... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070177420 - Magnetic random access memory with selective toggle memory cells: A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni˜0.8Fe˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher... Agent: Stephen B. Ackerman

20070177422 - Capacitor boost sensing: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected... Agent: Texas Instruments Incorporated

20070177423 - Flash memory device having bit lines decoded in irregular sequence: An embodiment of a flash memory device comprises a cell array including memory cells coupled to bit lines, a decoder configured to decode successive logical column addresses into physical column addresses that are arranged non-sequentially, and a gate circuit to partially select the bit lines in response to the decoded... Agent: Marger Johnson & Mccollom, P.C.

20070177424 - Device with n-time pad and a method of managing such a pad: Data from an n-time pad is used in security-related tasks. To accommodate use of the pad with security-related tasks of different security ratings, the maximum number of times any particular data from the pad is used is determined by the security rating of the highest-security application using that data.... Agent: Hewlett Packard Company

20070177425 - A method and apparatus for repairing embedded memory in an integrated circuit: A method and apparatus for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element... Agent: Ibm Microelectronics Intellectual Property Law

20070177426 - System and method for automated delivery of software payload: The present invention discloses a system and method for delivery of software payload from a peripheral device to a host system, with generally one component of the software payload enabling the host system to communicate with the peripheral device. The method of the present invention uses an electronic component/storage device... Agent: Don Carnegie

20070177427 - Nonvolatile memory device and method thereof: A nonvolatile memory device and method thereof are provided. The example method may include applying a first bias voltage to a gate electrode, applying a second bias voltage to a substrate to obtain a first voltage potential difference between the gate electrode and the substrate and applying a third bias... Agent: Harness, Dickey & Pierce, P.L.C

20070177430 - Data transfer apparatus, information recording and reproducing apparatus, and data transfer method: A data transfer apparatus that performs burst transfer includes a buffer memory that temporarily stores data sent from a sending apparatus, and a control unit that controls data transfer to and from the sending apparatus. When an amount of free space in the buffer memory is equal to or less... Agent: Knobbe Martens Olson & Bear LLP

20070177428 - Memory circuit arrangement and method for reading and/or verifying the status of memory cells of a memory cell array: A memory circuit arrangement includes a memory cell array having a plurality of memory cells. A memory read/verify control circuit controls a read operation and/or a verify operation on one or a plurality of memory cells of the memory cell array. The memory read/verify control circuit is adapted to read... Agent: Slater & Matsil LLP

20070177429 - Nonvolatile semiconductor memory and nonvolatile memory system using thereof: A nonvolatile semiconductor memory that have a a plurality of bit lines and word lines disposed crossing each other; a memory cell array having a plurality of electrically-programmable memory cells disposed in a region where the bit lines and the word lines are crossing; a trimming circuit which is operated... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070177431 - Semiconductor integrated circuit device: There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070177434 - Three-level nonvolatile semiconductor memory device and associated method of operation: A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and... Agent: Volentine & Whitt PLLC

20070177436 - Memory system and method for two step memory write operations: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070177433 - Method and system for data security of recording media: Described embodiments generally relate to methods of encoding data on a data storage medium and methods of decoding and reading such encoded data. Other aspects relate to systems or apparatus for performing these methods. Still other aspects relate to systems and methods for monitoring use of data recorded on data... Agent: Bereskin And Parr

20070177432 - Phase change memory latch: A non-volatile memory latch may be formed with a phase change memory layer. Such a latch may be faster and more easily integrated into main stream semiconductor processes than conventional latches that use non-volatile memory elements such as flash memory.... Agent: Trop Pruner & Hu, PC

20070177435 - System for multiple wireless local area networks: A system is provided for a wireless local area network. The system includes, but is not limited to, at least one cell controller and simplified RF ports which are configured to provide lower level media access control functions. Higher level media access control functions are provided in a cell controller,... Agent: Ingrassia Fisher & Lorenz, P.C.

20070177437 - Nano molecular modeling method: A nano-technology modeling method wherein a group of atoms and an interaction thereof to an open environment are defined by Hamiltonian matrices and overlap matrices, matrix elements of the matrices being obtained by a tight-binding (TB) fitting of system parameters to a first principles atomistic model based on density functional... Agent: Goudreau Gage Dubuc

20070177438 - Method of driving transistor and shift register performing the same: A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal having a second... Agent: Cantor Colburn, LLP

20070177439 - Displaying supply information of an image forming apparatus: An apparatus, method, system, computer program and product, each capable of managing supply information of an image forming device provided in an image forming apparatus, and displaying the supply information.... Agent: Dickstein Shapiro LLP

20070177441 - Memory device having redundancy fuse blocks arranged for testing: A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may be alternately... Agent: Marger Johnson & Mccollom, P.C.

20070177440 - Method for multiple step programming a memory cell: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over... Agent: Freescale Semiconductor, Inc. Law Department

20070177442 - Low voltage data path and current sense amplifier: Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the... Agent: Brooks & Cameron, PLLC

20070177443 - Semiconductor memory device: This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070177444 - Semiconductor device having super junction structure and method for manufacturing the same: A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and... Agent: Posz Law Group, PLC

20070177445 - Semiconductor device: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070177447 - Memory having a layer with electrical conductivity anisotropy: A data storage device comprises a media including a memory layer within which are formable domains associated with information, and a conductive layer disposed over the memory layer, the conductive layer having anisotropically increased electrical conductivity in a thickness direction. A conductive tip contactable with the conductive layer is adapted... Agent: Fliesler Meyer LLP

20070177446 - System and method for application configuration for performance test: The present invention enables a performance testing framework that enables multiple components working together to test a deployed application automatically in an unattended manner and to analyze the test results easily. At very high level, the performance testing framework can run performance tests on a tested system with one or... Agent: Fliesler Meyer LLP

20070177448 - Access port for use in electrochemical cells: An electrochemical cell, comprising: an encasement including a case having a bottom and a sidewall terminating at an open top and a cover disposed over the case open top and hermetically sealed to the case, the encasement defining an interior space for containing cell components; and an access port defining... Agent: Medtronic, Inc.

20070177449 - Semiconductor memory, memory controller and control method for semiconductor memory: Semiconductor memory for inputting and outputting data synchronously with a clock, comprising: a clock reception unit for receiving the clock; and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed... Agent: Arent Fox PLLC