Static information storage and retrieval inventions 07/07

20070171691 - Semiconductor device with electrically broken fuse and its manufacture method: An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor including a source region, a drain region and a... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070171692 - Semiconductor integrated circuit device: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface... Agent: Antonelli, Terry, Stout & Craus

20070171694 - Current-switched spin-transfer magnetic devices with reduced spin-transfer switching current density: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having one or more spin diffusion layers to diffuse the electron spins outside the MTJ or spin valve structure to reduce the spin transfer switching current for switching the free layer.... Agent: Fish & Richardson, PC

20070171695 - Magnetic memory composition and method of manufacture: A sensing device includes a sensor, a control unit, an input/output (I/O) interface, and a non-volatile magnetic memory device having one or more memory cells, each of the memory cells, wherein each memory cell of the non-volatile magnetic memory device includes a magnetic switch including a magnetic component and a... Agent: Morgan Lewis & Bockius LLP

20070171696 - Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a... Agent: Bryan A. Santarelli

20070171693 - Semiconductor device, wireless chip, ic card, ic tag, transponder, bill, securities, passport, electronic apparatus, bag, and garment: The invention provides an ID chip to which data can be written only once in order to maintain high security as a non-contact type ID chip to which signals are inputted wirelessly from an antenna. A non-contact type ID chip includes a nonvolatile FeRAM in the chip. Data representative of... Agent: Eric Robinson

20070171697 - Cbram memory device and method for writing to a resistive memory cell in a cbram memory device: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070171698 - Memory circuit including a resistive memory element and method for operating such a memory circuit: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070171699 - Mounting apparatus for data storage devices: A mounting apparatus is provided for a data storage device defining a mounting hole. The mounting apparatus includes a bracket for accommodating the data storage device and a locking latch. The bracket includes a side plate forming a cantilever thereon. A receiving portion is formed at a free end of... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070171700 - Electronic device including a static-random-access memory cell and a process of forming the electronic device: An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have... Agent: Larson Newman Abel Polansky & White, LLP

20070171701 - Semiconductor memory device: A semiconductor memory device includes a plurality of word lines arranged above a semiconductor substrate to extend in a row direction; a plurality of digit lines arranged above the semiconductor substrate to extend in a column direction orthogonal to the row direction; a power supply line arranged in parallel to... Agent: Sughrue Mion, PLLC

20070171703 - Current source of magnetic random access memory: A current source for magnetic random access memory (MRAM) is provided, including a band-gap reference circuit, a first stage buffer, and a plurality of second stage buffers. The band-gap reference circuit provides an output reference voltage which is locked by the first stage buffer. The plurality of second stage buffers... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070171704 - High-bandwidth magnetoresistive random access memory devices and methods of operation thereof: A method for accessing a memory cell of a magnetoresistive random access memory (MRAM) device, where the memory cell includes a plurality of memory units, includes writing the memory cell by identifying ones of the memory units having stored therein a datum different from a datum to be written thereto;... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070171702 - Novel programming scheme for segmented word line mram array: An MRAM array has a plurality of MRAM devices that are arranged in rows and columns with segmented word lines. A magnetic biasing field is coupled to each of the MRAM devices. The MRAM devices are programmed by providing a bidirectional bit line current to a selected bit line of... Agent: George O. Saile

20070171706 - Semiconductor memory device: A memory cell has a heater element which generates heat by supplying electric current, a chalcogenide layer whose phase is changed by applying heat, and two transistors for driving the heater element. Bit lines extend in a predetermined direction and electrically connect with memory cells. Word lines extend at right... Agent: Sughrue Mion, PLLC

20070171705 - Writing phase change memories: In accordance with some embodiments, the endurance of phase change memory cells may be increased. This increase may be accomplished with adequate margin by reducing the current used to write the reset state. Generally, that current will be a current less than the saturated current.... Agent: Trop Pruner & Hu, PC

20070171707 - Nonvolatile carbon nanotube memory device using multiwall carbon nanotubes and methods of operating and fabricating the same: A nonvolatile carbon nanotube memory device using multiwall carbon nanotubes and methods of operating and fabricating the same are provided. The nonvolatile memory device may include a substrate, at least one first electrode on the substrate, first and second vertical walls on the at least one first electrode spaced from... Agent: Harness, Dickey & Pierce, P.L.C

20070171711 - Non-volatile memory device and method of operation therefor: In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells.... Agent: Harness, Dickey & Pierce, P.L.C

20070171709 - Program method for flash memory capable of compensating for the reduction of read margin between states: The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method may include programming memory cells, connected with a selected row and the second... Agent: Volentine & Whitt PLLC

20070171710 - Semiconductor storage device and method of using semiconductor storage device: A memory cell array includes a memory cell transistor storing data of a value in accordance with a set threshold voltage. A writing control unit controls writing of data in the memory cell transistor. A memory cell driving unit writes data in the memory cell transistor under the control of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070171708 - Multi-level memory cell sensing: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.... Agent: Lemoine Patent Services, PLLC C/o Portfolioip

20070171712 - Bitline transistor architecture for flash memory: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070171713 - Electronic device and method for operating a memory circuit: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance... Agent: Larson Newman Abel Polansky & White, LLP

20070171714 - Flash memory with coding and signal processing: A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory... Agent: Townsend And Townsend And Crew LLP

20070171715 - Non-volatile semiconductor memory device using adjacent bit lines for data transmission and method of driving the same: A non-volatile semiconductor memory device, including a memory array having a plurality of first bit line groups and a plurality of second bit line groups that are alternately arranged to be adjacent each other, a plurality of data lines, a plurality of first page buffers, a plurality of second page... Agent: F. Chau & Associates, LLC

20070171716 - System and method for visualizing configurable analytical spaces in time for diagrammatic context representations: A system and method are provided for generating a plurality of environments for a diagrammatic domain coupled to a temporal domain, such that each of the environments has a plurality of nodes and links between the nodes to form a respective information structure. The system and method include storage for... Agent: Gowling Lafleur Henderson LLP 1 First Canadian Place

20070171717 - Dynamic matching of signal path and reference path for sensing: A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense... Agent: Empk & Shiloh, LLP

20070171718 - Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages: Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in... Agent: Vierra Magen/sandisk Corporation

20070171719 - Method for programming non-volatile memory with reduced program disturb using modified pass voltages: Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. -In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in... Agent: Vierra Magen/sandisk Corporation

20070171720 - Nonvolatile semiconductor storage device: In a nonvolatile semiconductor storage device having a plurality of NAND strings, each NAND string includes a memory cell block obtained by connecting a plurality of nonvolatile memory cells in series, a first selection gate transistor connected to a data transfer line contact, and a second selection gate transistor connected... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070171721 - Semiconductor memory device capable of high-speed cache read operation: Primary data caches are connected to a common signal line, and secondary data caches are connected to an I/O data line. While data in the secondary data cache is being output to the I/O data line, the common signal line is used to make determinations for data in flag cells.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070171722 - Flash memory system compensating reduction in read margin between memory cell program states: A memory system includes a flash memory and a memory controller configured to control the flash memory. The memory controller determines whether program data provided from a host are all stored in the flash memory during a program operation. When the determination result is that the program data are all... Agent: Volentine & Whitt PLLC

20070171723 - Nor flash memory and related read method: A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of... Agent: Volentine & Whitt PLLC

20070171724 - Counteracting overtunneling in nonvolatile memory cells: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from... Agent: Impj - Thelen Reid Brown Raysman & Steiner LLP

20070171726 - Program method of flash memory capable of compensating reduction of read margin between states due to hot temperature stress: A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data;... Agent: Volentine & Whitt PLLC

20070171725 - Non-volatile memory with improved program-verify operations: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070171727 - Flash memory device with program current compensation: A memory device includes a flash memory cell array comprising a plurality of flash memory cells, a program voltage generator circuit configured to generate a program voltage at an output thereof and a program circuit coupled to the output of the program voltage generator circuit and configured to couple the... Agent: Myers Bigel Sibley & Sajovec

20070171728 - Nor flash memory and erase method thereof: A NOR flash memory includes a plurality of main cells, a plurality of main word lines, a plurality of dummy cells, and a plurality of dummy word lines. The main cells are electrically connected to a bit line and are arranged in a pattern. The main word lines are each... Agent: Myers Bigel Sibley & Sajovec

20070171729 - Memory block erasing in a flash memory device: The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then performed for an increasing sensing time period until either all of the memory cells of the block have a threshold voltage that is... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070171730 - Method and system for error correction in flash memory: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is... Agent: Townsend And Townsend And Crew LLP

20070171732 - Organic memory: An organic memory is provided. The organic memory at least comprises a plurality of select lines, a plurality of data lines, a bit cell array, and a plurality of digital sensing circuits. The bit cell array comprises a plurality of bit cells, wherein each bit cell comprises an organic memory... Agent: Jianq Chyun Intellectual Property Office

20070171731 - Leakage mitigation logic: Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch... Agent: Nixon & Vanderhye, PC

20070171733 - Timing circuit cad: A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprise steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said... Agent: Dechert LLP

20070171734 - Transistor level shifter circuit: A transistor level shifter circuit constituted by a plurality of PMOS TFT is disclosed. The transistor level shifter circuit primarily comprises a conversion circuit, a first amplifier circuit, and a second amplifier circuit. With the simplified circuit arrangement and a smaller quantity of required transistors, the transistor level shifter circuit... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20070171735 - Latency circuit for semiconductor memories: A random access memory includes an array of memory cells, a mode register and a controller. The mode register is configured to hold a programmable minimum timing requirement. The controller is configured to retrieve the programmable minimum timing requirement and to access the array of memory cells in a double... Agent: Dicke, Billig & Czaja

20070171737 - Semiconductor storage device: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070171736 - Method and apparatus for repairing a shorted tunnel device: A method for repairing a shorted tunnel device includes the step of applying a stressing signal to the tunnel device. The stressing signal has an amplitude that is greater than an amplitude of a bias signal applied to the device during normal operation. One or more characteristics of the stressing... Agent: Ryan, Mason & Lewis, LLP

20070171738 - Semiconductor memory device: A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal... Agent: F. Chau & Associates, LLC

20070171743 - Semiconductor memory device capable of writing different data in cells coupled to one word line during burn-in test: A semiconductor memory device includes a row decoder, a control circuit, and a memory cell array having an open bit-line structure. The memory cell array includes a plurality of word lines coupled to the row decoder, a plurality of bit lines, a plurality of memory cells, a plurality of sense... Agent: Mills & Onello LLP

20070171742 - Semiconductor memory device having an open bit line structure, and method of testing the same: A memory core having an open bit line structure and a semiconductor memory device having the memory core includes an edge sub-array and a dummy bit line control circuit. The edge sub-array has a plurality of word lines, a plurality of bit lines and a plurality of dummy bit lines.... Agent: F. Chau & Associates, LLC

20070171739 - Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices: A semiconductor memory device includes a flash memory, a buffer memory configured to receive expected data for testing for failed bits in the flash memory, and a failed bit control unit configured to receive the expected data from the buffer memory, to receive read data from the flash memory, and... Agent: Myers Bigel Sibley & Sajovec

20070171740 - Semiconductor memory module and semiconductor memory device: A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a... Agent: Volentine & Whitt PLLC

20070171741 - Method of curing analog device fail through fast transistor: Disclosed is a method of curing a failure of an analog device, wherein the operational range of a transistor is optimized, thereby curing a failure in the analog device and enhancing a yield. In the method, the target of the 1.5V high transistor is modified to a fast condition, thereby... Agent: Sherr & Nourse, PLLC

20070171745 - Bleq driving circuit in semiconductor memory device: A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply voltage, a BLEQ driver for generating the equalization signal by... Agent: Lowe Hauptman Berner, LLP

20070171744 - Memories with alternate sensing techniques: The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070171747 - Memory and method for sensing data in a memory using complementary sensing scheme: In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a... Agent: Larson Newman Abel Polansky & White, LLP

20070171746 - Non-volatile memory with power-saving multi-pass sensing: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070171748 - Sense amplifier circuit: A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining... Agent: Barnes & Thornburg LLP

20070171749 - Device having an array of non-volatile memory cells and a method for altering a state of a non-volatile memory cell: An array of non-volatile memory cells and a method for altering a state of a non-volatile memory cell that comprises multiple terminals, a substrate, and a charge retainer surrounded by an insulator, the method includes: illuminating the substrate with light such as to create electron-hole pairs within a first portion... Agent: Sonnenschein Nath & Rosenthal LLP

20070171751 - Device and method for controlling refresh rate of memory: A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in... Agent: Madson & Austin Gateway Tower West

20070171750 - Apparatus and method for self-refreshing dynamic random access memory cells: A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled... Agent: Borden Ladner Gervais LLP

20070171752 - Method and system for low power refresh of dynamic random access memories: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070171753 - Method and system for low power refresh of dynamic random access memories: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070171754 - Security circuit using at least two finite state machine units and methods using the same: A security circuit using at least two finite state machine units for storing data to and reading data from a multiport memory in a pipelined manner and an intermediate memory, for facilitating transfer of data between the at least two finite state machines. The security circuit may be used to... Agent: Harness, Dickey & Pierce, P.L.C

20070171755 - Semiconductor memory device and method therefor: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or... Agent: Marger Johnson & Mccollom, P.C.

20070171758 - Semiconductor memory device adapted to communicate decoding signals in a word line direction: A semiconductor memory device comprising decoding signals communicated solely in a word line direction is provided. The semiconductor memory device comprises a sub-array comprising a plurality of memory cells, a plurality of enable signal generators adapted to generate word line enable signals, a plurality of decoding signal generators adapted to... Agent: Volentine & Whitt PLLC

20070171756 - Double byte select high voltage line for eeprom memory block: A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows... Agent: Schneck & Schneck

20070171757 - System and method of selective row energization based on write data: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform... Agent: Ibm Corp. (clg) C/o Cardinal Law Group

20070171759 - Semiconductor memory device, system and method of testing same: A semiconductor memory device includes a plurality of address pads, a plurality of DQ pads, an address buffer, a data input buffer, a latch circuit and a first delay circuit. The address buffer receives a plurality of first address signals through the address pads and buffers the first address signals... Agent: Frank Chau, Esq. F.chau & Associates, LLC

20070171763 - Circuit and method for controlling write recovery time in semiconductor memory device: A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time... Agent: Marger Johnson & Mccollom, P.C.

20070171762 - Method and apparatus to control sensing time for nonvolatile memory: One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070171760 - Apparatus and method for trimming static delay of a synchronizing circuit: A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals provided by a DLL. For trimming an unadjusted forward delay, delay is added to one of a feedback clock signal path and an... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070171761 - Methods and tangible objects employing machine readable data: The present invention relates generally to steganography. In one implementation we provide a method comprising: receiving optical scan data representing at least a portion of a physical object. The physical object includes information steganographically hidden thereon, and the information includes at least some information indicating an operation of the physical... Agent: Digimarc Corporation

20070165434 - Resistive ram having at least one varistor and methods of operating the same: Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at... Agent: Harness, Dickey & Pierce, P.L.C

20070165436 - High-speed and low-power differential non-volatile content addressable memory cell and array: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal,... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070165435 - Low-power cam: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's... Agent: Macpherson Kwok Chen & Heid LLP

20070165438 - Inverter test device and a method thereof: The present invention discloses an inverter test device and a method thereof, which provides a single-load environment or a multi-load test environment to test electrical performance of an inverter or inverters, including: unbalanced current comparison, phase comparison, current/voltage deviation, and fusion heat (I2T), and record the test results, wherein the... Agent: Birch Stewart Kolasch & Birch

20070165437 - Method and apparatus for testing integrated circuits for susceptibility to latch-up: A test module for testing the susceptibility of an integrated circuit design to latch-up, the test module comprising a plurality of test blocks (30), connected in parallel, each test block (30) comprising an injector block (12) for applying a stress current or voltage to the respective test block (30), and... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070165439 - Edge pad architecture for semiconductor memory: A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and... Agent: Dicke, Billig & Czaja

20070165440 - System and device for managing control data: In one embodiment, a content data management system that handles control information on management of content data decryption includes a first device (a recorder/player) for recording/reproducing the content data, a second device (a magnetic disk drive) for storing the content data, and a host processor for controlling data transfer between... Agent: Townsend And Townsend And Crew LLP

20070165441 - High speed otp sensing scheme: A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on... Agent: Borden Ladner Gervais LLP

20070165442 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor device is configured so that a load circuit applying voltage to a variable resistive element is provided electrically connecting in series to the variable resistive element, a load resistive characteristic of the load circuit can be switched between two different characteristics. The two load resistive characteristics are... Agent: Nixon & Vanderhye, PC

20070165443 - Memory-enhanced image sensor: An image sensor IC may have a non-volatile memory for several functions. The functions may include storing control parameters for a camera autofocus module, part tracking data, and data for defect correction or color science. The non-volatile memory can in particular be an antifuse non-volatile memory, which may not need... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070165444 - Devices and methods of detecting movement between media and probe tip in a probe data storage system: A memory apparatus comprises a media, a tip adapted to write information to and read information from said media, a media movement mechanism attached to said media and configured to move said media in response to media control signals, and a capacitive sensor configured to detect an amount of relative... Agent: Fliesler Meyer LLP

20070165447 - Asymmetrical random access memory cell, a memory comprising asymmetrical memory cells and a method to operate such a memory: Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of... Agent: Ibm Microelectronics Intellectual Property Law

20070165445 - Eight transistor sram cell with improved stability requiring only one word line: An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a... Agent: Lynn L. Augspurger IBM Corporation

20070165446 - Seu hardened latches and memory cells using progrmmable resistance devices: Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first... Agent: Patent Law Professionals

20070165448 - Static memory cell having independent data holding voltage: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070165450 - Data retention indicator for magnetic memories: The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic element (51) and a second magnetic element (52) each having a pre-set magnetisation direction, the... Agent: Philips Intellectual Property & Standards

20070165451 - Enhanced mram reference bit programming structure: An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to focus a generated magnetic field while... Agent: Honeywell International Inc.

20070165449 - Nano-contacted magnetic memory device: A magnetic memory device includes a plurality of transistors (316, 317) formed on a substrate and a common magnetic memory block (312) including multiple effective magnetoresistive elements (318, 319), a ferromagnetic recording (321), a non-magnetic space (323), and a free magnetic reading (322) layer formed above the transistors (316, 317).... Agent: Davidson Berquist Jackson & Gowdey LLP

20070165452 - Phase change memory device and method for manufacturing phase change memory device: A composite plug 104 is formed, and both a first plug (TiN) 106 and a second plug (W) 108 are disposed in one contact hole; the first plug (TiN) 106 functions as a heater electrode and the second plug (W) 108 functions as a contact plug. This eliminates the need... Agent: Sughrue Mion, PLLC

20070165453 - Reconfigurable bit-manipulation node: A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with... Agent: Patterson & Sheridan, L.L.P.

20070165455 - Nand-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same: A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the... Agent: Myers Bigel Sibley & Sajovec

20070165454 - Nonvolatile semiconductor memory device and method of self-testing the same: A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070165456 - System and method for purge of flash memory: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by... Agent: Simpletech, Inc. C/o S. Jalal Sadr, Esq.

20070165457 - Nonvolatile memory system: A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070165458 - Random cache read using a double memory: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory... Agent: Harrity & Snyder, L.L.P.

20070165459 - Flash memory array using adjacent bit line as source: A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line... Agent: Leffert Jay & Polglaze, P.A.

20070165460 - Nonvolatile semiconductor memory device and programming or erasing method therefor: In a nonvolatile memory cell having a trap layer, by executing first charge injection with a given wait time being secured and second charge injection after the first charge injection in a programming or erasing sequence, surrounding charge that may deteriorate the data retention characteristic is reduced utilizing an initial... Agent: Mcdermott Will & Emery LLP

20070165461 - Disabling faulty flash memory dies: Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling... Agent: Fish & Richardson P.C.

20070165462 - Memory device with control circuit for regulating power supply voltage: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the... Agent: Driggs, Hogg & Fry Co. L.p.a.

20070165463 - Self timing write architecture for semiconductor memory and method for providing the same: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed... Agent: Seed Intellectual Property Law Group PLLC

20070165464 - Memory device for early stabilizing power level after deep power down mode exit: A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse... Agent: Mills & Onello LLP

20070165466 - Memory device comprising fuse memory elements: The invention relates to a memory device comprising a non-volatile memory element, a read-out circuit for reading out an item of memory information stored in the memory element, a switching unit, by means of which a supply voltage can be applied to the read-out circuit, and a control unit, which... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070165465 - Repair i/o fuse circuit of semiconductor memory device: A repair I/O fuse circuit of a semiconductor memory device includes a reduced by as much as half layout area of fuses by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse. The repair... Agent: Marshall, Gerstein & Borun LLP

20070165467 - Semiconductor integrated circuit device: There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality... Agent: Amin, Turocy & Calvin, LLP

20070165468 - Semiconductor memory device: A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein... Agent: Rader Fishman & Grauer PLLC

20070165470 - Semiconductor device generating a test voltage for a wafer burn-in test and method thereof: A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage... Agent: Harness, Dickey & Pierce, P.L.C

20070165471 - Internally asymmetric method for evaluating static memory cell dynamic stability: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070165472 - Method and apparatus for evaluating and optimizing a signaling system: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference.... Agent: Hunton & Williams LLP/rambus Inc. Intellectual Property Department

20070165469 - Test parallelism increase by tester controllable switching of chip select groups: Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070165473 - Semiconductor memory device: A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070165474 - Circuit for enabling sense amplifier and semiconductor memory device having the same: A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit... Agent: F. Chau & Associates, LLC

20070165475 - Tri-state output driver arranging method and memory device using the same: A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing... Agent: Marger Johnson & Mccollom, P.C.

20070165476 - Clock signal generating circuit: Each of identically configured logic inverter circuits 10a, 10b, 10c, and 10d comprises a PMOS transistor MP1 (abbreviated as MP1 hereinafter), and NMOS transistors MN1 and MN2 (abbreviated as MN1 and MN2 hereinafter). Gates of MP1 and MN1 are connected to input terminal IN1, gate of MN2 is connected to... Agent: Sughrue Mion, PLLC

20070165478 - Modular i/o bank architecture: A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between... Agent: Townsend And Townsend And Crew LLP/ 015114

20070165477 - Method and apparatus to adjust voltage for storage location reliability: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure... Agent: Blakely Sokoloff Taylor & Zafman

20070165479 - Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme: Embodiments of the invention generally provide a method for accessing a local wordline in a segmented memory. In one embodiment, the method includes, during an access to the local wordline, applying a first voltage to the local wordline via a local wordline driver located at a first end of the... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070165480 - Systems and methods for a controllable release of power supply in a mobile device: Systems and methods are disclosed for removing a power supply from a host unit running a computer program, without losing data or causing a cold boot. The present invention employs a retaining assembly for the power supply that delays removal of the power supply until shutting down of the computer... Agent: Amin, Turocy & Calvin, LLP

20070165481 - Method for performing a burn-in test: A DDR DRAM having a test mode and an operational mode and a method for testing the DDR DRAM. The method includes in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a bank activate command to select and bring up a wordline selected for write... Agent: Schmeiser, Olsen & Watts

20070165482 - Sequential access memory: Semiconductor memory devices 10 are each furnished with a memory array 100 having an EEPROM array 101 and a mask ROM array 102. Identifying information for identifying each semiconductor memory device 10 is stored at the beginning three addresses of the EEPROM array 101. 8-bit data relating to ink level... Agent: Stroock & Stroock & Lavan LLP

20070159867 - Memory device, memory circuit and semiconductor integrated circuit having variable resistance: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between... Agent: Mcdermott Will & Emery LLP

20070159868 - Nonvolatile memory device: A nonvolatile memory device comprises memory cells, each including a variable resistor element for storing data in accordance with a change in electrical resistance due to application of electrical stress, and a thermal diffusion barrier on a thermal diffusion path, wherein the thermal diffusion barrier is capable of suppressing a... Agent: Nixon & Vanderhye, PC

20070159869 - Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying... Agent: Marger Johnson & Mccollom, P.C.

20070159870 - Nonvolatile semiconductor memory device: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected... Agent: Mcdermott Will & Emery LLP

20070159871 - Semiconductor device with a non-erasable memory and/or a nonvolatile memory: A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby... Agent: Stanley P. Fisher Reed Smith LLP

20070159874 - Semiconductor memory device: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070159872 - Sram device and method for manufacturing the same: An SRAM device including first and second access transistor composed of an N channel MOS transistor, first and second drive transistors composed of the N channel MOS transistor, and first and second P channel thin film transistor functioning as a pull-up device, comprises: a well formed by implanting a dopant... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070159873 - Static random access memory cell: A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070159876 - Magnetic ramdom access memory and operating method of the same: A semiconductor memory device is provided with a memory array including memory cells arranged in rows and columns; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistive element storing data, and an amplifying member used to amplify a signal generated by a current through... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070159875 - Magnetoresistive random access memory and its write control method: It is made possible to prevent the recording layer in the TMR element from assuming the intermediate state as perfectly as possible even if writing into the MRAM is conducted, as heretofore described. A write control method for a magnetoresistive random access memory including: applying a pulsative first magnetic field... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070159877 - Magnetic storage device and method of manufacturing the same: In an MRAM of the invention, a curved region (206) is formed in a bit line (202), and this curved region (206) is in bent shape, with a TMR element (203) serving as a center, in this case, in rough U shape (in the illustrated example, in roughly inverted U... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070159878 - Phase change memory device: A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality... Agent: Volentine Francos, & Whitt PLLC

20070159879 - Method and system for probing fcode in problem state memory: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and... Agent: Schmeiser, Olsen & Watts

20070159880 - Secondary injection for nrom: Secondary electron injection (SEI) is used for programming NVM cells having separate charge storage areas in an ONO layer, such as NROM cells. Various combinations of low wordline voltage (Vwl), negative substrate voltabe (Vb), and shallow and deep implants facilitate the process. Second bit problems may be controlled, and retention... Agent: Empk & Shiloh, LLP

20070159882 - Protection of the flow of a program executed by an integrated circuit or of data contained in this circuit: A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070159883 - Method and related apparatus capable of improving endurance of memory: A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells,... Agent: North America Intellectual Property Corporation

20070159884 - Write-once-type recording medium, recording apparatus and method for write-once-type recording medium, and reproducing apparatus and method for write-once-type recording medium: On a write-once-type recording medium 10, there are provided: a definite defect management area 13 to definitely record therein defect management information; and a plurality of temporary defect management areas 14A, 14B, and 14C to temporarily record therein the defect management information. If the recording medium 10 is not yet... Agent: Young & Thompson

20070159885 - On-chip data grouping and alignment: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070159886 - Flash memory device including a dummy cell: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an... Agent: Volentine Francos, & Whitt PLLC

20070159887 - Method and apparatus for programming nonvolatile memory: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070159881 - Nonvolatile semiconductor memory device including nand-type flash memory and the like: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070159888 - Flash memory devices with trimmed analog voltages: A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell... Agent: Anderson, Levine & Lintel L.L.P.

20070159889 - Programming method for flash memory capable of compensating reduction of read margin between states due to hot temperature stress: A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a... Agent: Volentine Francos, & Whitt PLLC

20070159890 - Setting fail bit verification circuit with different reference fail numbers and a non-volatile semiconductor memory device including the same: A reference fail bit verification circuit includes a fail bit counter which counts a number of fail bits to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to the number of fail bits counted. The... Agent: Volentine Francos, & Whitt PLLC

20070159892 - Programming method for flash memory capable of compensating reduction of read margin between states due to high temperature stress: A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined... Agent: Volentine Francos, & Whitt PLLC

20070159891 - Trimming of analog voltages in flash memory devices: A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell... Agent: Anderson, Levine & Lintel L.L.P.

20070159893 - Method of programming and erasing multi-level flash memory: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting... Agent: J.c. Patents

20070159894 - Memory cell, read device for memory cell, memory assembly, and corresponding method: A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including... Agent: Dicke, Billig & Czaja

20070159895 - Semiconductor memory device: A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify... Agent: Morrison & Foerster LLP

20070159896 - Voltage supply circuit and semiconductor memory: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the... Agent: Arent Fox PLLC

20070159898 - Method and apparatus for increasing yield in a memory circuit: Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the first mode, the control circuitry is operative to apply a first signal to a selected... Agent: Ryan, Mason & Lewis, LLP

20070159897 - Method and apparatus for preventing permanent data loss due to single failure of a fault tolerant array: Methods and systems for preventing permanent data loss due to a single failure in an array of storage devices are described. In particular, a defective memory block is detected and data that was on the now defective memory block is reconstructed using backup data in the array. The reconstructed data... Agent: Sheridan Ross PC

20070159899 - Balanced sense amplifier circuits: Structures and methods are disclosed for operating Balanced Sense Amplifier Circuits. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode... Agent: Schmeiser, Olsen & Watts

20070159900 - Semiconductor memory device and method of testing the same: Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070159901 - Semiconductor integrated circuit device: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via... Agent: Miles & Stockbridge PC

20070159903 - Memory devices including floating body transistor capacitorless memory cells and related methods: In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the... Agent: Volentine Francos, & Whitt PLLC

20070159902 - Enhanced sensing in a hierarchical memory architecture: A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to... Agent: Ryan, Mason & Lewis, LLP

20070159904 - Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070159905 - Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refresh: A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and a second pulse width controller for... Agent: Cooper & Dunham, LLP

20070159906 - Semiconductor memory device, refresh control method thereof, and test method thereof: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other,... Agent: Arent Fox PLLC

20070159907 - Multi-chip package reducing peak power-up current: A multi-chip package is disclosed comprising a plurality of memory chips, each of the memory chips comprising an internal circuit; and a power level detector for detecting a level of a power supply voltage to initialize the internal circuit, at a power-up. The power level detectors in the respective memory... Agent: Volentine Francos, & Whitt PLLC

20070159908 - Method and system of operating mode detection: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory. The system also includes a memory to store a table. The table includes a plurality of operating voltage levels. The system... Agent: Toler Schaffer, LLP

20070159909 - Data retention in a semiconductor memory: The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be... Agent: Nixon & Vanderhye, PC

20070159910 - Command generating circuit and semiconductor memory device having the same: In a command generating circuit, operation mode signals (signals determining internal operations, such as ACTIVE, READ, WRITE, and PRECHARGE) are determined by decoding command signals /CS, /RAS, /CAS, and /WE. The operation mode signals and bank select signals (BS0, BS1, BS2, and BS3) are latched by internal clocks. Thereafter, a... Agent: Foley And Lardner LLP Suite 500

20070159911 - Semiconductor memory device and method of operating same: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the... Agent: Neil A. Steinberg

20070159912 - Integrated circuit memory device with delayed write command processing: An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070159913 - Circuit and method for generating write data mask signal in synchronous semiconductor memory device: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write... Agent: Volentine Francos, & Whitt PLLC

20070159914 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an... Agent: Miles & Stockbridge PC

20070153562 - Bit cell of organic memory: A bit cell of an organic memory is provided. The bit cell of the organic memory comprises an organic memory cell, a first transistor, a current mirror and a second transistor. To connect the organic memory cell to a data line, the first transistor is activated for reading and the... Agent: Jianq Chyun Intellectual Property Office

20070153565 - Semiconductor device and driving method of the same: The present invention provides a semiconductor device including a memory that has a memory cell array including a plurality of memory cells, a control circuit that controls the memory, and an antenna, where the memory cell array has a plurality of bit lines extending in a first direction and a... Agent: Eric Robinson

20070153564 - Storage device and semiconductor apparatus: A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state... Agent: Sonnenschein Nath & Rosenthal LLP

20070153563 - Write circuit for resistive memory: A memory includes a first resistive memory cell, a current source configured to provide an input current indicating a desired resistance level for the first memory cell, and a current mirror that mirrors the input current to provide an output current. The memory includes a first switching circuit configured to... Agent: Dicke, Billig & Czaja

20070153566 - Static random access memory cell: A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070153568 - Magnetic transistor with the and/nand/nor/or functions: A magnetic transistor circuit with the AND, NAND, NOR and OR functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070153567 - Memory structure and data writing method thereof: A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need... Agent: Mr. Robert Berliner Fulbright & Jaworski LLP

20070153570 - Phase change memory devices and multi-bit operating methods for the same: A phase change memory device includes a phase change resistor and first and second electrodes. The first and second electrodes may be connected to opposite ends of the phase change resistor, respectively. In a programming operation, the resistance of the phase change resistor is changed to at least one of... Agent: Harness, Dickey & Pierce, P.L.C

20070153571 - Phase-change memory device and its methods of formation: Phase-change memory device and methods for forming the same. The phase-change memory device comprises a first electrode and at least one phase-change material layer formed over the first electrode. The at least one phase-change material layer further comprising at least one implanted region that has higher thermal characteristics than an... Agent: Dickstein Shapiro LLP

20070153569 - Read circuit for resistive memory: A memory includes a resistive memory cell and a circuit configured to provide an output signal indicating a state of the memory cell based on a comparison of a voltage across the memory cell to a threshold voltage.... Agent: Dicke, Billig & Czaja

20070153572 - Method and device for preventing erroneous programming of a magnetoresistive memory element: The present invention provides an array of magnetoresistive memory elements comprising a magnetic field sensor unit for measuring an external magnetic field in the vicinity of the magnetoresistive memory elements, and means for temporarily disabling any programming operation when the measured external magnetic field exceeds a threshold value. A corresponding... Agent: Philips Intellectual Property & Standards

20070153573 - System for reducing read disturb for non-volatile storage: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the sourc