Static information storage and retrieval inventions 06/07

20070147101 - Memory device and method of arranging signal and power lines: A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells, a plurality of power lines to provide power to the... Agent: Marger Johnson & Mccollom, P.C.

20070147102 - Memory with resistance memory cell and evaluation circuit: A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitance has a reference memory cell with a reference resistance which is connected between the ground terminal and a reference capacitance, in which case, during the reading operation... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070147104 - Semiconductor device and manufacturing method thereof: An object of the present invention to provide a semiconductor device having a highly functional memory element with improved reliability, and to provide a technique for manufacturing such a highly reliable semiconductor device with a high yield at low cost without complicating an apparatus or a process. As a top... Agent: Eric Robinson

20070147103 - Ferroelectric memory device: A ferroelectric memory device includes: a plurality of first bit lines; a plurality of first memory cells that are connected to each of the first bit lines and store first data or second data; a plurality of first read-out voltage generation sections, each of which is connected to each of... Agent: Harness, Dickey & Pierce, P.L.C

20070147106 - Devices and methods for controlling active termination resistors in a memory system: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second... Agent: Volentine Francos, & Whitt PLLC

20070147105 - Phase change memory cell and manufacturing method: A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070147107 - Stacked memory cell for use in high-density cmos sram: A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and... Agent: Volentine Francos, & Whitt PLLC

20070147108 - Static random access memory cell: A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070147109 - Phase change memory and method for driving the same: A phase change memory comprises a first electrode formed over a substrate, a patterned phase change material layer formed over the first electrode to contact the first electrode and including a conductive material, and a second electrode formed over the patterned phase change material layer to contact the patterned phase... Agent: Mayer, Brown, Rowe & Maw LLP

20070147110 - Magnetic thin-film memory device for quick and stable reading data: An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation... Agent: Mcdermott Will & Emery LLP

20070147111 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070147113 - Alternate sensing techniques for non-volatile memories: The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070147114 - Semiconductor memory system: A semiconductor memory system includes: a non-volatile semiconductor memory device; and a memory controller configured to execute operation control of the non-volatile semiconductor memory device, wherein a sequencer contained in control logic for the non-volatile semiconductor memory device is composed of software developed in the memory controller.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147115 - Unified memory and controller: A memory device has a controller. The controller has a first address bus for receiving a RAM address signals, a first data bus for receiving RAM data signals, and a first control bus for receiving RAM control signals. The controller further has a second address bus for interfacing with a... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070147117 - Nonvolatile semiconductor memory device: In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147116 - Use of flash memory blocks outside of the main flash memory array: A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory blocks external to the array to store information in a single bit per cell mode, and... Agent: Intel Corporation C/o Intellevate, LLC

20070147120 - Page buffer and related reading method: A page buffer and a reading method comprising a unitary operation adapted to execute either a normal read operation or a copyback read operation using a page buffer are disclosed. The unitary operation comprises initializing a latch to store a first logic value; sensing a voltage level corresponding to a... Agent: Volentine Francos, & Whitt PLLC

20070147119 - Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices: A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070147118 - Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices: A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070147121 - Nonvolatile semiconductor memory device: According to a nonvolatile semiconductor memory device of the present invention, an address decode section 130 is provided in a block address decode circuit provided in a row decoder of a NAND-type flash memory device. The address decode section 130 has a selected block data storage section 132 composed of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147122 - Electrically rewritable non-volatile semiconductor memory device: A first selection transistor is connected between one end of a memory cell group and a bit line. A second selection transistor which has a gate length shorter than a gate length of the first transistor is connected between the other end of the memory cell group and a source... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147125 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147126 - Low power flash memory devices: A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070147124 - Memory capable of storing information and the method of forming and operating the same: A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of... Agent: The Maxham Firm

20070147123 - Split gate type non-volatile memory device and method of manufacturing the same: There are provided a NOR-type non-volatile memory having a split gate and a method of manufacturing the same. The split gate includes a block that protrudes above a semiconductor substrate, a first electrode formed on one side wall of the block, an inter electrode dielectric layer formed on the block... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.

20070147112 - Sense amplifier and semiconductor memory device with the same: A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147127 - Nonvolatile memory device having self reprogramming function: A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The memory cell is for data storage. The first transistor receives a reading control signal at a gate. And a first... Agent: Jianq Chyun Intellectual Property Office

20070147128 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate: A semiconductor memory device includes a memory cell array, a bit line, a precharge circuit and a first sense amplifier. The memory cell array includes memory cells. The bit line connects commonly the memory cells in the same column. The precharge circuit applies a precharge potential to the bit line... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147131 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070147130 - Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of... Agent: Jenkens & Gilchrist, PC

20070147129 - Nonvolatile memory and writing method thereof, and semiconductor device: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus,... Agent: Fish & Richardson P.C.

20070147132 - Pixel circuits including boosting capacitors, methods of driving the same, and image sensors including the same: A pixel circuit of an image sensor includes a photodiode that generates photocharges corresponding to light input to the photodiode; a transfer transistor that transfers the photocharges to a floating diffusion node in response to a transfer control signal; a reset transistor that transfers a power voltage to the floating... Agent: Harness, Dickey & Pierce, P.L.C

20070147134 - Low power nrom memory devices: A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a charge trapping dielectric layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070147133 - Nonvolatile semiconductor memory device and program method therefor: A nonvolatile semiconductor memory device and a program method are provided in an embodiment. Data is scanned to search data bits to be selectively programmed. The searched data bits are simultaneously programmed according to a predetermined number. Since data scanning and programming are conducted using a pipeline processing, an average... Agent: Marger Johnson & Mccollom, P.C.

20070147136 - Flash memory device and related erase operation: An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.... Agent: Volentine Francos, & Whitt PLLC

20070147135 - System for improving endurance and data retention in memory devices: A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memory cell. The stress on... Agent: Ishimaru & Zahrt LLP

20070147137 - Memory control circuit and memory control method: A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that... Agent: SocalIPLaw Group LLP

20070147138 - Semiconductor integrated circuit: There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147141 - High-speed writable semiconductor memory device: A memory cell array has a plurality of series connected memory cells connected to word lines and bit lines and arranged in a matrix. A select transistor selects from the word lines. A control circuit controls potentials of the word lines and bit lines in accordance with input data, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147139 - Controller for controlling a source current to a memory cell, processing system and methods for use therewith: A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state... Agent: Garlick Harrison & Markison

20070147140 - Internal voltage generation circuit: An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal... Agent: Mcdermott Will & Emery LLP

20070147142 - Write burst stop function in low power ddr sdram: A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device, when a write stop... Agent: Edell, Shapiro & Finnan, LLC

20070147143 - Integrated circuit memory device having delayed write capability: An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070147145 - Address path circuit with row redundant scheme: An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one... Agent: Marshall, Gerstein & Borun LLP

20070147144 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147146 - Semiconductor memory: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy... Agent: Arent Fox PLLC

20070147149 - Data output circuit of semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal,... Agent: Venable LLP

20070147150 - Nonvolatile memory: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories... Agent: Miles & Stockbridge PC

20070147148 - Semiconductor memory device: A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and... Agent: Mcdermott Will & Emery LLP

20070147147 - Semiconductor memory device and semiconductor integrated circuit: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a source terminal which supplies a source potential to the memory cells, a first switching element which electrically connects the source terminal and a first power supply potential in an operation mode of the memory... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070147151 - Semiconductor device: Information stored in a nonvolatile storage device mounted to a semiconductor device is read by inputting an address signal or the like and by using a sense amplifier or the like. At this time, since a prescribed period of time is required, it is necessary to design a semiconductor device... Agent: Eric Robinson

20070147152 - Sense amplifier for semiconductor memory device: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a... Agent: Stanley P. Fisher Reed Smith LLP

20070147154 - Semiconductor device: A multi-word line refresh-type semiconductor device may have a plurality of memory banks and performs a refresh operation simultaneously with respect to a plurality of word lines for each of the banks in a self-refresh mode. The semiconductor device includes an address controller for receiving a normal address and a... Agent: Marshall, Gerstein & Borun LLP

20070147153 - Gate induced drain leakage current reduction by voltage regulation of master wordline: A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage... Agent: Edell, Shapiro & Finnan, LLC

20070147155 - Memory device having a configurable oscillator for refresh operation: A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070147157 - Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages: A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts.... Agent: Stuart T Auvinen

20070147156 - Methods and apparatus for random number generation: Methods and apparatus provide for powering up a static random access memory (SRAM); interrogating at least some contents of the SRAM resulting from power up; and using the contents as at least a basis of a random number... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070147159 - Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit: Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor memory device comprising memory cells. The circuit comprises a bias signal generator adapted... Agent: Volentine Francos, & Whitt PLLC

20070147158 - Memory with spatially encoded data storage: Disclosed herein are memory circuit embodiments to have spatially encoded data.... Agent: Intel Corporation C/o Intellevate, LLC

20070147160 - Semiconductor device: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read... Agent: Miles & Stockbridge PC

20070147161 - Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region: A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring for signals to be transmitted from decoding drivers to a... Agent: Mills & Onello LLP

20070147162 - Multi-port semiconductor memory device having variable access paths and method therefor: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and... Agent: Marger Johnson & Mccollom, P.C.

20070147163 - Address decoder, storage device, processor device, and address decoding method for the storage device: The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which performs a logical AND operation between an output signal of said decode unit, which has been inverted by said... Agent: Staas & Halsey LLP

20070147165 - Memory unit and semiconductor device: A memory unit that is capable of operating in a desired operation condition with less power consumption, and a semiconductor device using the memory unit. The memory circuit comprises a cell array in which a plurality of memory cells is arranged, a driver circuit, a plurality of selection circuits each... Agent: Fish & Richardson P.C.

20070147164 - Row decoder for preventing leakage current and semiconductor memory device including the same: A row decoder preventing leakage current and a semiconductor memory device including the same are provided. The row decoder includes an address decoder and a selection signal generator. The address decoder decodes a predetermined address signal and activates an enable signal. The selection signal generator electrically connects a boosted voltage... Agent: Mills & Onello LLP

20070147166 - Apparatus and method of generating output enable signal for semiconductor memory apparatus: A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop).clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable signal... Agent: Venable LLP

20070147167 - Synchronous semiconductor memory device: Provided is a synchronous semiconductor memory device with improved latency control. In one embodiment, the synchronous semiconductor memory device may include a clock synchronizing circuit, a latency circuit, and a latency control circuit. The clock synchronizing circuit may receive an external clock signal and output a data output clock signal.... Agent: Marger Johnson & Mccollom, P.C.

20070147168 - Methods for writing non-volatile memories for increased endurance: A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070139987 - Storage element and storage apparatus: A storage element and storage apparatus are provided. A storage element includes a storage layer disposed between two electrodes, and an ion source layer provided in contact with the storage layer and containing any element selected from the group consisting of Cu, Ag, and Zn, wherein the material of the... Agent: Bell, Boyd & Lloyd, LLP

20070139988 - Detector of noise peaks in the power supply of an integrated circuit: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070139989 - Tamper-resistant packaging and approach using magnetically-set data: A tamper-resistant packaging approach protects an integrated circuit (100) from undesirable access. According to an example embodiment of the present invention, data is encrypted as a function of the state of a plurality of magnetically-responsive circuit elements (130-135) and then decrypted as a function of the state (130-135). A package... Agent: Philips Electronics North America Corporation Intellectual Property & Standards

20070139991 - Cache hit logic of cache memory and processor chip having the same: A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison... Agent: Mills & Onello LLP

20070139990 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells each have... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070139992 - Semiconductor memory device: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and... Agent: Mcdermott Will & Emery LLP

20070139993 - Ferroelectric memory device, electronic apparatus, and ferroelectric memory device driving method: A ferroelectric memory device including: a plurality of bit lines; a plurality of memory cells, which are connected to the bit lines, and which store prescribed data; and a sense amplifier, which is connected to a bit line, wherein the sense amplifier includes an op amp, a MOS transistor, and... Agent: Harness, Dickey & Pierce, P.L.C

20070139994 - Multi-level dynamic memory device having open bit line structure and method of driving the same: A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the... Agent: Mills & Onello LLP

20070139995 - Semiconductor memory device: A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070139998 - Radiation tolerant sram bit: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter.... Agent: Sierra Patent Group, Ltd.

20070139997 - Semiconductor memory: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to... Agent: Mcdermott Will & Emery LLP

20070139996 - Semiconductor memory and method for controlling semiconductor memory: A semiconductor memory maintains securely the stored contents in the memory cells, and it is written with data reliably even in a case where a relatively low supply voltage is applied. A memory cell M00 comprises a pair of inverters cross-coupled with each other, a first switching unit provided between... Agent: Arent Fox PLLC

20070139999 - Magnetic memory device: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ... Agent: Mcdermott Will & Emery LLP

20070140000 - Magnetic storage cell: Disclosed herein are different embodiments of a magnetic memory cell. This magnetic memory cell includes at least two conductive lines to carry current and a magnetic element disposed between the conductive lines. The current through the conductive lines induces a magnetic field. The design is such that the magnetic element... Agent: James E. Eakin

20070140001 - Nonvolatile storage device and method of manufacturing the same, and storage device and method of manufacturing the same: A nonvolatile storage device includes a plurality of bit lines 21 arranged in a column direction on a substrate; a plurality of word lines 35 arranged in a row direction on the substrate; a memory cell array 20 having a plurality of memory cells 31, where a store state of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070140002 - Use of recovery transistors during write operations to prevent disturbance of unselected cells: A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which is coupled to a unique array bitline. A... Agent: Schneck & Schneck

20070140006 - Compensating for coupling in non-volatile storage: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation

20070140005 - Multi-level dynamic memory device: A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that... Agent: Mills & Onello LLP

20070140007 - Flash memory, memory control circuit, microcomputer and memory control method: A flash memory includes a data area in which first and second k-bit data (k is a natural number) are stored; and an additional data area in which a first additional m-bit data (m is a natural number) and a second additional m-bit data used to respectively identify the first... Agent: Foley And Lardner LLP Suite 500

20070140008 - Independently programmable memory segments within an nmos electrically erasable programmable read only memory array achieved by p-well separation and method therefor: An array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.... Agent: Paul N. Katz Baker Botts L.L.P.

20070140009 - Virtual ground type nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a ground voltage applying circuit for applying a ground voltage to a selected source line connected to a source of a selected memory cell, a reading circuit for supplying a reading current to the selected memory cell via a selected bit line and detecting... Agent: Morrison & Foerster LLP

20070140010 - Method and apparatus for operating a string of charge trapping memory cells: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070140012 - Nand architecture memory devices and operation: Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of... Agent: Leffert Jay & Polglaze, P.A.

20070140013 - Program method of non-volatile memory device: A program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively. The program voltage is varied according to an arrangement of the selected word line.... Agent: Marger Johnson & Mccollom, P.C.

20070140011 - Reading non-volatile storage with efficient setup: A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the... Agent: Vierra Magen/sandisk Corporation

20070140003 - Nonvolative semiconductor memory device and operating method thereof: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells for a user area and a trimming data storage area; and a plurality of word lines. A first trimming data is stored in the trimming data storage area, and is for adjusting a read voltage to be applied... Agent: Foley And Lardner LLP Suite 500

20070140004 - Sensing scheme for low-voltage flash memory: Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their operation include precharging an input node of a single-ended sensing device to a precharge potential while the input node is coupled to a source/drain region of... Agent: Leffert Jay & Polglaze, P.A.

20070140014 - Lcd driver integrated circuit having double column structure: A driver integrated circuit (IC) for a liquid crystal display (LCD) has a double column structure. The driver IC includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores first and... Agent: Myers Bigel Sibley & Sajovec

20070140015 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a memory cell formed in a first well outputs a first voltage in response to a reference voltage necessary for program and erase verify operations. A reference cell formed in a second well generates a second voltage in response... Agent: F. Chau & Associates, LLC

20070140016 - System for reading non-volatile storage with efficient setup: A process for reading data (including verifying during programming) from a selected non-volatile storage elements of a group (e.g., NAND string) of non-volatile storage elements includes maintaining an intermediate voltage as a control gate voltage for an unselected non-volatile storage element and subsequently changing the control gate voltage for the... Agent: Vierra Magen/sandisk Corporation

20070140017 - Nonvolatile semiconductor memory device: There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the... Agent: Harness, Dickey & Pierce, P.L.C

20070140018 - Semiconductor memory device: A semiconductor memory device has a driver including a first resistor, and a control signal generator including a second resistor. A storage unit is employed to store adjustment data for setting a resistance of said second resistor at a designed resistance, which is specified based on the state of the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070140019 - Method and apparatus for operating a string of charge trapping memory cells: An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070140020 - Parallel data storage system: A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A... Agent: Mcdermott Will & Emery LLP

20070140021 - Semiconductor integrated circuit and data output method: A semiconductor integrated circuit for reducing power consumption and simultaneous switching noise in an output circuit, which outputs plural pieces of output data including first and second output data, each including a plurality of bits. The first output data is generated from first original data. The second output data is... Agent: Staas & Halsey LLP

20070140022 - System and method for enhanced mode register definitions: Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with data selecting one option of a set of options for the operating mode. A second register is programmed with... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070140023 - Integrated dynamic random access memory chip: An integrated dynamic random access memory chip is provided, the memory chip comprising a plurality of volatile memory cells for storing user data and a plurality of non-volatile rewritable memory cells for storing at least one of repair data, trimming data, sorting data and identification data.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070140025 - Method and apparatus for testing a fully buffered memory module: Described embodiments relate to a method of testing fully buffered memory modules that involves placing a buffer device, a test vectors generator, and a switch into a memory device tester, coupling the buffer device and the test vectors generator to the switch inside the tester, coupling the switch to an... Agent: Bell, Boyd & Lloyd, LLP

20070140024 - Random access memory including circuit to compress comparison results: A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070140026 - Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected... Agent: Mills & Onello LLP

20070140027 - Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected... Agent: Mills & Onello LLP

20070140028 - Input buffer for low voltage operation: Some embodiments of the invention include an input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070140029 - Resistive memory devices including selected reference memory cells: A Resistance based Random Access Memory (ReRAM) can include a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits.... Agent: Myers Bigel Sibley & Sajovec

20070140030 - Apparatus and method for thermal management of a memory device: A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then... Agent: Intel Corporation C/o Intellevate, LLC

20070140031 - Semiconductor memory device: A semiconductor memory device is provided for minutely changing a refresh interval according to a detected temperature and thereby lowering its power consumption. A temperature detector detects a temperature of a chip and outputs the corresponding temperature signal. A reference temperature signal output unit outputs the corresponding reference temperature signal... Agent: Arent Fox PLLC

20070140032 - Sensing current recycling method during self-refresh: A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line sensing of a selected wordline and deactivation of the selected wordline, a capacitor is connected to a source node associated with a bit line sensing amplifier... Agent: Edell, Shapiro & Finnan, LLC

20070140033 - Configurable mram and method of configuration: A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the memory cells that can be... Agent: George O. Saile

20070140034 - Semiconductor apparatus, semiconductor storage apparatus, control signal generation method, and replacing method: A semiconductor apparatus according to the present invention includes a plurality of electric fuses that can be disconnected electrically, a selection circuit selecting the plurality of electric fuses in response to a selection signal, a disconnection circuit disconnecting the selected plurality of electric fuses by passing a current, and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070140035 - Apparatus and method for pipelined memory operations: A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20070140036 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070140037 - Line driver circuit and method with standby mode of operation: A line driver circuit can include an integrated circuit substrate of a first conductivity type having at least a first and a second well of a second conductivity type formed therein. The second well can be coupled to a first power supply node. A first transistor can be formed in... Agent: Haverstock & Owens, LLP

20070140039 - Nonvolatile semiconductor memory: When different word lines are accessed sequentially, to perform access operations in parallel, a word decoder overlaps a part of activation periods of those word lines. That is, a nonvolatile semiconductor memory is capable of pipeline processing for performing access operations in parallel. All the combinations of bit lines and... Agent: Arent Fox PLLC

20070140038 - Selectable memory word line deactivation: Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to be deactivated simultaneously, which can cause voltage at a common deactivate node to rise undesirably. This undesirable voltage rise can adversely affect a system... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070140040 - Memory module: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load... Agent: Sughrue Mion, PLLC

20070133243 - A content addressable memory including capacitor memory cell: A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line. The plate of... Agent: Juhan Kim

20070133244 - A content addressable memory including capacitor memory cell: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments... Agent: Dennis R. Haszko Patent Law Office Of D.r.haszko

20070133247 - Memory system having point-to-point (ptp) and point-to-two-point (pttp) links between devices: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary... Agent: Mills & Onello LLP

20070133246 - Semiconductor memory apparatus: A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address... Agent: Young & Thompson

20070133245 - Spice optimized for arrays: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array... Agent: Bever, Hoffman & Harms, LLP

20070133248 - Diode-less array for one-time programmable memory: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070133249 - Single level cell programming in a multiple level cell non-volatile memory device: A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20070133250 - Phase change memory including diode access device: Phase change memory including diode access device is realized, wherein includes a chalcogenide storage element and a diode access device instead of MOS device, the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to one side of the storage element,... Agent: Juhan Kim

20070133251 - Magnetic random access memory (mram) having increased reference layer anisotropy through ion beam etch of magnetic layers: A Magnetic Random Access Memory (MRAM) cell and array for storing data. The MRAM array includes a memory cell having a magnetic pinned layer, a magnetic free layer and a non-magnetic spacer or barrier layer sandwiched between the pinned and free layer. The pinned layer has magnetization that is pinned,... Agent: Zilka-kotab, PC

20070133252 - Ferroelectric memory device: A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for... Agent: Harness, Dickey & Pierce, P.L.C

20070133253 - Test mode control device using nonvolatile ferroelectric memory: A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data... Agent: Heller Ehrman LLP

20070133254 - Test mode control device using nonvolatile ferroelectric memory: A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data... Agent: Heller Ehrman LLP

20070133256 - Integrated circuit with a memory of reduced consumption: An integrated circuit -comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power... Agent: Plevy & Howard & Darcy P.C.

20070133255 - Method and apparatus processing variable resistance memory cell write operation: A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As the switchable current blocking device blocks current flow through the variable resistance memory cell, the charge storing element charges.... Agent: Dickstein Shapiro LLP

20070133257 - Diode-based capacitor memory and its applications: Diode-based capacitor memory uses relatively small capacitor, and uses a diode as an access device instead of MOS transistor, wherein the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to the first plate of capacitor which serves as a storage... Agent: Juhan Kim

20070133258 - Diode-based memory including floating-plate capacitor and its applications: Floating plate memory includes a diode as an access device, wherein the diode has four terminals, the first terminal serves as a word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; a floating plate capacitor... Agent: Juhan Kim

20070133259 - One-time programmable memory: In the present invention, one-time programmable memory includes a diode as an access device and a capacitor as a storage device, the diode includes four terminals, wherein the first terminal is connected to a word line, the second terminal is connected to one plate of the capacitor, the third terminal... Agent: Juhan Kim

20070133260 - Semiconductor memory device with memory cells operated by boosted voltage: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than... Agent: Miles & Stockbridge PC

20070133261 - Semiconductor storage device: A semiconductor storage device such as a memory cell, a latch, etc. provides a memory cell or other such memory device that has a high immunity to soft errors. The device includes an inverter composed of a paired N-type transistors and a paired P-type transistor, and each of transistor is... Agent: Arent Fox PLLC

20070133263 - Magnetic memory: A magnetic memory 1 having a wire 5 extended in a direction of arbitrary decision, an electro-resistivity effect element 4 disposed adjacently to the wire 5, and a counter element side yoke 20B disposed adjacently on the side opposite the magneto-resistivity effect element 4 in the wire 5 and having... Agent: Mathews, Shepherd, Mckay, & Bruneau, P.A.

20070133262 - Mram with a write driver and method therefor: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell.... Agent: Freescale Semiconductor, Inc. Law Department

20070133265 - Semiconductor integrated circuit device with a plurality of memory cells storing data: A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing... Agent: Mcdermott Will & Emery LLP

20070133264 - Storage element and memory: A storage element includes a storage layer for holding information by use of a magnetization state of a magnetic material, with a pinned magnetization layer provided on one side of the storage layer, with an intermediate layer, to form a laminate film, and with the direction of magnetization of the... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070133266 - Memory devices using carbon nanotube (cnt) technologies: Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and... Agent: Schmeiser, Olsen & Watts

20070133269 - Non-volatile memory devices and systems including phase-change one-time-programmable (otp) memory cells and related methods: In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory... Agent: Volentine Francos, & Whitt PLLC

20070133268 - Phase change memory device and memory cell array thereof: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local... Agent: Volentine Francos, & Whitt PLLC

20070133267 - Phase change memory device and method of programming the same: A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls... Agent: Volentine Francos, & Whitt PLLC

20070133272 - Phase change memory device having semiconductor laser unit: Provided is a phase change memory device including: a phase change memory unit comprising a phase change layer pattern; a laser beam focusing unit locally focusing a laser beam on the phase change layer pattern of the phase change memory unit; and a semiconductor laser unit generating and emitting the... Agent: Ladas & Parry LLP

20070133270 - Phase-change random access memory device and method of operating the same: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second... Agent: Lee & Morse, P.C.

20070133271 - Phase-changeable memory device and read method thereof: Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The... Agent: Volentine Francos, & Whitt PLLC

20070133273 - Gated diode nonvolatile memory cell: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070133274 - Gated diode nonvolatile memory cell array: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070133277 - Non-volatile semiconductor memory device: A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values... Agent: Mcdermott Will & Emery LLP

20070133276 - Operating array cells with matched reference cells: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to... Agent: Eitan Law Group C/o Landonip, Inc.

20070133279 - Reducing the effects of noise in non-volatile memories through multiple roads: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070133280 - Semiconductor integrated circuit apparatus and electronic system: A flash memory is provided with a protect area PA in which reading of a specific block is prohibited. A RAM to be used as a work area of a program is provided with a protect area PA1 in which reading of a specific block is prohibited. A bus state... Agent: Miles & Stockbridge PC

20070133281 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070133282 - Nonvolatile semiconductor memory: A memory cell array has a unit formed from one memory cell and two select transistor sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one gate. A sense amplifier having a latch function is connected to a bit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070133283 - Nonvolatile semiconductor memory: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20070133284 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070133285 - Flash memory device with sector access: A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be... Agent: Marger Johnson & Mccollom, P.C.

20070133289 - Nand-type flash memory device with high voltage pmos and embedded poly and methods of fabricating the same: The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple... Agent: Stephen B. Ackerman

20070133286 - Nonvolatile memory and method of program inhibition: A memory circuit and a method is provided for programming a dual-gate memory cell without program disturb in other dual-gate memory cells in the memory circuit coupled by common word lines. In one embodiment, the method uses a self-boosting technique on unselected memory cells having source and drain regions in... Agent: Macpherson Kwok Chen & Heid LLP

20070133291 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070133288 - Nonvolatile semiconductor memory, method for reading out thereof, and memory card: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070133290 - Semiconductor memory device equipped with storage section for storing setting information to set initial operation and function: A device includes first and second memory cell arrays, first and second decoders, first and second sense amplifiers, and first and second switch circuits. The first switch circuit switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, and switches the supply... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070133287 - Threshold value read method of nonvolatile semiconductor memory device and nonvolatile semiconductor memory device: A threshold voltage read method of a nonvolatile semiconductor memory device is disclosed. The threshold voltage read method applies a first threshold voltage measuring read voltage to the word line with a selection gate kept in a nonconductive state and then makes the selection gate conductive to read out a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070133294 - Flash memory programming to reduce program disturb: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that... Agent: Leffert Jay & Polglaze, P.A.

20070133292 - Method for operating gated diode nonvolatile memory cell: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070133293 - Non-volatile memory device with a programming current control scheme: A non-volatile memory device includes at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a programming current on the bit line when one of the memory cells is selected for programming operation. At... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070133275 - Low-power reading reference circuit for split-gate flash memory: A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating... Agent: Morris Manning Martin LLP

20070133295 - Reducing read disturb for non-volatile storage: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of... Agent: Vierra Magen/sandisk Corporation

20070133296 - Methods for operating a nonvolatile memory and related circuit: A method for operating a nonvolatile memory and related circuit are applied to a nonvolatile memory of an RFID tag. The operating method is for repeatedly performing a program procedure on the nonvolatile memory at least twice, and then performing an verification procedure on the nonvolatile memory.... Agent: Bacon & Thomas, PLLC

20070133297 - Non-volatile memory read operations using compensation currents: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and... Agent: Vierra Magen/sandisk Corporation

20070133298 - Time-dependent compensation currents in non-volatile memory read operations: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and... Agent: Vierra Magen/sandisk Corporation

20070133302 - Electrically writable non-volatile memory: A memory cell array circuit of a non-volatile memory selects the drain electrodes of the memory cells, interconnected to word lines and bit lines, by two drain selectors, adapted for selecting the drain electrodes in two selection routes, so that the memory cell array circuit will select the drain electrodes... Agent: Nixon Peabody, LLP

20070133300 - High voltage switching circuit: A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and an, enhancement mode NMOS transistor. A control circuit generates first and second control signals. A first control signal controls the enhancement mode NMOS transistor and a logical combination of both control signals... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070133301 - Low-voltage single-layer polysilicon eeprom memory cell: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A... Agent: Schneck & Schneck

20070133299 - Non-volatile memory storage device and controller therefor: A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory... Agent: Rosenberg, Klein & Lee

20070133303 - Nonvolatile semiconductor memory: Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value,- a voltage adjusting circuit outputs adjusting signals... Agent: Arent Fox PLLC

20070133304 - Method and apparatus for determining sensing timing of flash memory: A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform... Agent: John S. Egbert Egbert Law Offices

20070133305 - Method of erasing data with improving reliability in a nonvolatile semiconductor memory device: A method of erasing data in a nonvolatile semiconductor memory device including applying an erase voltage to a substrate of the semiconductor memory device, applying a ground voltage to wordlines of a selected memory cell string formed in the substrate, and applying a control voltage to at least one of... Agent: Marger Johnson & Mccollom, P.C.

20070133306 - Erasing method for non-volatile memory: An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the... Agent: Jianq Chyun Intellectual Property Office

20070133307 - Methods to resolve hard-to-erase condition in charge trapping non-volatile memory: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070133278 - Data processing system and nonvolatile memory: Erasing is performed with respect to a nonvolatile memory cell with