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Static information storage and retrieval May archived listing by USPTO class 05/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/31/2007 > patent applications in patent subcategories. archived listing by USPTO class
20070121358 - Semiconductor integrated circuit: This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field... Agent: GlobalIPCounselors, LLP
20070121359 - Semiconductor memory device with mos transistors each having floating gate and control gate: A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating regions which have stripe shapes along the bit lines. The memory... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070121360 - Apparatus and method of generating dbi signal in semiconductor memory apparatus: An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal... Agent: Venable LLP
20070121361 - Semiconductor memory device, electronic card and electronic device: A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a... Agent: Hogan & Hartson L.L.P.
20070121362 - Memory array using mechanical switch, method for controlling the same, display apparatus using mechanical switch, and method for controlling the same: Provided are a memory array using a mechanical switch, a method for controlling the same, a display apparatus using a mechanical switch, and a method for controlling the same. The memory array comprises a plurality of word lines, a plurality of bit lines intersecting each other with the plurality of... Agent: Foley And Lardner LLP Suite 500
20070121364 - One-time programmable, non-volatile field effect devices and methods of making same: One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each of the source, drain, and gate has a corresponding terminal. An electromechanically-deflectable, nanotube switching... Agent: Wilmer Cutler Pickering Hale And Dorr LLP
20070121363 - Phase change memory cell and manufacturing method: A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070121366 - Data carrier system and data saving/restoring method thereof: A data carrier system includes: a first memory, which is a ferroelectric memory; a second memory; a polarization canceling circuit for canceling polarization of the first memory in accordance with an instruction given thereto; and a control circuit for making data access to the first and second memories and controlling... Agent: Mcdermott Will & Emery LLP
20070121367 - Ferroelectric random access memory device and method of driving the same: A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced... Agent: Volentine Francos, & Whitt PLLC
20070121365 - Memory: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and... Agent: Mcdermott Will & Emery LLP
20070121368 - Programmable memory device circuit: Circuits for writing, reading, and erasing a programmable metallization cell are disclosed. The programming circuits compensate for parasitic capacitance and/or parasitic resistance. The parasitic resistance and/or capacitance is compensated for using a feedback loop or a time current filter. Various circuits also measure a switching speed of the programmable metallization... Agent: Snell & Wilmer L.L.P. (main)
20070121369 - Resistive memory cell arrangement and a semiconductor memory including the same: A memory cell arrangement includes a set of word lines and bit lines and at least one chain of series-connected memory elements which is electrically connected to one of the bit lines. The memory elements each include a resistive memory cell, which can be switched between a low-resistance ON state... Agent: Edell, Shapiro & Finnan, LLC
20070121371 - Compact static memory cell with non-volatile storage capability: A static random access memory (SRAM) cell includes a SRAM circuit and a programmable resistor connected to a storage node of the SRAM circuit. The SRAM circuit can be any type of SRAM circuit, such as a 3T, negative differential resistance (NDR) transistor-based circuit, or a 6T (conventional SRAM) circuit.... Agent: Bever, Hoffman & Harms, LLP
20070121372 - Semiconductor memory device and method for operating the same: A semiconductor memory device is provided, which comprises an analog switch, a first inverter, a second inverter, and a clocked inverter. A first terminal of the analog switch is electrically connected to a first data line. A second terminal of the analog switch is electrically connected to an input terminal... Agent: Fish & Richardson P.C.
20070121370 - Sram voltage control for improved operational margins: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the... Agent: International Business Machines Corporation Dept. 18g
20070121373 - Magnetic memory: The magnetic fields generated by the electric current flowing through the respective lines are pulled into a magnetic yoke whereby the magnetic fields are concentrated on a magnetoresistive element including the magnetosensitive layer. Namely, the opposite magnetic fields are brought close to each other in the magnetosensitive layer in reading... Agent: Oliff & Berridge, PLC
20070121374 - Phase change memory device and manufacturing method: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase change bridge has a length, a width and a thickness. The... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070121375 - System and method for forming nanodisks used in imprint lithography and nanodisk and memory disk formed thereby: A system and method form a nanodisk that can be used to form isolated data bits on a memory disk. The imprint stamp is formed from first and second overlapping patterns, where the patterns are selectively etched. The selective etching leaves either pits or posts on the imprint stamp. The... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.
20070121377 - Semiconductor device: A semiconductor storage device in which a read sense circuit stable for the fluctuation in manufacturing process and environmental conditions can be realized and the read access time can be shortened is provided. A sense circuit for reading a memory cell characterized in that a flowing current is varied depending... Agent: Stanley P. Fisher Reed Smith LLP
20070121378 - Semiconductor memory device: In a memory cell array, a plurality of memory cells which store data in the form of n values (n is a natural number which is not smaller than 2) which are in first and second to nth states are arranged in a matrix form. Before a write operation of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070121379 - Electrically writable nonvolatile memory: A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to... Agent: Nixon Peabody, LLP
20070121380 - Location-specific nand (ls nand) memory technology and cells: The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as... Agent: Mammen Thomas
20070121381 - Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for a general-purpose cmos technology with thick gate oxide: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The... Agent: Fliesler Meyer LLP
20070121383 - Behavior based programming of non-volatile memory: The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which... Agent: Vierra Magen/sandisk Corporation
20070121382 - Circuit to control voltage ramp rate: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a... Agent: Schneck & Schneck
20070121376 - Semiconductor memory device and data write method thereof: A semiconductor memory device including a memory cell array and a sense amplifier, wherein the memory cell array includes: a plurality of information cells, in each of which either one of multi-level data is written; a first reference cell with the same structure and the same connection state as the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070121384 - Method and apparatus for implementing walkout of device junctions: A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output... Agent: Sierra Patent Group, Ltd.
20070121385 - Pattern layout of world line transfer transistors in nand flash memory which executes subblock erase: A semiconductor device includes a memory cell array, first word lines, second word lines and interconnection switching region. The memory cell array includes electrically rewritable nonvolatile memory cells. Each first word line is connected in common to memory cells of a corresponding row. Second word lines correspond to the respective... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070121386 - Multi-level-cell programming methods of non-volatile memories: The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070121388 - Flash memory device and method for controlling erase operation of the same: A non-volatile memory device includes first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines. A block selection unit connects given local word lines to global word line, respectively, in response... Agent: Townsend And Townsend And Crew, LLP
20070121387 - Method and apparatus for programming/erasing a non-volatile memory: An integrated circuit (10) having non-volatile memory (NVM) (14) includes a threshold selector (28) which selects a first one of a plurality of read current/voltage thresholds during a first portion of a program/erase cycle, and which selects a second one of a plurality of read current/voltage thresholds during a second... Agent: Freescale Semiconductor, Inc. Law Department
20070121389 - Memory interface to bridge memory buses: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface... Agent: Ivy Y. Mei
20070121391 - Magnetoresistive random access memory array: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070121390 - Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same: The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that is common with other transistors, a method for characterizing the leakage current of at least one of a plurality of functionally separate transistors located in a... Agent: Texas Instruments Incorporated
20070121392 - Nonvolatile semiconductor memory device and its writing method: There is provided a nonvolatile semiconductor memory device and its writing method capable of controlling an increase in threshold voltage due to effects of adjacent memory cells and performing stable readout operations even if miniaturization of semiconductor memory devices proceeds further. The device comprises a memory cell array 411 having... Agent: Morrison & Foerster LLP
20070121393 - Semiconductor memory circuit, circuit arrangement and method for reading out data: A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO... Agent: Maginot, Moore & Beck Chase Tower
20070121394 - Semiconductor memory device: Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock... Agent: Mcdermott Will & Emery LLP
20070121395 - Device and method of controlling source driver: A source driver control device and method. The source driver control device includes a memory, a first write controller, a second write controller and a write clock signal generator. The memory receives display data corresponding to an image and stores the display data in response to a write clock signal.... Agent: Frank Chau, Esq. F. Chau & Associates, LLC
20070121396 - Semiconductor memory device and method for operating a semiconductor memory device: A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundancy information, and a redundancy control unit (RU) for selecting... Agent: Slater & Matsil LLP
20070121397 - Output circuit, semiconductor memory device having the same, and method of expanding a valid output data window: A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the, read data sequentially in... Agent: Mills & Onello LLP
20070121398 - Memory controller capable of handling precharge-to-precharge restrictions: A memory controller capable of handling precharge-to-precharge restrictions is disclosed. Upon commencement of a write operation, the location of the corresponding write precharge command is tracked from a timing standpoint. A determination is then made as to whether or not a subsequent read precharge command will collide with any pending... Agent: Dillon & Yudell LLP
20070121401 - Precharge apparatus: A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, a precharge voltage to be applied to each of the precharge... Agent: Venable LLP
20070121402 - Semiconductor device and operating method thereof: An object is to provide a semiconductor device capable of reducing an area of the semiconductor device, reading data reliably, and simplifying replacement of data. A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device. In... Agent: Eric Robinson
20070121399 - Semiconductor memory devices and systems, and methods of using having reduced timers and registers: A device including a command decoder to receive a compound command, a timer to begin operating if the compound command includes an activate command and a precharge command, the timer to begin operating at substantially the same time as the activate command is issued, and control logic coupled to the... Agent: Marger Johnson & Mccollom, P.C.
20070121400 - Supplying voltage to a bit line of a memory device: A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070121403 - Apparatus and method for controlling operation of data buses of memory device: Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section... Agent: Ladas & Parry LLP
20070121404 - Temperature sensing circuit, voltage generation circuit, and semiconductor storage device: A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20070121405 - Semiconductor memory device: There is provided a semiconductor memory device for acceleration in burst mode. The semiconductor memory device has a burst mode for serially reading multiple bits of data in synchronization with both edges of a clock. Multiple memory blocks are geometrically arranged correspondingly to the multiple bits. An address selection circuit... Agent: Miles & Stockbridge PC
20070121409 - Method and system for providing independent bank refresh for volatile memories: A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank... Agent: Qualcomm Incorporated
20070121407 - Self-refresh period measurement circuit of semiconductor device: A self-refresh period measurement circuit of a semiconductor device is disclosed, herein which includes a shift register configured to receive an oscillation signal that is periodically enabled after a self-refresh signal is enabled, to allow a self-refresh operation to be performed, and delay the received oscillation signal by a unit... Agent: Cooper & Dunham, LLP
20070121406 - Semiconductor integrated circuit having low power consumption with self-refresh: A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for low power consumption. The logically identical circuits can... Agent: Borden Ladner Gervais LLP
20070121410 - Semiconductor memory: After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in response to an access request, the word control circuit unselects only a word line selection signal line of a... Agent: Arent Fox PLLC
20070121408 - Stable temperature adjustment for referesh control: A refresh control circuit and method generates a refresh signal in response to one of a plurality of clock signals and a temperature signal. The clock signals and temperature signal may be synchronized to prevent an incomplete refresh operation at a trip point of a temperature sensor. In one embodiment,... Agent: Marger Johnson & Mccollom, P.C.
20070121411 - Efuse programming data alignment verification apparatus and method: An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.
20070121412 - Uni-stage delay speculative address decoder: An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n−1 inputs, the n−1 inputs being a subset of n inputs conveyed to each decoder circuit. Each decoder circuit further includes a second stage having... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)
20070121413 - Apparatus and method of controlling bank of semiconductor memory: An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control... Agent: Venable LLP
20070121414 - Shielded bitline architecture for dynamic random access memory (dram) arrays: A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.... Agent: Hogan & Hartson LLP
20070121416 - Memory array decoder: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein... Agent: Jones Day
20070121417 - Memory array decoder: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein... Agent: Jones Day
20070121415 - Pseudo-dynamic word-line driver: In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device,... Agent: Mendelsohn And Associates, P.C.
20070121418 - Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the... Agent: Marger Johnson & Mccollom, P.C.
20070121419 - Alignment of memory read data and clocking: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows... Agent: Fish & NeaveIPGroup Ropes & Gray LLP
20070121420 - Page access circuit of semiconductor memory device: A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit configured to control the page address... Agent: Heller Ehrman LLP05/24/2007 > patent applications in patent subcategories. archived listing by USPTO class
20070115708 - Alterable dc power supply circuit: An alterable DC power supply circuit includes a regulator, a resistor, and an adjustable load resistance. The regulator includes a voltage input pin, a voltage output pin, and an adjusting pin. The resistor is coupled between the voltage output pin and the adjusting pin. The adjustable load resistance is coupled... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp
20070115712 - Apparatus and method for mounting microelectronic devices on a mirrored board assembly: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a... Agent: Michael G. Pate, Esq. Dorsey & Whitney LLP
20070115711 - Device and method for using dynamic cell plate sensing in a dram memory cell: A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and... Agent: Trask Britt, P.C./ Micron Technology
20070115709 - Host computer memory configuration data remote access method and system: A host computer memory configuration data remote access method and system is proposed, which is designed for use with a client station and a host computer for the purpose of allowing a user at the client station to learn the current memory configuration of the host computer via the client... Agent: Fulbright And Jaworski LLP
20070115710 - Semiconductor memory device with hierarchical bit line structure: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the... Agent: Volentine Francos, & Whitt PLLC
20070115713 - Non-volatile electromechanical configuration bit array: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.... Agent: Stephen L. King
20070115714 - Method for initializing resistance-variable material, memory device containing a resistance-variable material, and method for initializing nonvolatile memory circuit including variable resistor: An initialization method of the present invention is a method for initializing a material (variable-resistance material) (2) whose resistance value increases/decreases according to the polarity of an applied electric pulse. An electric pulse having a first polarity is applied at least once between first and second electrodes (1, 3) connected... Agent: Mcdermott Will & Emery LLP
20070115715 - Magnetic access memory device using perpendicular magnetization and fabrication method thereof: Provided are a magnetic random access memory (MRAM) device using perpendicular magnetization, capable of stably reducing a size of a magnetic domain, and a method of fabricating the magnetic random access memory device. The magnetic random access memory device includes at least two magnetic layers, a tunnel insulation layer, and... Agent: Ladas & Parry LLP
20070115716 - Spin-injection fet: An spin-injection FET according to an embodiment of the invention includes a first ferromagnetic body whose magnetization direction is fixed, a second ferromagnetic body whose magnetization direction is changed by spin-injection current, a gate electrode which is formed on a channel between the first and second ferromagnetic bodies, a first... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070115718 - Multi-layered magnetic memory structures: An exemplary memory array including a plurality of memory cells, each of the memory cells comprises a first ferromagnetic layer, a second ferromagnetic layer spaced apart from the first ferromagnetic layer by a non-magnetic separating layer and being magnetically coupled to the first ferromagnetic layer by demagnetizing fields from the... Agent: Hewlett Packard Company
20070115717 - Reference cell scheme for mram: An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a... Agent: George O. Saile
20070115719 - Pulse width converged method to control voltage threshold (vt) distribution of a memory cell: A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different binary state and has a voltage threshold distribution. A constant operating voltage is maintained... Agent: Akin Gump Strauss Hauer & Feld L.L.P.
20070115720 - Non-volatile semiconductor memory device and method for operating a non-volatile memory device: Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile memory cells adapted to replace a defective array column, a column decoder,... Agent: Slater & Matsil LLP
20070115721 - Non-volatile memory and method with compensation for source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070115722 - Non-volatile memory and method with control gate compensation for source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070115723 - Nand type multi-bit charge storage memory array and methods for operating and fabricating the same: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors... Agent: Martine Penilla & Gencarella, LLP
20070115724 - Nonvolatile semiconductor memory with low-loading bit line architecture and method of programming the same: A NAND flash memory device includes an array of NAND flash memory cells; a plurality of word lines connected to the NAND flash memory cells; and a plurality of bit lines connected to the NAND flash memory cells. Each bit line includes a first bit line portion, a second bit... Agent: Volentine Francos, & Whitt PLLC
20070115725 - Low-voltage, multiple thin-gate oxide and low-resistance gate electrode: A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070115726 - Method, system and circuit for programing a non-volatile memory array: The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a... Agent: Eitan Law Group C/o Landonip, Inc.
20070115727 - Flash memory device having pump with multiple output voltages: A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage.... Agent: Marger Johnson & Mccollom, P.C.
20070115728 - Array source line (avss) controlled high voltage regulation for programming flash or ee array: A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS... Agent: Schneck & Schneck
20070115729 - Method and apparatus for reducing stress in word line driver transistors during erasure: In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, the method comprising the steps of:... Agent: Duane Morris, LLPIPDepartment
20070115730 - Methods and systems for high write performance in multi-bit flash memory devices: Methods and circuits are presented for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to... Agent: Eschweiler & Associates, LLC National City Bank Building
20070115731 - Data access methods and storage subsystems thereof: Data access methods and storage subsystems thereof for reading data from storage devices in a redundant array of independent disks (RAID) system are provided. After a controller receives a read request, the target data that the controller is about to read and the sub-stripe(s) where the target data is located... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070115732 - Input circuit for memory device: An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data processing speed by advancing an operation... Agent: Ladas & Parry LLP
20070115733 - Circuits and methods for data bus inversion in a semiconductor memory: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number... Agent: Myers Bigel Sibley & Sajovec
20070115734 - Method of operating an integrated circuit tester employing a float-to-ratio conversion with denominator limiting: A digital integrated circuit tester is prepared for testing a device having multiple time domains by specifying at least two cycle durations as literal times and selecting one of the cycle durations as a reference cycle duration. For each cycle duration other than the reference cycle duration, the literal time... Agent: Smith-hill And Bedell, P.C.
20070115735 - Semiconductor integrated circuits and test methods thereof: A semiconductor integrated circuit that can be tested in a reduced test time includes a high-frequency receiving circuit for receiving a high-frequency signal, and a demodulation circuit for demodulating a signal received from the high-frequency receiving circuit. The demodulation circuit includes an SRAM, an SRAM control circuit, and a test... Agent: Birch Stewart Kolasch & Birch
20070115736 - Semiconductor memory device having a single input terminal to select a buffer and method of testing the same: A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminals and an input terminal to select a buffer. The input-output buffers are coupled... Agent: Marger Johnson & Mccollom, P.C.
20070115738 - Failure management method for a storage system: Provided is a method of performing backup and recovery of data by using journaling, and performing management upon occurrence of a failure. The method includes: a first step of setting a recovery point indicative of the given time; a second step of creating an information of correspondence between the snapshot... Agent: Stanley P. Fisher Reed Smith LLP
20070115740 - Method and apparatus for driver circuit: A method includes a row precharge voltage applied to a node and a column voltage that is set. A row enable signal is pulsed to a switching device coupled between the node and the column voltage to cause the node voltage to be lowered to a desired level.... Agent: Hewlett Packard Company
20070115737 - Method and apparatus for reading data from nonvolatile memory: Various embodiments address the problem of efficiently reading data from nonvolatile memory. Nonvolatile memory circuit, method, and manufacturing method embodiments relate to a virtual ground array of nonvolatile memory cells which are read by precharging the drains of multiple nonvolatile memory cells and measuring the resulting currents. Power consumption and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070115739 - Output circuit of a memory and method thereof: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070115741 - Current sensing circuit and boost converter having the same: A current sensing circuit and a boost converter including the current sensing circuit are disclosed. The current sensing circuit includes a switching device, a sensing transistor, and a current sensing amplifier, and senses the current flowing through the switching device. The current sensing amplifier maintains a potential of an output... Agent: Townsend And Townsend And Crew, LLP
20070115742 - Sense amplifier for a non-volatile memory device: The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback... Agent: Leffert Jay & Polglaze, P.A.
20070115743 - Memory architecture with serial peripheral interface: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20070115744 - Register read for volatile memory: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read... Agent: Qualcomm Incorporated
20070115745 - Fuse box, method of forming a fuse box, and fuse cutting method: A fuse of a fuse box includes a fuse line with a plurality of sub-fuse lines. A fuse cutting method involves selectively cutting sub-fuse lines of a fuse line.... Agent: Marger Johnson & Mccollom, P.C.
20070115746 - Internal voltage generation circuit of semiconductor memory device: Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column... Agent: Marshall, Gerstein & Borun LLP
20070115747 - Semiconductor device including voltage level conversion output circuit: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for... Agent: Arent Fox PLLC
20070115748 - Semiconductor integrated circuit: Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires... Agent: Stanley P. Fisher Reed Smith LLP
20070115749 - Voltage reference circuit using programmable metallization cells: A programmable metallization cell voltage reference is disclosed. The voltage reference can be taken from the anode to ground, from the cathode to ground, or differentially across the programmable metallization cell device.... Agent: Snell & Wilmer L.L.P. (main)
20070115750 - Column decoder of semiconductor memory device, and method of generating column selection line signal in semiconductor memory device: A column decoder of a semiconductor memory device includes an internal address output circuit, an address decoder, and a control circuit. The internal address output circuit converts an external column address into an internal column address and outputs the internal column address. The address decoder decodes a pre-decoded column address,... Agent: F. Chau & Associates, LLC
20070115751 - Latency control circuit and method thereof and an auto-precharge control circuit and method thereof: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the... Agent: Harness, Dickey & Pierce, P.L.C
20070115752 - Output driver and output driving method for enhancing initial output data using timing: An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being... Agent: F. Chau & Associates, LLC05/17/2007 > patent applications in patent subcategories. archived listing by USPTO class
20070109828 - Refresh control circuit of pseudo sram: Disclosed herein is a refresh control circuit of a pseudo SRAM. According to the present invention, a single bank select signal for performing a retresh operation on one bank in a period where a chip select signal is enabled, or until a period before a time for reading or writing... Agent: Marshall, Gerstein & Borun LLP
20070109829 - Dynamic time sequence control device and its method for word matching circuit: A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-charging phase period a current... Agent: Birch Stewart Kolasch & Birch
20070109830 - Data collector: A data collector to be installed in an electrical storage device has a data reader and a base. The data reader is to be connected to the electrical storage device to store status data detected by the electrical storage device. The stored data has a specific format. The stored data... Agent: Troxell Law Office PLLC Suite 1404
20070109833 - Daisy chain cascading devices: A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data,... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
20070109832 - Eco cell for reducing leakage power: A semiconductor structure includes a first conductive line for connecting to a power supply, and a second conductive line for connecting to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at lease one normal cell,... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP
20070109831 - Semiconductor product and method for forming a semiconductor product: A semiconductor product includes a first semiconductor chip that includes input/output circuitry enabling transfer of data from memory banks of the semiconductor product to an external electronic device and/or from an external electronic device to the memory banks of the semiconductor product. A number of second semiconductor chips are stacked... Agent: Slater & Matsil LLP
20070109834 - Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same: A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109835 - Cross-point rram memory array having low bit line crosstalk: A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed... Agent: Robert D. Varitz
20070109836 - Thermally insulated phase change memory device and manufacturing method: A thermally insulated memory device comprises a memory cell, the memory cell having electrodes with a via extending therebetween, a thermal insulator within the via and defining a void extending between the electrode surfaces. A memory material, such as a phase change material, is within the void and electrically couples... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070109837 - System comprising an electronic device and method of operating a system: A display device is provided in which the electro-optical effect is created through bending of bendable elements, particularly nanowires or nanotubes. Arrays of bendable elements are provided in areas of the display with the light path. This is possible in that the bendable elements are transparent in the case where... Agent: Philips Intellectual Property & Standards
20070109841 - Load-balanced apparatus of memory: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to... Agent: Michael W. Taylor
20070109838 - Magnetic memory device: A memory cell (310) for a magnetic memory device (300) includes a free layer (311), a cap layer, an antiferromagnetic layer, and a synthetic antiferromagnetic layer which comprises two or more than two ferromagnetic layers that are antiferromagnetically coupled through non-magnetic space layers. The synthetic antiferromagnetic layer is pinned by... Agent: Davidson Berquist Jackson & Gowdey LLP
20070109842 - Magnetic memory layers thermal pulse transitions: A ferromagnetic thin-film based digital memory having a bit structures therein a magnetic material film in which a magnetic property thereof is maintained below a critical temperature above which such magnetic property is not maintained, and may also have a plurality of word line structures each with heating sections located... Agent: Kinney & Lange, P.A.
20070109840 - Memory write circuit: A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell.... Agent: Slater & Matsil LLP
20070109839 - Mram read sequence using canted bit magnetization: A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage... Agent: Honeywell International Inc.
20070109843 - Phase change memory device and manufacturing method: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070109844 - Semiconductor memory device and method for driving semiconductor memory device: A semiconductor memory device includes a memory cell including a floating body region in an electrically floating state and storing data by accumulating or discharging charges in or from the floating body region; a memory cell array including a plurality of the memory cells; a word line connected to a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109849 - Compensating for coupling during read operations of non-volatile memory: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070109851 - Method of manufacturing non-volatile memory and method of operating non-volatile memory array: A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region... Agent: Jianq Chyun Intellectual Property Office
20070109848 - Nonvolatile semiconductor memory and fabrication method for the same: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109850 - Read operation for non-volatile storage that includes compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070109852 - One time programming memory cell using mos device: A non-volatile memory cell based on a soft breakdown mechanism is provided. The memory cell comprises a resistor coupled serially to a gate or source/drain regions of a MOS device. When a soft breakdown occurs to the MOS device, leakage current flowing through the gate dielectric increases. The change of... Agent: Slater & Matsil, L.L.P.
20070109853 - Systems and methods for a magnetic memory device that includes a single word line transistor: An MRAM cell comprises a magnetic metal layer and a magnetic sensing device in close proximity to the magnetic metal layer. One end of the magnetic metal layer is coupled with a word line transistor and a diode is included and configured to couple the magnetic sensing device to a... Agent: Baker & Mckenzie LLP Patent Department
20070109855 - Electrical device with readable storage data: In one aspect, an electrical device with an I2C EEPROM as a storage medium, to which a clock line and a data line are electrically connected is provided. A first terminal and a second terminal are externally accessible and in conjunction with a capacitor for buffering the I2C EEPROM enable... Agent: Siemens Corporation Intellectual Property Department
20070109854 - Semiconductor memory device capable of memorizing multivalued data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109856 - Method of managing fails in a non-volatile memory device and relative memory device: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20070109857 - Non-volatile semiconductor memory device and operating method thereof: A non-volatile semiconductor memory device comprises a memory cell array having a plurality of electrically-programmable non-volatile memory cells; a byte scan section detecting errors of said non-volatile memory cells per byte and outputting a status of pseudo-pass even though a number of byte errors are equal to or less than... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109858 - Novel method and structure for efficient data verification operation for non-volatile memories: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109859 - Latched programming of memory and method: Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109861 - Method for operating single-poly non-volatile memory device: A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of... Agent: North America Intellectual Property Corporation
20070109860 - Single-poly non-volatile memory device and its operation method: A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls... Agent: North America Intellectual Property Corporation
20070109862 - Flash memory device and word line enable method thereof: In one aspect, a word line enable method in a flash memory device includes driving a signal line corresponding to a selected word line with a word line voltage, and stepwise increasing a gate voltage of a switch transistor connected between the selected word line and the signal line during... Agent: Volentine Francos, & Whitt PLLC
20070109845 - Compensating for coupling during read operations of non-volatile memory: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070109847 - Non-volatile memory and method with improved sensing: A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109846 - Read operation for non-volatile storage that includes compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070109863 - Power regulation in radio-frequency transmitters: An apparatus for regulation of the signal power of a transmitter includes a control loop. The control loop includes a controlled module, a voltage detector, an evaluation circuit and an input amplification module. A decoupling module decouples the output of the control loop from a downstream electrical load.... Agent: Brinks Hofer Gilson & Lione
20070109864 - Selective operation of a multi-state non-volatile memory system in a binary mode: A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109866 - Method of programming and verifying cells of a nonvolatile memory and relative nand flash memory: A method of programming cells in a nonvolatile memory is based upon a Global Verify operation and a Byte-by-byte Verify operation. The cells of a destination page of the nonvolatile memory are programmed, and logic values stored in the programmed cells of a source page of the same memory are... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20070109865 - Radiation tolerant combinational logic cell: A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic... Agent: Haverstock & Owens LLP
20070109867 - Use of data latches in cache operations of non-volatile memories: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109868 - Word line driving circuit of semiconductor memory device: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor... Agent: Marshall, Gerstein & Borun LLP
20070109871 - Nrom flash memory with self-aligned structural charge separation: A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride layer, is comprised of two sections that each have structurally defined and separated charge trapping regions. A charge is stored on a... Agent: Leffert Jay & Polglaze, P.A.
20070109869 - Operation method of non-volatile memory: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive... Agent: Jianq Chyun Intellectual Property Office
20070109870 - Semiconductor memory device: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS... Agent: Miles & Stockbridge PC
20070109872 - Single-poly non-volatile memory device and its operation method: A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls... Agent: North America Intellectual Property Corporation
20070109873 - Non-volatile memory device having controlled bulk voltage and method of programming same: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by... Agent: Volentine Francos, & Whitt PLLC
20070109874 - Time-lapse cell cycle analysis of unstained nuclei: The present invention provides a cell imaging technique for automatically tracking the progression of a cell through the cell cycle over time through segmentation of a volume of two-dimensional time-lapse images. The technique allows long-term tracking of the cell cycle progression of an individual cell or multiple cells. Further, the... Agent: General Electric Company (pcpi) C/o Fletcher Yoder
20070109875 - Data storage method and information processing device using the same: A hierarchical-search-based motion vector search, which stores both a non-reduced image and a reduced image in an external memory, has the problem of wasting the external memory capacity and the memory bandwidth. An information processing device according to the present invention exchanges data in a range wider than the memory... Agent: Antonelli, Terry, Stout & Kraus, LLP
20070109877 - Regulating voltages in semiconductor devices: The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining... Agent: Williams, Morgan & Amerson
20070109876 - Semiconductor memory device with mos transistors each having floating gate and control gate and method of controlling the same: A semiconductor memory device includes memory cells, a memory cell array, a first voltage generating circuit, a reference voltage generating circuit, and a first voltage control circuit. Each of the memory cells includes a first MOS transistor comprising a floating gate and a control gate formed on the floating gate.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109878 - Memory device with improved writing capabilities: Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda
20070109879 - Physical quantity detecting device and imaging apparatus: A physical quantity detecting device includes: a detecting unit that detects a physical quantity supplied from the outside; and pixels which are two-dimensionally arranged and each of which has a selecting transistor for outputting a signal from the detecting unit to a signal line. In the physical quantity detecting device,... Agent: Sonnenschein Nath & Rosenthal LLP
20070109880 - Digital i/o timing control: When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference... Agent: Mendelsohn And Associates, P.C.
20070109883 - Apparatus and method to reconfigure a storage array: A method is disclosed to reconfigure a storage array. The method supplies a data storage and retrieval system comprising (N) data storage device assemblies, wherein each of those (N) data storage device assemblies comprises (M) data storage devices, wherein (N) is greater than or equal to 2, and wherein (M)... Agent: Dale F. Regelman
20070109886 - Block redundancy implementation in heirarchical ram's: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder... Agent: Christopher C. Winslade
20070109885 - Defect analysis place specifying device and defect analysis place specifying method: A defect analysis place specifying device for specifying defect analysis places from an inspection result of produced printed wiring boards in an electronic part mounting device for mounting parts on the printed wiring boards through plural steps, including an accepting unit for accepting plural printed wiring boards as inspection targets... Agent: Foley And Lardner LLP Suite 500
20070109881 - Management of defective blocks in flash memories: The invention relates to a method for the management of defective memory blocks in a non-volatile memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks can be addressed by means of an address conversion that... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20070109882 - Method and apparatus for redundant memory configuration in voltage island: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a... Agent: Michael J. Lestrange International Business Machines Corporation
20070109884 - Pseudo-dual port memory having a clock for each port: A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge... Agent: Qualcomm Incorporated
20070109888 - Integrated circuit with test circuit: An integrated circuit including an input/output pad, an intergrated circuit, and a test circuit. The input/output pad is configured to receive first output signals of another integrated circuit that are based on input signals. The internal circuit is configured to receive the input signals and provide second output signals based... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070109887 - Memory device that provides test results to multiple output pads: A memory device including at least two output pads and at least two memory die. Each of the at least two memory die is configured to provide an output signal that includes compressed test results to any of the at least two output pads.... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070109889 - Non-volatile memory and method with reduced source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070109890 - Memory, processing system and methods for use therewith: A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces... Agent: Garlick Harrison & Markison
20070109891 - Semiconductor memory device and method for driving semiconductor memory device: A semiconductor memory device includes a memory cell including a floating body; a word line connected to a gate of the memory cell; a data bit line connected to the memory cell and transmitting the data stored in the memory cell; a reference bit line transmitting a reference voltage; a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070109892 - Memory device and method of operating the same: A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the... Agent: Mills & Onello LLP
20070109893 - Sram circuitry: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from... Agent: Dechert LLP
20070109894 - Systems and methods for reading and writing a magnetic memory device: An MRAM cell comprises a magnetic metal layer and a magnetic sensing device in close proximity to the magnetic metal layer. One end of the magnetic metal layer is coupled with a word line transistor, while the other end of the magnetic metal layer is coupled to a first bit... Agent: Baker & Mckenzie LLP Patent Department
20070109895 - Semiconductor memory device and method for reading semiconductor memory device: A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell 11 connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell 12 connected to a word line... Agent: Rader Fishman & Grauer PLLC
20070109896 - Data storage device and refreshing method for use with such device: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing... Agent: Neil A. Steinberg
20070109897 - Semiconductor memory device: A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority.... Agent: Arent Fox PLLC
20070109898 - Semiconductor device: Each of switching circuits included in each of semiconductor memory chips performs switching among interface functions of predetermined second external connecting electrodes by bonding options in accordance with states of potentials applied to first external connecting electrodes. The second external connecting electrodes intended for interchange of the interface functions are... Agent: Miles & Stockbridge PC
20070109900 - Nonvolatile memory apparatus: Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a... Agent: Miles & Stockbridge PC
20070109899 - Programmable logic device memory elements with elevated power supply levels: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During... Agent: G. Victor Treyz
20070109901 - Semiconductor device including voltage level conversion output circuit: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for... Agent: Arent Fox PLLC
20070109902 - Semiconductor device including voltage level conversion output circuit: A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for... Agent: Arent Fox PLLC
20070109904 - Memory core and semiconductor memory device having the same: A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column... Agent: Mills & Onello LLP
20070109903 - Method of modeling physical layout of an electronic component in channel simulation: A method of developing the physical layout of an electronic component in a data bus connected logic analog system includes: providing a data bus connected logic analog system modeled as a software-implemented channel simulation model including: a bit pattern generator for generating a bit pattern; the electronic component, whose physical... Agent: Edell, Shapiro & Finnan, LLC
20070109905 - Semiconductor memory device for achieving high reliability without increasing process complexity and cost: A semiconductor memory device is provided with a DRAM array and a control circuit. The DRAM array includes first and second storage areas. The control circuit controls an access to said DRAM array so that data hold characteristics of said first storage area are superior to those of said second... Agent: Young & Thompson
20070109906 - Word line driver for dram embedded in a logic process: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep... Agent: Bever Hoffman & Harms, LLP Tri-valley Office
20070109908 - Individual data line strobe-offset control in memory systems: Systems and methods for strobe signal timing calibration and control in strobe-based memory systems are provided below. These strobe-offset control systems and methods receive a strobe signal from a memory device and in turn automatically generate separate per-bit strobe signals for use in receiving data on each data line of... Agent: Shemwell Mahamedi LLP
20070109907 - Synchronization circuit for a write operation on a semiconductor memory: A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.
20070109909 - Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent: A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation.... Agent: Qualcomm Incorporated05/10/2007 > patent applications in patent subcategories. archived listing by USPTO class
20070103953 - Content addressable memories (cams) based on a binary cam and having at least three states: Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM... Agent: Ryan, Mason & Lewis, LLP Suite 205
20070103954 - Memory circuit: There is provided a memory circuit including a first memory cell mapped on an address space accessible from a processor, and a second memory cell not mapped on the address space and having the same constitution as that of the first memory cell, wherein a control circuit for executing a... Agent: Mcdermott Will & Emery LLP
20070103957 - Data transfer in a memory device: A method transfers data in a memory device including at least one memory module and a memory controller. The method includes coupling the memory module to the memory controller via a mechanically detachable data transfer connection, transferring data between the memory controller and an interface unit assigned to the memory... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070103955 - Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20070103956 - Semiconductor memory: At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit than the complete cell array. The signal control... Agent: Arent Fox PLLC
20070103958 - Semiconductor memory device capable of realizing a chip with high operation reliability and high yield: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20070103959 - Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge... Agent: Ryan, Mason & Lewis, LLP
20070103960 - Method for operating a data storage apparatus employing passive matrix addressing: In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse... Agent: Birch Stewart Kolasch & Birch
20070103961 - Ram cell with soft error protection using ferroelectric material: A static random access memory (SRAM) cell with single event and soft error protection using ferroelectric material is presented. The SRAM cell comprises two inverters in a mutual feedback loop, with the output of each of the inverters coupled to the input of the other. A ferroelectric capacitor is coupled... Agent: Honeywell International Inc.
20070103963 - Non-volatile memory devices and method thereof: Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured... Agent: Harness, Dickey & Pierce, P.L.C
20070103962 - Programmable memory cell and operation method: A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory... Agent: J.c. Patents, Inc.
20070103964 - Resistive memory devices including selected reference memory cells and methods of operating the same: A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be... Agent: Myers Bigel Sibley & Sajovec
20070103966 - Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects... Agent: Sierra Patent Group, Ltd.
20070103965 - Memory cell with a vertically integrated delay element: A method and device for a vertically integrated delay element are presented. The vertically integrated delay element includes a portion of an interconnect sandwich. The interconnect sandwich includes dielectric layers and metal layers. The portion of the interconnect sandwich is used to form a capacitor, such as a Metal Insulator... Agent: Honeywell International Inc.
20070103969 - Method and apparatus for reading data from a ferromagnetic memory cell: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor... Agent: Morgan Lewis & Bockius LLP
20070103967 - Non-homogeneous shielding of an mram chip with magnetic field sensor: The present invention provides a magnetoresistive memory device (30) comprising an array (20) of magnetoresistive memory elements (10) and at least one magnetic field sensor element (32), wherein the magnetoresistive memory device (30) comprises a partial or non-homogeneous shielding means (40, 41) so as to shield the array (20) of... Agent: Philips Intellectual Property & Standards
20070103970 - Non-volatile ferromagnegtic memory having sensor circuitry shared with its state change circuitry: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and... Agent: Morgan Lewis & Bockius LLP
20070103968 - Non-volatile memory device conducting comparison operation: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a... Agent: Buchanan, Ingersoll & Rooney PC
20070103971 - Memory device with a plurality of memory cells, in particular pcm memory cells, and method for operating such a memory cell device: The invention relates to a method for operating a memory device, and to a memory device with a plurality of memory cells (1) which each have at least one switching device (13) assigned thereto for controlling, as well as a current supply line and a current discharge line (11, 12),... Agent: Morrison & Foerster LLP
20070103972 - Non-volatile phase-change memory device and method of reading the same: In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series... Agent: Volentine Francos, & Whitt PLLC
20070103976 - Flexible and area efficient column redundancy for non-volatile memories: The present invention presents a non-volatile memory wherein bad columns in the array of memory cells can be removed. According to another aspect of the present invention, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070103975 - Read operation for non-volatile storage that includes compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103978 - Memory with retargetable memory cell redundancy: In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070103980 - Method for operating a semiconductor memory device and semiconductor memory device: A method for restoring information stored in a memory cell that has a variable characteristic indicating the stored information, wherein a first state is stored if the characteristic is below a reading threshold or a second state is stored if the characteristic is above the reading threshold. The method includes... Agent: Slater & Matsil LLP
20070103977 - Retargetable memory cell redundancy methods: In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070103981 - Reverse coupling effect with timing information: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103979 - Reverse coupling effect with timing information for non-volatile memory: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103982 - Read operation for non-volatile storage that includes compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103983 - Nonvolatile semiconductor memory: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701
20070103984 - Clustered hierarchical file system: A system for object-based archival data storage includes an object-based storage subsystem having respective data storage devices, at least one file presentation interface that interfaces to client platforms, an administration interface having graphical user interface (GUI) and a command line interface (CLI), a meta data subsystem for storing meta data... Agent: Brooks Kushman P.C. / Sun / Stk
20070103985 - Fabricating bi-directional nonvolatile memory cells: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can... Agent: Volentine Francos, & Whitt PLLC
20070103973 - Memory architecture: A memory architecture includes a matrix of memory cells structured into rows and columns and associated with a row decoder, an array of reference cells associated with the matrix, a first detector block including plural sense amplifiers associated with the matrix in correspondence with its columns, and a plurality of... Agent: Seed Intellectual Property Law Group PLLC
20070103986 - Compensating for coupling during read operations of non-volatile memory: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103987 - Read operation for non-volatile storage that includes compensation for coupling: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly... Agent: Vierra Magen/sandisk Corporation
20070103988 - Circuit arrangement and method for controlling an inductive load: A circuit configuration controls an inductive consumer, especially protecting the consumer from being accidentally turned on. The circuit configuration contains a free-wheeling circuit for reducing energy stored in the consumer. In order to prevent the consumer from being accidentally turned on when a grounding wire between an energy store and... Agent: Lerner Greenberg Stemer LLP
20070103989 - Data processing device having flash rom, and a flash rom data erasing method: A data processing device 1 has flash ROM having a plurality of sectors, and a CPU for erasing data stored in a predetermined area of the flash ROM. A plurality of erase areas is set in the flash ROM based on the sector structures of a plurality of flash ROM... Agent: Edwards & Angell, LLP
20070103991 - Integrated code and data flash memory: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP
20070103990 - Methods of erasing and designing electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge... Agent: Myers Bigel Sibley & Sajovec
20070103974 - Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution: A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to check whether a threshold voltage of... Agent: Arent Fox PLLC
20070103992 - Memory system: A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in... Agent: Rader Fishman & Grauer PLLC
20070103993 - Personal portable devices: This application provides novel computer systems and method using novel personal portable consumer devices wherein the personal portable devices store, secure, communicate, and with or without an associated personal computer, process transaction data and incentive offers for the consumer.... Agent: NeifeldIPLaw, PC
20070103994 - Regulation circuit for inductive charge pump: Embodiments of an inductive charge pump are generally described herein. Other embodiments may be described and claimed.... Agent: Fleshner-kim, LLP Intel Corporation
20070103995 - Address decoding: A signal interface for interfacing with an address decoder and a method of address decoding are disclosed. The signal interface comprises: a signal capture element operable to receive an address portion signal associated with a read access to a memory and to provide a first interim address portion signal and... Agent: Nixon & Vanderhye, PC
20070103996 - Data input/output circuit having data inversion determination function and semiconductor memory device having the same: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output... Agent: Mills & Onello LLP
20070103997 - System for restricting data access: A filter is arranged to selectively block or allow a data access command from an initiator according to whether the initiator is secure or insecure and whether a data source or destination being accessed is privileged or unprivileged. The data access command contains an identification of the initiator from which... Agent: Seed Intellectual Property Law Group PLLC
20070104001 - Current reduction circuit of semiconductor device: A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an isolation controller which is enabled... Agent: Marshall, Gerstein & Borun LLP
20070104000 - Field programmable memory repair for eprom: The present invention according to certain embodiments is directed to a method, device and apparatus for repairing a plurality of memory locations. The present invention includes providing a plurality of memory locations, providing a plurality of fuses coupled to the memory locations and loading fuse data into a data register... Agent: Squire, Sanders & Dempsey L.L.P.
20070103999 - Redundancy circuit and semiconductor apparatus having the redundancy circuit: When a redundancy circuit is fully used and a further defect is present, an irreparable-state signal is produced. When the irreparable-state signal is produced, a defect is judged. When the irreparable-state signal is not produced, upon testing for quality judgment, extraction of a defective memory cell, programming an address of... Agent: Young & Thompson
20070103998 - Semiconductor memory for relieving a defective bit: A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the... Agent: Arent Fox PLLC
20070104003 - Memory device with auxiliary sensing: A semiconductor memory device may include bit line coupled to a sense amplifier and an auxiliary sensing unit to drive an output line in response to the voltage of the bit line during a read operation. In some embodiments, the auxiliary sensing unit may include a differential amplifier arranged to... Agent: Marger Johnson & Mccollom, P.C.
20070104004 - Multi-bit-per-cell flash eeprom memory with refresh: A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070104002 - Semiconductor memory device with mos transistors each having floating gate and control gate and method of controlling the same: A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, first sense amplifiers and second sense amplifiers. The memory cell array includes memory cells arranged in a matrix. The first bit line connects commonly the memory cells in a same column. The second bit line... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070104005 - Method and apparatus for reducing standby current in a dynamic random access memory during self refresh: A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070104006 - Memory core and method thereof: A memory core and method thereof are provided. The example memory core may include an edge sub-array including a plurality of word lines, a plurality of bit lines, and a plurality of dummy bit lines, a sense amplifier circuit configured to amplify voltages of the plurality of dummy bit lines... Agent: Harness, Dickey & Pierce, P.L.C
20070104007 - Data distribution processing system, data distribution processing method, and program: A first copier acquires data and determines a plurality of recipients to deliver split data. A data splitter 308 splits data into a plurality of data blocks and a dummy data generator 315 generates dummy data. A data delivery unit 310 delivers the data blocks and dummy data to the... Agent: Fitzpatrick Cella Harper & Scinto
20070104008 - Bit-line sense amplifier driver: In a memory device that operates at high speed, a bit-line sense amplifier driver is provided to overdrive a sense amplifier in a refresh mode. A bit-line sense amplifier driver includes a refresh overdriving control unit that is coupled to an external power supply terminal and a sense amplifier power... Agent: Venable LLP
20070104009 - Flash/dynamic random access memory field programmable gate array: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory... Agent: Sierra Patent Group, Ltd.
20070104010 - Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory: A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power... Agent: Dickstein Shapiro LLP
20070104011 - Cell array of semiconductor memory device and a method of forming the same: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a... Agent: Volentine Francos, & Whitt PLLC
20070104012 - Semiconductor storage device: The objective of the present invention is to provide a semiconductor storage device wherein a low active current is obtained by reducing the number of sense amplifiers to be activated at a time. An SDRAM has a divided word line structure, and includes a plurality of banks, each of which... Agent: W. Riyon Harding 972e
20070104013 - Apparatus for controlling column selecting signal of semiconductor memory apparatus and method of controlling the same: An apparatus for controlling a column selecting signal of semiconductor memory apparatus comprising a column decoder that outputs a first column selecting signal, a signal control unit that outputs a second column selecting signal that is generated by controlling an enable period of the first column selecting signal, and an... Agent: Venable LLP
20070104014 - Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency: A circuit arrangement for generating an n-bit output pointer in a semiconductor memory comprises at least one m-bit interface for accepting an m-bit reference signal, at least one m-bit binary counter, a decoder arrangement connected downstream of the binary counter, and outputs for providing the bits of the output pointer.... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.
20070104015 - Clock signal generation techniques for memories that do not generate a strobe: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is... Agent: Qualcomm Incorporated
20070104017 - Memory controller and memory system: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20070104016 - Semiconductor device and control method therefor: The invention is a semiconductor device that includes a memory cell array having non-volatile memory cells, and a control circuit that writes data into the memory cell array by programming memory cells to be programmed to a first level and then programming the memory cells to a second level, and... Agent: Wagner, Murabito & Hoa LLP
20070104018 - Apparatus and method for improving dynamic refresh in a memory device: An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time delay portion and a reset portion may be used to generate a close signal. The time delay portion may define a predetermined time... Agent: Jones Day05/03/2007 > patent applications in patent subcategories. archived listing by USPTO class
20070097723 - Area efficient stacked tcam cell for fully parallel search: An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM cell includes a pair of memory... Agent: Texas Instruments Incorporated
20070097722 - Circuit and method for subdividing a camram bank by controlling a virtual ground: A CAM bank is functionally divided into two or more sub-banks, without replication CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of... Agent: Qualcomm Incorporated
20070097724 - Nonvolatile semiconductor memory device and its writing method: A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is... Agent: Morrison & Foerster LLP
20070097725 - Semiconductor integrated circuit and contactless electronic device using the same: There is provided a semiconductor integrated circuit provided with a charge pump circuit of low power consumption, capable of maintaining an output voltage thereof at a predetermined voltage level without causing current consumption to undergo intermittent variation, and a contactless electronic device using the semiconductor integrated circuit. With respective charge... Agent: Miles & Stockbridge PC
20070097727 - Nonvolatile ferroelectric perpendicular electrode cell, feram having the cell and method for manufacturing the cell: A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to... Agent: Heller Ehrman LLP
20070097726 - Semiconductor device and manufacturing method of the same: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20070097728 - Data holding circuit: A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error... Agent: Foley And Lardner LLP Suite 500
20070097729 - Semiconductor memory device and semiconductor device: A flip-flop includes a first storage node at one terminal and a second storage node at the other terminal. The gate of a first MOS connects to the first storage node. The gate of a second MOS connects to the second storage node. One end of the current path of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097733 - Controllably connectable strings of mram cells: A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM... Agent: Hewlett Packard Company
20070097730 - Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells: A method and system for providing a magnetic memory is described. The magnetic memory includes a plurality of magnetic storage cell and at least one bit line and a plurality of source lines corresponding to the plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element that... Agent: Sawyer Law Group LLP
20070097732 - Magnetic tunnel junction current sensors: An integrated circuit device is provided which includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit... Agent: Ingrassia, Fisher & Lorenz, P.C.
20070097735 - Semiconductor memory device: In a writing method of a semiconductor memory device according to an aspect of the present invention, writing is carried out by using a magnetic field generated by a write current that flows through a write line in such a manner that one end of the write line is established... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097736 - Spin-injection magnetic random access memory: A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which applies, to the magnetoresistive element, a magnetic field of a direction of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097734 - Thermally assisted integrated mram design and process for its manufacture: A memory element uses a conventional MTJ for reading purposes and a separate magnetic reference stack which is briefly heated while information is written into it. This information is then magnetostatically imposed on the MTJ's free layer which is located nearby. In this way the MTJ can be optimized for... Agent: Stephen B. Ackerman
20070097731 - Tuned pinned layers for magnetic tunnel junctions with multicomponent free layers: Apparatus and methods for optimizing a toggle window for a magnetic tunnel junction (MTJ) having a multicomponent free layer are provided. In accordance with an aspect of the invention, a MTJ comprises a free layer, a pinned layer, and a barrier layer formed between the free layer and the pinned... Agent: Ryan, Mason & Lewis, LLP
20070097740 - Content-addressable memory having phase change material devices: Content-addressable memory (CAM) cells comprised of phase change material devices (PCMDs), including PCMD-based binary CAM cells (PCMD-based BCAM cells), PCMD-based ternary CAM cells (PCMD-based TCAM cells), and PCMD-based universal CAM cells (PCMD-based UCAM cells). The PCMDs of the various PCMD-based CAM cells are configured and programmed in a manner that... Agent: Thelen Reid Brown Raysman & Steiner LLP
20070097737 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element includes a bottom electrode 12, a bit line 14 provided on the bottom electrode 12, and a recording layer 15 containing phase change material connected between the bottom electrode 12 and the bit line 14. In accordance with this invention, the bit line 14 is in... Agent: Mcdermott Will & Emery LLP
20070097738 - Electrically rewritable non-volatile memory element and method of manufacturing the same: A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in... Agent: Mcdermott Will & Emery LLP
20070097739 - Phase change memory cell including multiple phase change material portions: A memory cell includes a first electrode, a second electrode, and a first portion of phase-change material contacting the first electrode. The memory cell includes a second portion of phase-change material contacting the second electrode and a third portion of phase-change material between the first portion and the second portion.... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070097741 - Phase change random access memory, boosting charge pump and method of generating write driving voltage: A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps... Agent: Volentine Francos, & Whitt PLLC
20070097742 - Enhanced toggle-mram memory device: A toggle-MRAM device is disclosed that uses an SAF composite and lowers the operating field substantially with a wide operating field margin and high thermal stability using specific magnetic parameters. Consequently, this device enhances the performance of MRAM's, especially in its large operating field margin and high thermal stability characteristics... Agent: Needle & Rosenberg, P.C.
20070097743 - Non-volatile memory in cmos logic process: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain... Agent: Bever Hoffman & Harms, LLP Tri-valley Office
20070097744 - Use of data latches in multi-phase programming of non-volatile memories: A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation
20070097746 - Flash eeprom cell and method of fabricating the same: A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097745 - Modified-layer eprom cell: An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal layer, and a control gate, including a second metal layer. The floating gate is disposed adjacent to the source and drain regions and separated... Agent: Hewlett Packard Company
20070097747 - Apparatus for programming of multi-state non-volatile memory using smart verify: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate... Agent: Vierra Magen/sandisk Corporation
20070097748 - Managing wireless communication with limited channels: Communications between a central station and plural nodes is managed at the central station. The central station has an answer channel, a number of data channels, and a data channel manager. A node transmits a channel request, which is received by the answer channel. The answer channel queries the data... Agent: Decker, Jones, Mcmackin, Mcclane, Hall & Bates, P.C.
20070097749 - Method for programming of multi-state non-volatile memory using smart verify: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate... Agent: Vierra Magen/sandisk Corporation
20070097750 - Nand flash memory and blank page search method therefor: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097751 - Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same: There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating a semiconductor memory cells of a memory cell array, including electrically floating body transistors in which an electrical charge is stored in the body... Agent: Neil A. Steinberg
20070097752 - High speed digital signal input buffer and method using pulsed positive feedback: An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit initially couples a positive feedback signal to the buffer circuit responsive to each transition of the input signal. The positive feedback signal increases the gain... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20070097753 - Memory device, memory system and method of inputting/outputting data into/from the same: A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit... Agent: F. Chau & Associates, LLC
20070097754 - Voltage regulator for a bit line of a semiconductor memory cell: A voltage regulator for a bit line of a semiconductor memory cell is disclosed. In one embodiment, the voltage regulator includes an inverter, a feedback transistor, and a band gap reference voltage source. The inverter includes an inverter input connected to the bit line, and an inverter output. The feedback... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070097755 - Method for comparing a first data set with a second data set: A method for comparing a first data set with a second data set, where each comprises one or more corresponding segments. The method comprises determining the difference between corresponding pairs of end points of corresponding segments, and deeming the first data set to match the second data set if the... Agent: Hewlett Packard Company
20070097757 - Automatic digital variable resistor and display device having the same: An automatic digital variable resistor capable of preventing failure in a liquid crystal display panel and an LCD having the same are provided. The automatic digital variable resistor comprises a programmable memory in which an intermediate value of n-bit data is stored, wherein (n>2) and a voltage adjuster adjusting the... Agent: F. Chau & Associates, LLC
20070097758 - Power supply circuit for delay locked loop and its method: A delay locked loop (DLL) power supply circuit for use in a semiconductor memory device, including: a DLL power supplier for supplying a DLL power supply voltage to a DLL in response to a reference voltage and a clock enable exit pulse signal; and a pulse signal generator for generating... Agent: Blakely Sokoloff Taylor & Zafman
20070097756 - Semiconductor integrated circuit and leak current reducing method: The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to... Agent: Nixon Peabody, LLP
20070097759 - Method of reducing settling time in flash memories and improved flash memory: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing... Agent: Duane Morris, LLPIPDepartment
20070097760 - Compact column redundancy cam architecture for concurrent read and write operations in multi-segment memory arrays: A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the... Agent: Schneck & Schneck
20070097761 - Semiconductor storage device: The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an... Agent: W. Riyon Harding
20070097762 - Semiconductor storage device, redundancy circuit thereof, and portable electronic device: A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion... Agent: Birch Stewart Kolasch & Birch
20070097763 - Manufacturing method of semiconductor integrated circuit device: The invention intends to provide a manufacturing method of a semiconductor integrated circuit device, which can detect an off-specification faulty wafer in real time. An abnormality detection server stores apparatus log data outputted from semiconductor manufacturing apparatus that processes a semiconductor wafer in an apparatus log data memory. Thereafter, in... Agent: Antonelli, Terry, Stout & Kraus, LLP
20070097764 - Capacitor supported precharging of memory digit lines: Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the... Agent: Fish & NeaveIPGroup Ropes & Gray LLP
20070097765 - Dynamic sense amplifier for sram: A dynamic sense amplifier for static random access memory (SRAM) is provided. The dynamic sense amplifier includes a pre-amplifier configured to amplify small input signals according to a first clock signal, and a main sense-latch coupled to the pre-amplifier, wherein the main sense-latch is configured to respond to the small... Agent: Haverstock & Owens LLP
20070097766 - Electro-optic device, method for driving the same, and electronic device: An electro-optic device comprising, a plurality of pixels corresponding to a plurality of scanning lines and a plurality of data lines a scanning-line drive circuit that selects the scanning lines in a predetermined order a block selection circuit that sequentially selects a block including m columns of data lines (m... Agent: Advantedge Law Group, LLC
20070097767 - Amplifier for low-voltage applications: A wheeled machine that rakes lawns and other surfaces to remove leaves, pine needles and other lightweight debris and conveys this material directly into a standard size plastic bag for disposal or transport to a composting location.... Agent: Graybeal Jackson Haley LLP
20070097769 - Semiconductor memory: A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power... Agent: Foley And Lardner LLP Suite 500
20070097768 - System and method for capacitive mis-match bit-line sensing: Dynamic random access memory (DRAM) sensing is accomplished by using capacitive mismatch between a bit line without a cell and a corresponding bit line with a cell to determine if a selected capacitor holds a one or a zero. Isolators on the bit lines are used to create the mismatch.... Agent: Ibm Microelectronics Intellectual Property Law
20070097770 - Method and arrangement in inverter: A method and arrangement in connection with an inverter that comprises several power semiconductor components and a control apparatus arranged to control them, the control apparatus being arranged to control the power semiconductor components in response to a control quantity to generate an output voltage. The method comprises the steps... Agent: Buchanan, Ingersoll & Rooney PC
20070097771 - Asynchronous first-in first-out cell: The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a... Agent: Rosenberg, Klein & Lee
20070097772 - Semiconductor storage device and refresh control method therefor: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal... Agent: Foley And Lardner LLP Suite 500
20070097773 - Semiconductor memory device and method of adjusting same: A DLL Reset signal for delivering Fuse data from anti-fuses is generated from a reset signal which is supplied asynchronous to a clock when an initial setting is made. The DLL Reset signal is supplied to an anti-fuse block which comprises a plurality of anti-fuses, such that the delay amount... Agent: Young & Thompson
20070097774 - Semiconductor memory device: A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA , and a storage block is selected with external address... Agent: Mcdermott Will & Emery LLP
20070097775 - Flash memory device: A flash memory device includes first to nth banks sharing an I/O line, a page buffer unit commonly connected to a bit line of the first to nth banks, for buffering data to be transmitted to the first to nth banks, a first X-decoder connected to a word line of... Agent: Mayer, Brown, Rowe & Maw LLP
20070097776 - Memory control device and memory control method: There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a select circuit 27 is changed by a switch signal... Agent: Arent Fox PLLC
20070097777 - Semiconductor device and method of manufacturing the same: The semiconductor device of the present invention includes a semiconductor substrate, a plurality of floating gate electrodes formed in a memory cell forming region of the semiconductor substrate, a word line electrically connecting the floating gate electrodes and a conductor portion formed on the word line so as to reduce... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070097781 - Ddr ii write data capture calibration: A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined... Agent: Dickstein Shapiro LLP
20070097779 - Generating a sampling clock signal in a communication block of a memory device: A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070097780 - Performing read and write operations in the same cycle for an sram device: A decoding signal circuit is configured to generate a dual operation decoding signal that enables a read operation and a write operation to be performed in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed... Agent: Jonathan O. Owens Haverstock & Owens LLP
20070097778 - System and method for controlling timing of output signals: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLPPrevious industry: Electric power conversion systems
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