Static information storage and retrieval inventions 04/07

20070091661 - Nanocrystal write once read only memory for archival storage: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070091662 - Semiconductor device: A semiconductor device employs two electric fuses (31, 32) connected in parallel to each other. First terminals of the electric fuses (31, 32) are connected to a junction of first and second P-channel transistors (21, 22), which are connected in series between a high potential application line (111) and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070091663 - Cmis semiconductor nonvolatile storage circuit: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a... Agent: Ladas & Parry LLP

20070091664 - Memory device, circuits and methods for reading a memory device: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment... Agent: Marger Johnson & Mccollom, P.C.

20070091666 - Memory architecture and method of manufacture and operation thereof: An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a... Agent: Dickstein Shapiro LLP

20070091667 - Memory circuit as well as method for evaluating a memory datum of a cbram resistance memory cell: The invention relates to a memory circuit (Conductive Bridging RAM), and in particular to a CBRAM having CBRAM resistance elements as memory cells. The invention also relates to a method for evaluating a memory datum of a CBRAM resistance memory cell.... Agent: Morrison & Foerster LLP

20070091665 - Phase change random access memory and method of controlling read operation thereof: A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is... Agent: Volentine Francos, & Whitt PLLC

20070091669 - Giant magneto-resistive static read ram memory architecture: A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary... Agent: Honeywell International Inc.

20070091668 - Magnetic memory device and methods for making a magnetic memory device: A nonvolatile memory device is disclosed. The device includes a substrate, at least one relatively high permeability conductive line, and at least one magnetoresistive memory cell separated from the at least one relatively high permeability conductive line by an insulating material and located in a region of a magnetic field... Agent: Baker & Mckenzie LLP Patent Department

20070091672 - Mram arrays and methods for writing and reading magnetic memory devices: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first... Agent: Baker & Mckenzie On Behalf Of Tsmc

20070091671 - Nonvolatile memory device with write error suppressed in reading data: A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current... Agent: Mcdermott Will & Emery LLP

20070091670 - Thin film magnetic memory device having a highly integrated memory array: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As... Agent: Mcdermott Will & Emery LLP

20070091673 - Semiconductor memory device: A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070091674 - Transistor and method of fabrication: A transistor cell and method of making a transistor cell is disclosed. In one embodiment a transistor cell, includes first metal line spacers and the first gate spacers that vertically at least partially overlap, wherein second metal line spacers and second gate spacers vertically at least partially overlap. A contact... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070091675 - Double bias for a magnetic reader: The present invention provides a tunneling giant magnetoresistance (TGMR) sensor. The sensor including an active region. The active region having a first bias layer. The sensor also including a passive region. The passive region has an insulating layer and a second bias layer. Furthermore, the insulating layer is positioned between... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.

20070091676 - Semiconductor device and methods for forming the same: A semiconductor device includes a first transistor and a second transistor formed on a substrate. Each of the first transistor and the second transistor has a first source region, first drain region of a first conductivity type and a gate. The first transistor is an off-transistor and includes a second... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070091678 - Memory system and operating method of same: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to... Agent: Arent Fox PLLC

20070091677 - Method for recovering from errors in flash memory: Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070091680 - Pipelined parallel programming operation in a non-volatile memory system: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070091679 - Storage device, computer system, and data writing method: A storage device that includes: a flash memory device being a main storage medium; a cache memory for use for the flash memory device; and a control circuit. In the storage device, based on a write command and address information provided from outside, the control circuit selects either the flash... Agent: Rader Fishman & Grauer PLLC

20070091681 - Non-volatile memory with improved programming and method therefor: Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070091682 - Byte-erasable nonvolatile memory devices: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor... Agent: Myers Bigel Sibley & Sajovec

20070091683 - Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage: A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region... Agent: Sierra Patent Group, Ltd.

20070091684 - Buried word line memory integrated circuit system: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the... Agent: Ishimaru & Zahrt LLP

20070091685 - Efficient verification for coarse/fine programming of non-volatile memory: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory... Agent: Vierra Magen/sandisk Corporation

20070091686 - High integrated semiconductor memory device: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units... Agent: Mcdermott Will & Emery LLP

20070091687 - Implantable medical device with reconfigurable non-volatile program: A device comprises a stimulus generator comprising an instruction processor. The stimulus generator is configured to deliver stimuli to a biological tissue. The device also comprises a non-volatile memory for storing instructions directly executable by the instruction processor, the instructions controlling, at least in part, the operation of the device.... Agent: Cyberonics, Inc.

20070091688 - Method of programming a non-volatile memory cell: The present invention relates to a method of programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070091689 - Programmable memory and access method for the same: A programmable memory includes N number of one-time programmable (OTP) memory rows, an output module, a judge module, and a write-in module. The output module receives all data of the OTP memory rows and generates output data. The judge module receives the output data and write-in data and generates write-in... Agent: Birch Stewart Kolasch & Birch

20070091690 - Non-volatile memory cell array for improved data retention and method of operating thereof: A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an... Agent: Larson Newman Abel Polansky & White, LLP

20070091693 - Data input/output (i/o) apparatus for use in a memory device: A data I/O apparatus for use in a memory device. The data I/O apparatus for use in the memory device performs data transmission using the same polarity when neighbor global I/O lines have opposite polarities to reduce coupling noise generated between global I/O lines acting as data I/O lines of... Agent: Marshall, Gerstein & Borun LLP

20070091692 - Method to transfer information between data storage devices: A method is disclosed to transfer information between data storage devices. The method provides an information storage assembly comprising a frame, a memory device disposed on that frame, information written to that memory device, a power supply removeably attached to the frame, and a first data storage device comprising a... Agent: Dale F. Regelman

20070091691 - Wide window clock scheme for loading output fifo registers: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit... Agent: Hogan & Hartson LLP

20070091694 - Flash memory device capable of improving reliability: A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select... Agent: F. Chau & Associates, LLC

20070091695 - Shift register and organic light emitting display device using the same: A shift register capable of reducing power consumption is provided. The shift register includes: a clock signal supply line for supplying a clock signal; a plurality of selectors coupled to the clock signal supply line to generate driving signals in response to sampling signals; and a plurality of stages respectively... Agent: Christie, Parker & Hale, LLP

20070091696 - Memory controller: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070091697 - Device recoverable purge for flash storage device: A flash storage device includes flash storage units that are purged in response to a condition or command while allowing the flash storage device to be used subsequent to the purge. A flash controller interface receives a command for purging the flash storage device and provides a purge command to... Agent: Simpletech, Inc. C/o S. Jalal Sadr, Esq.

20070091698 - Testing method and testing apparatus: A testing method of a semiconductor integrated circuit device includes a testing step of conducting a functional test by supplying test pattern data to a semiconductor integrated circuit device mounted upon a testing apparatus, and a post processing step conducted after the testing step for continuously driving the semiconductor integrated... Agent: Arent Fox PLLC

20070091699 - Sense amplifier organization for twin cell memory devices: A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines.... Agent: Edell, Shapiro & Finnan, LLC

20070091700 - Memory, processing system and methods for use therewith: A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and... Agent: Garlick Harrison & Markison

20070091701 - Semiconductor device and a method of testing the same: The present invention comprises first and second differential pairs (MN31, MN32), (MN33, MN34) to which first and second differential input signals (CIB0, CIT0), (CIB90, CIT90) are input, output pairs of said first and second differential pairs being commonly connected to each other, further connected to load circuits (MN1 to MN4)... Agent: Sughrue Mion, PLLC

20070091702 - Rram controller built in self test memory: An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and logic cells.... Agent: Lsi Logic Corporation

20070091703 - Semiconductor memory: A precharge voltage generating circuit outputs any of a plurality of kinds of precharge voltages in accordance with an ambient temperature. A precharge circuit supplies the precharge voltage to a bit line during the nonaccess of a dynamic memory cell. A sense amplifier amplifies a difference between the voltage of... Agent: Arent Fox PLLC

20070091704 - Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type: In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs... Agent: Slater & Matsil LLP

20070091705 - Semiconductor storage device: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM... Agent: Sughrue Mion, PLLC

20070091706 - Memory redundancy programming: A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes... Agent: Williams, Morgan & Amerson

20070091707 - Semiconductor memory device, operational processing device and storage system: A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.... Agent: Buchanan, Ingersoll & Rooney PC

20070091708 - Semiconductor storage device: A semiconductor storage device has a simple control circuit that is added to a general one-port RAM. Taking a port-A clock signal as the reference, the control circuit generates a select signal that selects a port A during the period from elapse of a first predetermined time from the reference... Agent: Nixon Peabody, LLP

20070091709 - Dram semiconductor memory device with increased reading accuracy: A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a sense amplifier and are connected in each case to a further memory cell. The gates of the... Agent: Edell, Shapiro & Finnan, LLC

20070091710 - Clock circuit for semiconductor memories: A circuit and method for producing a read clock signal in a semiconductor memory device from an input clock signal to ensure that the read access time does not exceed the clock cycle time. One of a plurality of delay amounts is selected to be imposed on the input clock... Agent: Edell, Shapiro & Finnan, LLC

20070091712 - Clocking architecture using a bi-directional reference clock: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a... Agent: Blakely Sokoloff Taylor & Zafman

20070091711 - Method of transferring signals between a memory device and a memory controller: Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are transferred with a first rate and command signals and/or address signals are transferred with a second rate lower than a first... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070091713 - Onboard data storage and method: A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes advantage of the memory access pattern to simplify address processing circuit to realize savings in power and silicon area. Because random... Agent: Macpherson Kwok Chen & Heid LLP

20070091714 - Synchronous semiconductor memory device: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or... Agent: Mcdermott Will & Emery LLP

20070091715 - Semiconductor memory device: An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding... Agent: Arent Fox PLLC

20070086227 - Error protected ternary content-addressable memories and lookup operations performed thereon: Ternary content-addressable memory (TCAM) entries are disclosed for use in performing error-protected lookup operations by allowing an error budget of u deviations in values stored in each entry. Each TCAM entry is configured to identify a hit condition (else a miss condition) with an input lookup word if its stored... Agent: The Law Office Of Kirk D. Williams

20070086228 - Memory modules and memory systems having the same: A memory module includes a port configured to receive write data and command/address signals and multiple memory devices. The multiple memory devices include a first set of the memory devices, each memory device of the first set coupled to the port, and a second set of the memory devices, each... Agent: Marger Johnson & Mccollom, P.C.

20070086229 - Semiconductor integrated circuit: A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line.... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070086231 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device includes a plurality of memory cells connected serially between a bit line and a sensing line, a first switching unit configured to selectively connect the memory cells to the bit line in response to a first selecting signal, and a second switching unit configured to... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070086230 - Nonvolatile latch circuit and system on chip with the same: A nonvolatile ferroelectric memory device includes a bottom word line, an insulating layer formed on the bottom word line, a bit line including a floating channel region formed on the insulating layer, a tunnel oxide film formed on the floating channel region, a ferroelectric layer formed on the tunnel oxide... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070086232 - Ring oscillator row circuit for evaluating memory cell performance: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070086234 - Magnetic memory: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070086233 - Method for reducing word line current in magnetoresistive random access memory and structure thereof: The method for reducing word line currents in magnetoresistive random access memory (MRAM) includes disposing the MRAM bit between a pair of word lines according to a magnetic field strength is increased when a distance between a magnetic section and its corresponding word line is decreased.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070086235 - Phase-change memory device and method of fabricating the same: A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at... Agent: Volentine Francos, & Whitt PLLC

20070086236 - Mram memory cell having a weak intrinsic anisotropic storage layer and method of producing the same: An MRAM memory cell has a layer system of circular-disk-shaped layers. The memory cell includes two magnetic layers separated by a nonmagnetic intermediate layer. The first magnetic layer or reference layer exhibits hard-magnetic behavior. The second magnetic layer or storage layer exhibits soft-magnetic behavior. Information is stored by the magnetization... Agent: Edell, Shapiro & Finnan, LLC

20070086237 - Shape memory device: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070086241 - Evaluation circuit and evaluation method for the assessment of memory cell states: An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first... Agent: Slater & Matsil LLP

20070086240 - Measuring circuit and reading method for memory cells: An electronic circuit arrangement includes at least one memory element in which at least two electrical quantities can be stored. A switching unit is electrically connected to the memory element and has at least one first circuit path and a second circuit path. A storage unit has a first partial... Agent: Slater & Matsil LLP

20070086239 - Probabilistic error correction in multi-bit-per-cell flash memory: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention,... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070086242 - Data storage: A data storage includes a part of functioning for, when data reading operation is carried out on a storage part storing data for a case where the data storage is handled in a predetermined manner, causing predetermined data different from target data to be read out instead of the target... Agent: Staas & Halsey LLP

20070086243 - Nor-nand flash memory device with interleaved mat access: In a NOR-NAND flash memory device, data bits may be alternately selected from first and second mats. A selected wordline in a mat may be kept active until completing a read operation for data bits of more than one memory cells coupled to the selected wordline.... Agent: Marger Johnson & Mccollom, P.C.

20070086244 - Data restoration in case of page-programming failure: The present invention discloses systems and methods for restoring data in flash memory after an operational failure. The method includes: setting bits of a data buffer in accordance with the data; programming a plurality of memory cells in accordance with the data buffer; and upon failure of the programming step,... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070086245 - Nonvolatile semiconductor storage apparatus and method of driving the same: A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses present in the memory cell at the same time are set... Agent: Mcdermott Will & Emery LLP

20070086246 - Non-volatile semiconductor storage apparatus: A non-volatile semiconductor storage apparatus includes a memory cell array-including at least one memory cell unit in which multiple electrically rewritable non-volatile memory cells are serially connected, multiple control gate lines connecting to a control terminal for the multiple memory cells, a bit line connecting to the memory cell unit,... Agent: Rader Fishman & Grauer PLLC

20070086247 - Method for controlled programming of non-volatile memory exhibiting bit line coupling: The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to... Agent: Vierra Magen/sandisk Corporation

20070086238 - Semiconductor memory device and electronic apparatus: In the semiconductor storage device, in a read operation, a bit line charging/discharging section 101 performs discharge of bit lines of a memory cell array 100, and a counter counts discharge periods over which the potentials of bit lines come to a specified potential, based on a comparison result of... Agent: Birch Stewart Kolasch & Birch

20070086248 - Method and apparatus for a dual power supply to embedded non-volatile memory: A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high voltage level, and to select one... Agent: Sierra Patent Group, Ltd.

20070086249 - Memory device having internal voltage supply providing improved power efficiency during active mode of memory operation: A internal voltage generator in a semiconductor memory device has a first and second internal voltage generators. The first internal voltage generator outputs a first signal having a first voltage level to internal circuits of the memory device during an active mode of the memory device operation. The second internal... Agent: Ladas & Parry LLP

20070086250 - Measure control delay and method having latching circuit integral with delay circuit: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070086251 - Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling: The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to... Agent: Vierra Magen/sandisk Corporation

20070086252 - Semiconductor memory device: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell... Agent: Mills & Onello LLP

20070086254 - Integrated circuits with interchangeable connectors: Techniques for interchanging positions of external terminals of an integrated circuit chip are disclosed. According to one aspect of the present invention, a chip comprises at least a pair of external terminals for communicating with other components or circuits, an internal circuit and an interchangeable unit coupled between the external... Agent: Silicon Valley Patent Agency

20070086253 - Scanned memory testing of multi-port memory arrays: A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC

20070086255 - Memory device with a plurality of reference cells on a bit line: In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070086256 - Optical memory with embedded optical recording medium: An optical memory includes a substrate and an optical recording layer embedded in a part of the substrate. At least an upper area of the substrate where the optical recording layer is embedded is transparent, and the optical recording layer has a size to read out data recorded in the... Agent: Stein, Mcewen & Bui, LLP

20070086257 - Tamper response system for integrated circuits: A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit... Agent: Honeywell International Inc.

20070086259 - Apparatus and method for controlling active period of semiconductor memory apparatus: A circuit for controlling an active period of semiconductor memory apparatus includes: an active controller that generates active control signals for determining active periods of two or more individual banks according to whether a refresh operation is performed; and an active signal generator that generates an active signal for each... Agent: Venable LLP

20070086258 - Directed auto-refresh for a dynamic random access memory: A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070086261 - Directed auto-refresh for a dynamic random access memory: A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a row address counter configured to provide a row address for selecting a row of memory cells for a directed auto-refresh, and a bank address counter... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070086262 - Integrated circuit chip with connectivity partitioning: A semiconductor integrated circuit (IC) chip includes at least one core logic module located in a central area of the chip and having a core input/output (I/O) and a plurality of I/O pads disposed on a periphery of the chip. Narrow logic blocks including buffers and delay elements separate the... Agent: Freescale Semiconductor, Inc. Law Department

20070086260 - Method of storing transformed units of data in a memory system having fixed sized storage blocks: A change in the amount of data to be stored that results from various encoding, compression, encryption or other data transformation algorithms, is handled by individually identifying distinct units of the transformed data and storing such units in physical succession within storage blocks of a memory system such as flash... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070086263 - Clock reset address decoder for block memory: In one embodiment of the invention, an address decoder for decoding a word-line address to energize a word line in a block of computer memory. Instead of relying on a distinct enable signal, a clock signal provides a reset function and an enable function to the address decoder. In one... Agent: Mendelsohn And Associates, P.C.

20070086264 - High-voltage generation circuits and nonvolatile semiconductor memory device with improved high-voltage efficiency and methods of operating: A power-voltage driver circuit includes a first MOS transistor configured to turn a second MOS transistor off when a high-voltage generator provides a high voltage output. Related methods are also disclosed.... Agent: Myers Bigel Sibley & Sajovec

20070086265 - Semiconductor storage device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, a plurality of word lines connected to the memory cells, a row decoder including a plurality of decode sections and configured to receive first and second address signals... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070086266 - Directed auto-refresh for a dynamic random access memory: A memory includes a row address latch. The row address latch includes a first stage configured to latch a row address for a memory read or write operation, and a second stage configured to latch a row address for a memory bank auto-refresh. The row address latch provides the row... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070086269 - Clock control circuit and semiconductor memory device including the same and input operation method of semiconductor memory device: The present invention relates to a clock control circuit that can reduce power consumption in the input operation of an address signal and control signals and semiconductor memory device including the same, and an input operation method of the semiconductor memory device. The clock control circuit accordance to the present... Agent: Mayer, Brown, Rowe & Maw LLP

20070086267 - Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration: A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a first output clock signal that is synchronized with a first input clock signal and adjusts a second adjustable delay circuit to provide a... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070086268 - Memory controller with staggered request signal output: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in... Agent: Shemwell Mahamedi LLP

20070081373 - Cam circuit and output method thereof: A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where... Agent: Mcdermott Will & Emery LLP

20070081376 - Memory module and memory system: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other... Agent: Katten Muchin Rosenman LLP

20070081374 - Semiconductor memory device and electronic apparatus: A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal,... Agent: Harness, Dickey & Pierce, P.L.C

20070081375 - Semiconductor storage device: A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside... Agent: Mcdermott Will & Emery LLP

20070081377 - Method and circuit for reading fuse cells in a nonvolatile memory during power-up: A method and circuit are described for ensuring a properly operational power-up read of fuse cells in a nonvolatile memory by selecting predefined data for loading in a portion of a fuse memory and matching the reading of the predefined data during power-up with the predefined data, thereby indicating a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070081378 - Leakage power management with ndr isolation devices: A method and system for minimizing sub-threshold leakage in a logic block is disclosed An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the... Agent: Silicon Valley Patent Group LLP

20070081379 - Write assist for latch and memory circuits: One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a... Agent: Texas Instruments Incorporated

20070081380 - Semiconductor integrated circuit: An object of the present invention is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. The present invention is configured as follows. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells... Agent: Miles & Stockbridge PC

20070081382 - Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell: The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first... Agent: Edell, Shapiro & Finnan, LLC

20070081381 - Programmable magnetic memory device fp-mram: A memory device has an information plane (32) for storing data bits in a magnetic state of an electro-magnetic material at an array of bit locations (31). The device further has an array of electro-magnetic sensor elements (51) that are aligned with the bit locations. The information plane (32) is... Agent: Philips Intellectual Property & Standards

20070081383 - Bit line selection transistor layout structure: A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit... Agent: Baker & Mckenzie LLP Patent Department

20070081384 - Self-boosting system for flash memory cells: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070081385 - [method for managing memory blocks in flash memory]: The present invention discloses a method for managing memory blocks in a flash memory. The method is first to calculate the total number of good blocks and total number of bad blocks in the flash memory, and then all the good blocks and the bad blocks will be evenly allocated... Agent: Phison Electronics Corporation

20070081386 - Methods, circuits and computer program products for updating data in non-volatile memories: A method of updating data, which is stored in each page in a non-volatile memory with a multi-plane structure, using an external buffer, is provided. In the method, source data that will not be updated in a page in each plane of the non-volatile memory is moved to the external... Agent: Myers Bigel Sibley & Sajovec

20070081387 - Two-bits per cell not-and-gate (nand) nitride trap memory: A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070081388 - Program method of flash memory device: A method for programming a non-volatile memory device includes applying a first dummy voltage to a Multi-Level Cell (MLC). A first program voltage is applied to the MLC to program the MLC, the first program voltage being applied to the MLC after the first dummy voltage has been applied to... Agent: Townsend And Townsend And Crew, LLP

20070081389 - Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation: Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070081390 - Systems and methods for programming a memory device: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming.... Agent: Baker & Mckenzie LLP Patent Department

20070081391 - Flash memory device and voltage generating circuit for the same: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein... Agent: Volentine Francos, & Whitt PLLC

20070081392 - Flash memory device and voltage generating circuit for the same: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators... Agent: Volentine Francos, & Whitt PLLC

20070081394 - Method of operating non-volatile memory: A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage... Agent: J.c. Patents, Inc.

20070081393 - Multi-operation mode nonvolatile memory: Disclosed are various embodiments that program a memory array with different carrier movement processes. In one application, memory cells are programmed with a particular carrier movement process depending on the pattern of data usage, such as code flash and data flash. In another application, memory cells are programmed with a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070081395 - Semiconductor memory device having low power consumption type column decoder and read operation method thereof: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder... Agent: Mayer, Brown, Rowe & Maw LLP

20070081397 - Data output multiplexer: A data output multiplexer for multiplexing and transferring data of a data input/output (I/O) line includes a first latch unit coupled to the data I/O line to latch the data of the data I/O line, a transmission gate unit to transfer an output of the first latch unit in response... Agent: Blakely Sokoloff Taylor & Zafman

20070081398 - Semiconductor memory device and transmission/reception system provided with the same: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a... Agent: Mcdermott Will & Emery LLP

20070081396 - System and method for multi-use efuse macro: A system and method for a multi-use eFuse macro is presented. A device includes multiplexers and selection logic that allow eFuse latches to store auxiliary data in addition to programming electronic fuses. The multiplexers and selection logic are coupled to the inputs and outputs of the eFuse latches, and are... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20070081399 - Data delivery apparatus and data delivery method: A data delivery apparatus including a storage adapted to store limited-access data which associates user data for specifying a user, with data, access to which is permitted or limited to the user; a function determination unit adapted to determine whether a destination device to which the limited-access data is to... Agent: Fitzpatrick Cella Harper & Scinto

20070081400 - Control selection circuit and method for a semiconductor device: A control selection circuit for a semiconductor device including a pulse generation circuit to delay a first pulse signal by a predetermined delay time to generate a second pulse signal, a frequency information generation circuit to generate a selection signal in response to the second pulse signal, the selection signal... Agent: Marger Johnson & Mccollom, P.C.

20070081401 - Apparatus for controlling flash memory and method thereof: An apparatus for controlling a flash memory and the method thereof are disclosed. The flash memory includes a plurality of blocks which are divided into a plurality of storage blocks and a plurality of spare blocks. The apparatus includes a bad block mapping table and a controller. When a data... Agent: J C Patents, Inc.

20070081402 - Repair circuit of semiconductor memory device: An embodiment of the present invention relates to a repair circuit of a semiconductor memory device. The repair circuit includes an address counter that sequentially generates a first column address signal and a second column address signal in response to a write enable signal or a read enable signal, a... Agent: Mayer, Brown, Rowe & Maw LLP

20070081403 - Semiconductor memory device: A second roll call test mode is added in addition to a first roll call test mode for checking use/nonuse of a redundancy circuit. A semiconductor memory device is capable of confirming program states of an enable fuse and each address fuse by providing with a logic circuit which blocks... Agent: Young & Thompson

20070081405 - Low power memory control circuits and methods: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the... Agent: John P. O'banion O'banion & Ritchey LLP

20070081404 - Semiconductor device: A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting... Agent: Marshall, Gerstein & Borun LLP

20070081406 - Apparatus and method for providing a reprogrammable electrically programmable fuse: An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070081408 - Multi-chip semiconductor memory device having internal power supply voltage generation circuit for decreasing current consumption: A multi-chip semiconductor memory device may comprise of a plurality of memory chips sharing a predetermined chip enable signal. Each of the plurality of memory chips may comprise of an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage... Agent: Volentine Francos, & Whitt PLLC

20070081407 - Semiconductor memory: Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control... Agent: Arent Fox PLLC

20070081409 - Reduced bitline leakage current: A method for reducing power in an SRAM is achieved by applying a first voltage to all bitlines of a section of the SRAM in standby operation and applying a second voltage to all the bitlines of a section of the SRAM in normal operation. The first voltage is not... Agent: Hewlett Packard Company

20070081411 - Memory block reallocation in a flash memory device: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070081410 - Wafer level i/o test and repair enabled by i/o layer: A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing... Agent: Whitham, Curtis & Christofferson, P.C.

20070081412 - Apparatus and method for controlling dual port memory in a mobile communication terminal with multi processors: Provided are an apparatus and method for preventing a dual port memory full in a mobile communication terminal with multi processors. The apparatus includes an auxiliary processor having a buffer and storing data in the dual port memory, a main processor having a memory processing module and a buffer and... Agent: Dilworth & Barrese, LLP

20070081413 - Address path circuit with row redundant scheme: An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one... Agent: Marshall, Gerstein & Borun LLP

20070081414 - System and method of on-circuit asynchronous communication, between synchronous subcircuits: The system for on-circuit asynchronous communication, between synchronous subcircuits, includes a first synchronous subcircuit regulated by a first clock frequency, which sends requests to a second synchronous subcircut regulated by a second clock frequency. The first subcircuit transmits data to the second subcircuit through a first mesochronous unidirectional communication link,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070076460 - Trapping bubbles of conducting matter in magnetic fields: Free suspension of matter comprising granular materials, liquids or plasmas, is of considerable interest in studying properties under controlled physical conditions. We describe a method for trapping bubbles of conductive matter in circularly polarized magnetic fields. In the preferred embodiments, the bubble assumes the topology of a torus or a... Agent: Maurice H.p.m. Van Putten

20070076461 - Bitcell layout: Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070076462 - Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells: A method for operating a semiconductor memory (M) comprising a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first... Agent: Slater & Matsil LLP

20070076463 - Dual gate oxide one time programmable (otp) antifuse cell: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is... Agent: Blakely Sokoloff Taylor & Zafman

20070076465 - Erase method to reduce erase time and to prevent over-erase: An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a... Agent: Hogan & Hartson L.L.P.

20070076464 - Memory device and method for operating a memory device: A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n)... Agent: Slater & Matsil LLP

20070076466 - Multiple-clock controlled logic signal generating circuit: A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two... Agent: Edwards & Angell, LLP

20070076468 - Asymmetric six transistor sram random access memory cell: A random access memory cell includes a pair of complementary bit lines, a bistable circuit including first and second complementary read/write terminals, and two storage nodes. The first storage node is provided by a first nMos transistor and a first pMos transistor, and the second storage node is provided by... Agent: Jenkens & Gilchrist, PC

20070076467 - Semiconductor memory device: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the... Agent: Miles & Stockbridge PC

20070076470 - Magnetic random access memory device and sensing method thereof: A magnetic random access memory (MRAM) device includes sense lines, a selector, a reading circuit and a writing circuit. Each sense line is coupled to one or more MRAM cells. The selector is used to select one of the sense lines to allow a read or write operation. The reading... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070076469 - Magnetoresistive effect element and magnetic memory device: The magnetoresistive effect element comprises a pinned magnetic layer 16 having a multilayered synthetic antiferromagnet (SAF) structure, a nonmagnetic spacer layer 18 formed on the pinned magnetic layer 16, a free magnetic layer 20 formed on the nonmagnetic spacer layer 18 and formed of a single ferromagnetic layer, a nonmagnetic... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070076471 - Storage element and memory: A storage element includes a storage layer which holds information based on a magnetization state of a magnetic body, an upper pinned magnetic layer disposed above the storage layer with an upper intermediate layer therebetween, and a lower pinned magnetic layer disposed below the storage layer with a lower intermediate... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070076472 - Thin film magnetic memory device writing data with bidirectional current: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets... Agent: Mcdermott Will & Emery LLP

20070076476 - Method and system for regulating a program voltage value during multilevel memory device programming: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage... Agent: Sawyer Law Group LLP

20070076474 - Semiconductor storage device: A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in synchronization with an internal clock; and... Agent: Mcdermott Will & Emery LLP

20070076473 - Step voltage generator: A technique includes selectively coupling a regulator to storage elements to store voltages in the storage elements. In response to an operation to read data from a multilevel cell, a word line is selectively coupled to the storage elements to generate a time sequence of voltages on the word line.... Agent: Trop Pruner & Hu, PC

20070076475 - System and method for executing binary images: A system that determines where a particular XIP component is stored on a medium and loads the component into RAM for execution, providing the ability to demand page specific components at will from storage media, frees up working RAM on memory constrained devices. A Binary File System uses a generic... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070076477 - Sonos type two-bit finfet flash memory cell: A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the... Agent: Slater & Matsil, L.L.P.

20070076480 - Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the... Agent: Saile Ackerman LLC

20070076479 - Multiple independent serial link memory: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070076478 - System and method of memory block management: The disclosure is directed to a method of managing data storage. The method includes detecting an unusable memory block. The unusable memory block is in a set of user accessible memory blocks of a memory device. The memory device includes the set of user accessible memory blocks, a set of... Agent: Toler Schaffer, LLP

20070076481 - Multimode focal plane array with electrically isolated commons for independent sub-array biasing: In a multimode FPA, all of the FPA's conducting layers including all of the absorbing layers are patterned to form electrically isolated commons for at least two, and in some instances all of the photodetector sub-arrays, to support independent mode biasing of the photodetectors. Because the commons are electrically isolated,... Agent: Koppel, Patrick & Heybl

20070076482 - Nonvolatile semiconductor memory device and manufacturing method thereof: A nonvolatile semiconductor memory device includes a gate electrode provided on a channel region of a semiconductor layer and a floating gate provided on a back side of the semiconductor layer with a first insulating layer interposed therebetween.... Agent: Oliff & Berridge, PLC

20070076483 - Band-gap voltage reference circuit: A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through the first and second reference circuit blocks respectively, an amplifier having non-inverting and inverting inputs responsive to the voltages developed by the first and second reference circuit blocks... Agent: Texas Instruments Incorporated

20070076484 - Read operation for semiconductor memory devices: Disclosed is a method of performing a read operation in a NAND/RAM semiconductor memory device. The semiconductor memory device comprises a NAND flash memory device having a memory cell array and a page buffer, and a data RAM outputting data in response to a clock signal received from a host.... Agent: Volentine Francos, & Whitt PLLC

20070076488 - Non-volatile memory device capable of changing increment of program voltage according to mode of operation: A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is... Agent: Marger Johnson & Mccollom, P.C.

20070076486 - Phase change memory device and method of forming the same: A PRAM and method of forming the same are disclosed. In various embodiments, the PRAM includes a lower insulation layer formed on a semiconductor substrate, a phase change material pattern formed on the lower insulation layer and a heating electrode contacting the phase change material pattern. The heating electrode can... Agent: Volentine Francos, & Whitt PLLC

20070076485 - Self-aligned non-volatile memory cell and process for fabrication: Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of... Agent: Parsons Hsue & De Runtz LLP

20070076487 - Semiconductor integrated circuit device: A semiconductor integrated circuit device has data rewritable nonvolatile memory cells which are formed on a semiconductor chip and in which data of three or more values can be stored. The nonvolatile memory cell has two or more write levels and two or more write threshold voltages are used. The... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070076489 - Word line voltage boosting circuit and a memory array incorporating same: A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070076490 - Nonvolatile semiconductor storage device: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070076491 - Multibit memory cell: Provided are a method, system and device for storing multiple bits into a multibit memory cell. In the illustrated embodiment, each multibit memory cell is a “quadbit” cell capable of storing 4 bits which are read out on four bit lines of the cell in response to activation of a... Agent: Konrad Raynes & Victor, LLP. Attn: Int77

20070076492 - Storage device and control method thereof: A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during... Agent: Wagner, Murabito & Hao LLP

20070076493 - Circuit for generating data strobe signal of semiconductor memory device: A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency... Agent: Heller Ehrman LLP

20070076494 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a memory cell section containing memory cells, bit lines connected to one end of the memory cell section, and a data circuit connected to the bit lines to temporarily store one of write data and read data with respect to the memory cell. Each... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070076495 - Wafer-level burn-in test method, wafer-level burn-in test apparatus and semiconductor memory device: A wafer-level burn-in test for a write operation to memory cells is disclosed. The memory cells are associated with a column switch transistor having a gate. In accordance with the method, a voltage level supplied for the gate is changed in correspondence with a level written into the memory cells.... Agent: Mcdermott Will & Emery LLP

20070076496 - Image display device and driving method thereof: An image display device including a plurality of data lines for transmitting data currents which correspond to images and a plurality of scan lines for transmitting select signals. A plurality of pixel circuits coupled to the data lines and the scan lines are used to display the images which correspond... Agent: Christie, Parker & Hale, LLP

20070076497 - Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same: A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal,... Agent: Volentine Francos, & Whitt PLLC

20070076498 - Controlling circuit for automatically adjusting clock frequency of a central processing unit: A controlling circuit for automatically adjusting clock frequency of a CPU is provided. The controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a voltage signal; a voltage amplifying circuit for amplifying the voltage signal; a multi-stage switching circuit for converting the amplified... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070076500 - Semiconductor memory device: A semiconductor memory device is capable of resolving a problem of operational efficiency difference that can occur due to a loading difference on a supplying line while receiving a driving voltage of a unit bit line sense amplifier supplied from a certain part. The memory device includes a plurality of... Agent: Mcdermott Will & Emery LLP

20070076501 - Semiconductor memory device and driving method thereof: A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used... Agent: Mcdermott Will & Emery LLP

20070076499 - Semiconductor storage device and electronic equipment: A semiconductor storage device has a memory cell array composed of a plurality of arrayed memory cells, word lines, bit lines, a bit line charging and discharging circuit, and a readout section. Each memory cell has two storage regions in vicinity of opposite ends of a channel region, first and... Agent: Birch Stewart Kolasch & Birch

20070076503 - Circuitry and methods for efficient fifo memory: Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070076502 - Daisy chain cascading devices: A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data,... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070076504 - Memory device having low vpp current consumption: Embodiments of the invention provide a method of performing a self refresh of memory cells in a memory device. In one embodiment, the memory device includes a first group of cell blocks and a second group of cell blocks and each cell block of the first group shares at least... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070076505 - Power line communications device and method of use: A method of providing communications over a medium voltage power line having a plurality of segments is provided. In one embodiment, the method comprises the steps of determining a first amplification for data signals, receiving a first data signal from a first segment of the power line, amplifying said first... Agent: Capital Legal Group, LLC

20070076506 - Power supply system having standby power: A power supply system for selectively supplying a main power and a standby power to a computer is provided. The power supply system comprises a transistor including a first terminal, a second terminal and a third terminal. The first terminal being coupled to a motherboard power source, the second terminal... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070076507 - Storage device employing a flash memory: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070076511 - Method and apparatus for mapping memory: A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method maps the memories such that continuous even-numbered lines are written in different banks of different memories,... Agent: Sughrue Mion, PLLC

20070076510 - Method of reducing disturbs in non-volatile memory: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word... Agent: Parsons Hsue & De Runtz LLP

20070076508 - Semiconductor memory chip: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having... Agent: Edell, Shapiro & Finnan, LLC

20070076509 - Three-dimensional mask-programmable read-only memory: The present invention discloses several improved three-dimensional mask-programmable read-only memories (3D-MPROM), including interleaved self-aligned pillar-shaped 3D-MPROM (ISP 3D-MPROM), separate self-aligned pillar-shaped 3D-MPROM (SSP 3D-MPROM), interleaved self-aligned natural-junction 3D-MPROM (ISN 3D-MPROM) and separate self-aligned natural-junction 3D-MPROM (SSN 3D-MPROM). They have larger memory capacity and lower manufacturing cost.... Agent: Guobiao Zhang

20070076513 - Decoder for memory device with loading capacitor: A decoder system for a memory device includes a high voltage pump, a high voltage switch, and a loading capacitor. The high voltage pump generates a boost voltage, and the high voltage switch couples one of the boost voltage or a low voltage to a line of the memory device.... Agent: Law Office Of Monica H Choi

20070076514 - Lus semiconductor and application circuit: The Lus Semiconductor in this invention is characterized by replacing the static shielding diode (SSD) of traditional Power Metal Oxide Semiconductor Field Effect Transistors (Power MOSFETs) with polarity reversed (comparing with traditional SSD) SSD, Schottky Diode, or Zener Diode, or face-to-face or back-to-back coupled Schottky Diodes, Zener Diodes, Fast Diodes,... Agent: Lu, Chao-cheng

20070076515 - Memory and driving method of the same: According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit... Agent: Eric Robinson

20070076512 - Three transistor wordline decoder: A word line decode circuit may include three devices, a first p-type transistor, a first n-type transistor and a second n-type transistor together with a shared (with other word line decoding circuits) p-type transistor make up a “distributed” NOR gate. The first p-type transistor and the first n-type transistor may... Agent: Blakely Sokoloff Taylor & Zafman

20070076516 - Semiconductor device with latency counter: A latency counter of a semiconductor device comprises a single cyclic signal generator and a command delay circuit. The single cyclic signal generator cyclically produces 0-th to n-th base signals based on an internal clock signal. The command delay circuit comprises 0-th to n-th latch elements and latches an internal... Agent: Mcdermott Will & Emery LLP

20070076517 - Semiconductor memory device and module for high frequency operation: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of... Agent: Mills & Onello LLP

20070076518 - Microcomputer: A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with... Agent: Posz Law Group, PLC