Static information storage and retrieval inventions 03/07

20070070669 - Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a... Agent: Deniro/rambus

20070070670 - Semiconductor memory device: A semiconductor memory device includes a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks according to a first data output mode; a second group of local input/output lines to transfer data stored... Agent: Mcdermott Will & Emery LLP

20070070671 - Integrated semiconductor memory with transmission of data via a data interface: During a read access to a memory cell array of an integrated semiconductor memory device, data of a data word is fed to a data generator circuit which can be operated in the operating modes of noninverted and bitwise inverted transmission of data. The data generator circuit generates a control... Agent: Edell, Shapiro & Finnan, LLC

20070070672 - Semiconductor device and driving method thereof: A semiconductor device includes a first internal voltage generator generating an internal voltage using a first external power supply voltage in a normal mode; a second internal voltage generator generating the internal voltage using a second external power supply voltage supplied through a no connection (N/C) pin in a test... Agent: Blakely Sokoloff Taylor & Zafman

20070070673 - Power delivery and power management of many-core processors: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide... Agent: Blakely Sokoloff Taylor & Zafman

20070070674 - Semiconductor memory device: Provided are semiconductor design technologies, especially a bit line sense amplifier array of a semiconductor memory device. The semiconductor memory device includes a plurality of unit bit line sense amplifiers, a pull-up power line which is a power line of the plurality of unit bit line sense amplifiers, a single... Agent: Blakely Sokoloff Taylor & Zafman

20070070675 - Semiconductor memory device: An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read signal, a... Agent: Mcdermott Will & Emery LLP

20070070677 - Internal signal generator for use in semiconductor memory device: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command.... Agent: Mcdermott Will & Emery LLP

20070070676 - Pipe latch device of semiconductor memory device: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when... Agent: Mcdermott Will & Emery LLP

20070070678 - Semiconductor storage device: The present invention is a semiconductor storage device comprising a plurality of memory cells disposed in an array in the row and column directions and a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in... Agent: Arent Fox PLLC

20070070679 - Circuitry for a programmable element: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part... Agent: Trask Britt, P.C./ Micron Technology

20070070680 - Electric circuit: As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a... Agent: Fish & Richardson P.C.

20070070681 - Memory device comprising an array of resistive memory cells: A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and the bit... Agent: Morrison & Foerster LLP

20070070682 - Storage device and semiconductor device: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070070684 - Dynamic therapy bed system: A therapeutic mattress system is provided for treating a patient. The mattress system has a mattress having plurality of vertically elongated cells extending from a base layer that are arranged in a row and column grid arrangement. Each cell has a sidewall and a patient support surface extending therefrom, and... Agent: Wallenstein & Wagner, Ltd.

20070070683 - Random access memory including first and second voltage sources: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070070685 - Atomic probes and media for high density data storage: A device in accordance with embodiments of the present invention comprises an atomic probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the atomic probe can include a core having a conductive coating. The core can comprise an insulating or conducting material, and the coating... Agent: Fliesler Meyer LLP

20070070687 - Adjustable current source for an mram circuit: A word current source for a magnetoresistive random access memory (MRAM) circuit includes an n-channel transistor including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the MRAM circuit. A positive supply voltage is coupled to the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070686 - Method and device for performing active field compensation during programming of a magnetoresistive memory device: The present invention provides an array (20) og magnetoresistive memory elements (10). The array (20) comprises: means for applying a current or voltage for generating a programming magnetic field at a selected magnetoresistive memory element (10s), a magnetic field sensor unit (50) for measuring an external magnetic field in the... Agent: Philips Intellectual Property & Standards

20070070688 - Word driver and decode design methodology in mram circuit: A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070689 - Magneto-resistive element: A magneto-resistive element according to an aspect of the present invention includes a free layer whose magnetized state changes and a pinned layer whose magnetized state is fixed. The free layer comprises first and second ferromagnetic layers and a non-magnetic layer which is arranged between the first and second ferromagnetic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070690 - Method for using a multi-use memory cell and memory array: A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least... Agent: Brinks Hofer Gilson & Lione

20070070691 - Apparatus and method for simultaneous testing of multiple orthogonal frequency division multiplexed transmitters with single vector signal analyzer: Apparatus and method for testing signals from two or more OFDM transmitters simultaneously with a single VSA.... Agent: Vedder Price Kaufman & Kammholz

20070070692 - Compressed event counting technique and application to a flash memory system: A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based... Agent: Parsons Hsue & De Runtz LLP

20070070693 - Semiconductor integrated circuit device including storage unit having nonvolatile and volatile memory element sections: A semiconductor integrated circuit device includes a storage unit arranged on a semiconductor chip to store a plurality of data, and a plurality of registers provided on the semiconductor chip, the registers storing the data transferred from the storage unit, respectively. The storage unit has a nonvolatile memory element section... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070694 - Storage device employing a flash memory: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070070695 - Circuit and method of generating internal supply voltage in semiconductor memory device: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first... Agent: Mills & Onello LLP

20070070696 - Drift compensation in a flash memory: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070070697 - Semiconductor memory device: A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the second... Agent: Mcdermott Will & Emery LLP

20070070698 - Compact virtual ground diffusion programmable rom array architecture, system and method: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with each pair of adjacent columns,... Agent: Shreen K. Danamraj Danamraj & Youst, P.C.

20070070699 - Nonvolatile semiconductor memory device having dummy bit line with multiple sections: A nonvolatile semiconductor memory device is disclosed having a dummy bit line formed from a plurality of dummy bit line sections. The particular dummy bit line sections are variously connected a common source line and a P-type well region.... Agent: Volentine Francos, & Whitt PLLC

20070070700 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled... Agent: Leffert Jay & Polglaze, P.A.

20070070701 - Nand flash memory device and programming method: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating... Agent: Volentine Francos, & Whitt PLLC

20070070702 - Nonvolatile semiconductor memory device which stores multi-value information: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit)... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070070703 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070070704 - Nonvolatile memory with program while program verify: A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070070706 - Bit line control circuit for semiconductor memory device: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for... Agent: Mcdermott Will & Emery LLP

20070070707 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of... Agent: Mcdermott Will & Emery LLP

20070070705 - Semiconductor memory device for driving a word line: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of... Agent: Mcdermott Will & Emery LLP

20070070708 - Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070711 - Driving signal generator for bit line sense amplifier driver: A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving signal generating... Agent: Mcdermott Will & Emery LLP

20070070710 - Nonvolatile semiconductor memory device and data writing method: The present invention aims to eliminate variations in threshold voltage subsequent to the writing of data in an EPROM. When a parasitic resistance between the source of a memory cell (M00) of an even-numbered row and its corresponding bit line (BL0) is larger by a resistance (R00) than a parasitic... Agent: Nixon Peabody, LLP

20070070709 - Write circuit of memory device: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the... Agent: Mcdermott Will & Emery LLP

20070070712 - Data input/output multiplexer of semiconductor device: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer... Agent: Mcdermott Will & Emery LLP

20070070713 - Data output device of semiconductor memory device: There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a second address information signal to directly output or inversely output the received signal as a third address information signal in response to a first... Agent: Mcdermott Will & Emery LLP

20070070716 - Semiconductor integrated circuit device: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable... Agent: Miles & Stockbridge PC

20070070715 - Semiconductor memory device: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An... Agent: Mcdermott Will & Emery LLP

20070070714 - Synchronous semiconductor memory device: A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signal in response to internal command signals; a delay unit for delaying... Agent: Mcdermott Will & Emery LLP

20070070717 - Semiconductor memory device for adjusting impedance of data output driver: An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output... Agent: Mcdermott Will & Emery LLP

20070070719 - Core voltage generator and method for generating core voltage in semiconductor memory device: Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to... Agent: Mcdermott Will & Emery LLP

20070070721 - Device for controlling internal voltage: A device controls internal voltage. Increased reliability of a semiconductor memory device is obtained by increasing or decreasing a level of internal reference voltage according to change of the device. Fuse ROMs generate fuse signals having different levels according to a cutting condition of each fuse. A bit counter performs... Agent: Mcdermott Will & Emery LLP

20070070723 - Internal voltage generator for semiconductor memory device: An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the... Agent: Mcdermott Will & Emery LLP

20070070725 - Internal voltage supplying device: An internal voltage supplying device includes a level sensing means for sensing a level of a high voltage with respect to a core voltage, an oscillation signal generating means for generating an oscillation signal controlled by the level sensing means, and a pumping means for pumping charges during an activation... Agent: Blakely Sokoloff Taylor & Zafman

20070070724 - Semiconductor memory device for controlling reservoir capacitor: A semiconductor memory device is provided. Especially, there is disclosed a technique capable of increasing a net die by employing a cell capacitor as a reservoir capacitor according to a set mode. The semiconductor memory device of the present invention uses the cell capacitor as the reservoir capacitor in a... Agent: Blakely Sokoloff Taylor & Zafman

20070070722 - Voltage generator: A voltage generator reduces a stand by current in a stand by or a self-refresh mode and shortens a response time in an active mode by selectively driving a control transistor of a final driver. A core voltage control unit provides a power voltage. Pull-up and pull-down driving signals are... Agent: Mcdermott Will & Emery LLP

20070070720 - Voltage generator for use in semiconductor device: A voltage generator for use in a semiconductor memory device includes an output voltage controller for generating a bias voltage using a reference voltage of which a voltage level is half of a core voltage level. Pull-up/pull-down driving signals are output by generating a voltage which is higher or lower... Agent: Mcdermott Will & Emery LLP

20070070718 - Voltage regulator for memory device: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply... Agent: Rabin & Berdo, PC

20070070726 - Over-driving circuit in semiconductor memory device: A semiconductor memory over-driving scheme for a semiconductor memory device makes it possible to secure a high-speed sensing operation of a memory sense amplifier, regardless of a change of a power supply voltage. Over-driving efficiency is improved by controlling the discharging time and the drivability using different sized the drivers... Agent: Mcdermott Will & Emery LLP

20070070727 - Semiconductor memory device including reset control circuit: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a... Agent: Mcdermott Will & Emery LLP

20070070728 - Semiconductor memory with reset function: A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate... Agent: Townsend And Townsend And Crew, LLP

20070070733 - Circuit and method for outputting aligned strobe signal and parallel data signal: An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying... Agent: Madson & Austin Gateway Tower West

20070070731 - Delay locked operation in semiconductor memory device: A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling... Agent: Mcdermott Will & Emery LLP

20070070729 - High access speed flash controller: A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write (R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and... Agent: Bruce H. Troxell

20070070732 - Method for generating adjustable mram timing signals: A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit generates a timing control signal. A number of variable timing circuits are each coupled to receive at least... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070730 - Semiconductor memory device: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an... Agent: Mcdermott Will & Emery LLP

20070070737 - Method and auxiliary device for creating and checking the circuit diagram for a circuit which is to be integrated: Method and apparatus for creating and checking a circuit diagram for a circuit which is to be integrated. On the basis of this circuit diagram, a layout for the circuit which is to be integrated is designed. Both when designing the circuit diagram and in a layout description extracted from... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070738 - Motor and controller inversion: commanding torque to position-controlled robot: Systems and methods are presented that cancel the dynamics of a motor and a joint controller in the presence of communication time delays, measurement noise, and controller parameter uncertainties inherent in a robot system. A cancellation system includes feedback of the measured output Ê of a controller block C. A... Agent: Honda/fenwick

20070070734 - Reconfigurable memory block redundancy to repair defective input/output lines: An embodiment of the present invention is a technique to provide a reconfigurable repair circuit in a memory device. A table structure contains a plurality of entries, each entry having a defective address word and a redundant address word. The redundant address word corresponds to a redundant block and is... Agent: Blakely Sokoloff Taylor & Zafman

20070070735 - Redundant circuit for semiconductor memory device: A redundant circuit includes a plurality of bit line sense amp arrays including different local data buses, sharing one bit line sense amp, and being formed adjacently to each other, an input/output fuse unit for outputting a selection signal with different logic state depending on whether or not a first... Agent: Blakely Sokoloff Taylor & Zafman

20070070736 - Semiconductor device: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces... Agent: Young & Thompson

20070070743 - Multi-port semiconductor memory device: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the... Agent: Blakely Sokoloff Taylor & Zafman

20070070739 - Semiconductor memory device and its test method: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070070741 - Semiconductor memory device for measuring internal voltage: A semiconductor memory device includes a plurality of internal voltage measuring units, each for driving data input from a memory bank to output the data when a test signal is deactivated, and outputting a corresponding one of internal voltages used in the semiconductor memory device when the test signal is... Agent: Mcdermott Will & Emery LLP

20070070740 - Semiconductor memory device having data-compress test mode: A semiconductor memory device performs a data-compress test under the same conditions as a normal mode. The semiconductor memory device includes a cell bank for including plural memory cell units for data storage and a data sense amplifying block for sensing and amplifying plural output data of the cell bank... Agent: Mcdermott Will & Emery LLP

20070070742 - Test mode controller: A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate... Agent: Mcdermott Will & Emery LLP

20070070744 - Fast pre-charge circuit and method of providing same for memory devices: A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector distance from driver of the integrated circuit memory device, and the... Agent: Baker & Mckenzie LLP Patent Department

20070070748 - Method for discharging and equalizing sense lines to accelerate correct mram operation: A method and apparatus for discharging and equalizing sense lines embedded in a magnetoresistive random access memory integrated circuit (MRAM IC) includes using a current source connected to a current source node. A sense line is connected to the current source node. A bit decode element is coupled to turn... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070745 - Redundant wordline deactivation scheme: Embodiments of the present inventions provide a method and apparatus for reducing power consumption of a memory device. In one embodiment, the method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070747 - Semiconductor memory device: A semiconductor memory device includes an equalizing signal generation circuit comprising a clamping circuit that clamps a voltage level less than the voltage level of a high voltage level by being controlled by the high voltage, and an equalizing signal driver receiving an output signal of the equalizing signal generation... Agent: Mcdermott Will & Emery LLP

20070070749 - Semiconductor memory device and data read and write method thereof: A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting... Agent: Marger Johnson & Mccollom, P.C.

20070070746 - Semiconductor memory device and its driving method: A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD, when the equalization signal is repeated by a repeater. In order to improve bit line precharging performance... Agent: Mcdermott Will & Emery LLP

20070070750 - Apparatus and method for data transmission, and apparatus and method for driving image display device using the same: An apparatus and method for data transmission and an apparatus and method for driving an image display device using the same are disclosed, in which transition of data is minimized during data transmission to minimize electromagnetic interference. The apparatus for data transmission includes a data modulator modulating low bits excluding... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070070751 - Bit line sense amplifier control circuit: A bit line sense amplifier control circuit comprises a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal... Agent: Heller Ehrman LLP

20070070752 - Semiconductor memory device and method for driving bit line sense amplifier thereof: A semiconductor memory device includes an amplifying unit for amplifying a voltage difference between a bit line pair; a power supply driver for supplying a power to the amplifying unit in response to a second driving signal; a control unit for generating a first driving signal of the power supply... Agent: Blakely Sokoloff Taylor & Zafman

20070070753 - Single transistor sensing and double transistor sensing for flash memory: A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070070754 - Low equalized sense-amp for twin cell drams: Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline. The method includes precharging the first bitline and the second bitline to a low voltage. A wordline... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070757 - Over-driving circuit for semiconductor memory device: An over-driving circuit for a semiconductor memory device is capable of rapidly securing a sensing operation of a bit line sense amplifier regardless of a level change of a power supply voltage. Timings are adjustsed for supplying an over-driving voltage and for discharging based on a level change of a... Agent: Mcdermott Will & Emery LLP

20070070759 - Scalable embedded dram array: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070070755 - Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof: A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper... Agent: Mcdermott Will & Emery LLP

20070070756 - Semiconductor memory device sharing sense amplifier: A semiconductor memory device contains a reduced number of signal lines of a core area required for data access. The semiconductor memory device includes a sense amplifier for selectively sensing and amplifying data signals on a first pair of bit lines arranged at a first cell array and a second... Agent: Mcdermott Will & Emery LLP

20070070758 - Semiconductor memory with sense amplifier and switch: A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070070761 - Internal voltage generator: An internal voltage generator includes: an internal voltage driving unit for supplying an internal voltage corresponding to a reference voltage maintaining a predetermined voltage level regardless of a temperature variation; and a temperature compensation current sinking unit for sinking a current generated by an internal voltage in response to a... Agent: Mcdermott Will & Emery LLP

20070070760 - Memory device with self refresh cycle control function: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent... Agent: Mcdermott Will & Emery LLP

20070070762 - Method and apparatus for optimizing data buffering: A method for storing data in a first buffer and a second buffer is disclosed. The method includes: sequentially storing an incoming data into the first buffer and the second buffer according to a first threshold; transferring data stored in the second buffer to the first buffer when an amount... Agent: North America Intellectual Property Corporation

20070070766 - High voltage generator and semiconductor memory device: A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power... Agent: Mcdermott Will & Emery LLP

20070070764 - Memory: This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion... Agent: Mcdermott Will & Emery LLP

20070070767 - Multi-port memory device having self-refresh mode: The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh... Agent: Blakely Sokoloff Taylor & Zafman

20070070768 - Refresh control circuit and method for multi-bank structure dram: A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal... Agent: Blakely Sokoloff Taylor & Zafman

20070070763 - Semiconductor memory device: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and... Agent: Blakely Sokoloff Taylor & Zafman

20070070765 - Semiconductor memory device with advanced refresh control: A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank;... Agent: Mcdermott Will & Emery LLP

20070070769 - Circuit and method for controlling a standby voltage level of a memory: A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of... Agent: Ibm Microelectronics Intellectual Property Law

20070070771 - Method and a control unit for controlling a power level: A method and a control unit for controlling a power level being drawn from a power source (26). Based on a determined rate of change of a measured voltage (1) an estimated remaining runtime is calculated. The estimated remaining runtime represents a time where specific run criteria will no longer... Agent: Mccormick, Paulding & Huber LLP

20070070770 - Method and system of operating mode detection: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes... Agent: Toler Schaffer, LLP

20070070772 - Voltage generator for peripheral circuit: A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of... Agent: Blakely Sokoloff Taylor & Zafman

20070070773 - Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same: A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage,... Agent: Texas Instruments Incorporated

20070070775 - Device for driving global signal: A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the... Agent: Mcdermott Will & Emery LLP

20070070774 - Memory device having latch for charging or discharging data input/output line: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is... Agent: Mcdermott Will & Emery LLP

20070070776 - Semiconductor memory device: A semiconductor device reduces unnecessary operating current while an internal row/column address is generated. The semiconductor memory device includes an address input unit for transferring an address signal inputinput from an external device; an internal column address generating unit for receiving the transferred address signal to generate an internal column... Agent: Mcdermott Will & Emery LLP

20070070777 - Semiconductor memory device: A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second... Agent: Mcdermott Will & Emery LLP

20070070778 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent: Blakely Sokoloff Taylor & Zafman

20070070779 - Multi-port semiconductor memory: A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is... Agent: Nixon Peabody, LLP

20070070781 - Internal address generator: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate... Agent: Mcdermott Will & Emery LLP

20070070782 - Memory device input buffer, related memory device, controller and system: Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the... Agent: Volentine Francos, & Whitt PLLC

20070070780 - Output driving device: An output driving device includes a pull-up driver for pull-up driving an output node in response to a pull-up control signal; a pull-down driver for pull-down driving the output node in response to a pull-down control signal; and a first n-type metal oxide semiconductor (NMOS) transistor for pull-up driving the... Agent: Mcdermott Will & Emery LLP

20070070783 - Semiconductor memory device: A semiconductor memory device includes a cell matrix having a number of cells, a multiplicity of column decoders for selectively activating the cells in response to code signals containing column address information for the cells, wherein each column decoder contains a pre-driving unit for providing a state output signal transiting... Agent: Blakely Sokoloff Taylor & Zafman

20070070785 - Semiconductor memory device: A semiconductor memory device changes a pulse width of an over driving signal according to operation modes, which differ by a degree of accessing memory banks during an over driving operation. An over driver supplies an RTO line of the bit line sense amplifier with an over driving voltage in... Agent: Mcdermott Will & Emery LLP

20070070786 - Semiconductor storage device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, a plurality of word lines connected to the memory cells, a row decoder including a plurality of decode sections and configured to receive first and second address signals... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070784 - Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device: A semiconductor memory device includes a bit line sense amplifying block that senses and amplifies bit line data. A first driving block drives a pull up power line of the bit line sense amplifying block using a voltage applied to a normal driving voltage terminal. A second driving block drives... Agent: Mcdermott Will & Emery LLP

20070070787 - Semiconductor memory device: A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an address buffer control signal in response to... Agent: Mcdermott Will & Emery LLP

20070070788 - Apparatus and method for dynamically controlling data transfer in memory device: Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070794 - Arbitration for memory device with commands: A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or... Agent: Law Office Of Monica H Choi

20070070791 - Clock control device: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in... Agent: Mcdermott Will & Emery LLP

20070070797 - Data transmission device in semiconductor memory device: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through... Agent: Mcdermott Will & Emery LLP

20070070798 - Internal address generator for use in semiconductor memory device: An internal address generator for use in a semiconductor memory device includes an address detector, a drive pulse generator, and a delay unit. The address detector generates a comparison signal by comparing a first address currently input with a second address previously input. The drive pulse generator generates a drive... Agent: Mcdermott Will & Emery LLP

20070070799 - Memory and method of controlling access to memory: The present invention provides a memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access... Agent: Ibm Microelectronics Intellectual Property Law

20070070789 - Module apparatus and method for controlling auto on/off of clock for saving power: A module apparatus and method for saving power by automatically controlling an ON/OFF state of a clock is provided. The module apparatus comprises a core performing special functions and storing operation information, and a clock controller applying or not applying an external clock input according to the operation information transmitted... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070070795 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent: Blakely Sokoloff Taylor & Zafman

20070070790 - Output control device: An output controller includes a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe... Agent: Mcdermott Will & Emery LLP

20070070792 - Output controller with test unit: There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an initial synchronizing unit for outputting a first output enable signal when a read CAS signal is activated; a plurality... Agent: Mcdermott Will & Emery LLP

20070070793 - Semiconductor memory device: A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing... Agent: Blakely Sokoloff Taylor & Zafman

20070070796 - Semiconductor memory device having data-compress test mode: A semiconductor memory device includes a plurality of column circuit units selectively operated with a burst length set in a mode register set. A plurality of column control blocks control column access to unit cells, each block activated by each of plural column control signals, and a column control signal... Agent: Mcdermott Will & Emery LLP

20070070800 - Externally worn vasovagal syncope detection device: A device is worn adjacent to tissue of a patient to detect vasovagal syncope (VVS). The device includes a photoplethysmographic sensor that measures a plethysmographic signal through tissue, and a processor that derives an indicator of an autonomous nervous system (ANS) activity from the plethysmographic signal and estimates a probability... Agent: Medtronic, Inc.

20070064461 - Low power content addressable memory: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare... Agent: Shemwell Gregory & Courtney LLP

20070064462 - Memory system and data transmission method: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory... Agent: Scully Scott Murphy & Presser, PC

20070064463 - Rom load balancing for bit lines: An apparatus and method to improve a cycle time of a Read Only Memory (ROM). Loading of each bit line is controlled such that no bit line has less than a specified loading fraction of a loading of a maximally loaded bit line. No additional space or additional circuitry is... Agent: Robert R. Williams IBM Corporation

20070064464 - High performance flash memory device capable of high density data storage: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits... Agent: Harrity & Snyder, L.L.P.

20070064466 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled... Agent: Leffert Jay & Polglaze, P.A.

20070064465 - Rom storing information by using pair of memory cells: Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070064467 - Read-only memory: An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the... Agent: Seed Intellectual Property Law Group PLLC

20070064468 - Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device: Provided are a charge trap memory device including a substrate and a gate structure including a charge trapping layer formed of a composite of nanoparticles, and a method of manufacturing the charge trap memory device.... Agent: Cantor Colburn, LLP

20070064469 - Display device and driving method of the same: A first capacitor obtains a gate-source voltage of a first transistor in accordance with a programming current flowing through the first transistor, and a second capacitor obtains a threshold voltage of a second transistor. Then, the electric charges held in the first capacitor and the second capacitor are capacitively coupled.... Agent: Fish & Richardson P.C.

20070064470 - Semiconductor device: A semiconductor device according to an embodiment of the present invention includes: an oscillating circuit including a plurality of logic circuits connected in series; and an error detecting circuit receiving output signals of at least two of the plurality of logic circuits, and suspending an operation of the oscillating circuit... Agent: Young & Thompson

20070064471 - Magnetostatic communication: A system for providing communication of information by modulating a magnetostatic field with a magnetostatic transmitter that modulates said magnetostatic field to contain the information and detecting the information in the modulated field at a distance with a magnetostatic detector that detects the modulated magnetic field containing the information.... Agent: Eddie E. Scott Assistant Laboratory Counsel

20070064472 - Nonvolatile semiconductor memory device performing data writing in a toggle manner: A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between... Agent: Mcdermott Will & Emery LLP

20070064473 - Phase change memory device and program method thereof: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval.... Agent: Volentine Francos, & Whitt PLLC

20070064474 - Resistance variable memory element with threshold device and method of forming the same: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon... Agent: Dickstein Shapiro LLP

20070064475 - Simulating circuit for magnetic tunnel junction device: A simulating circuit for simulating the operation of a magnetic tunnel junction (MTJ) device having at least a free layer and a fixed layer is provided. The simulating circuit includes a closed switch loop for simulating the magnetization of the free layer and the fixed layer, thus for simulating the... Agent: Rabin & Berdo, PC

20070064476 - Semicoductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output... Agent: Rossi, Kimms & Mcdowell LLP.

20070064478 - Nanotube- and nanocrystal-based non-volatile memory: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write... Agent: Intel/blakely

20070064477 - System for remote data sharing: Embodiments of the present invention encompass a remote data sharing system that can support connectivity between any JDBC-compliant data source and any Java-compatible remote client, which system can be implemented without programming. The system can comprise at least one JDBC-compliant data source, a gateway running inside a Java-compliant web container,... Agent: Battelle Memorial Institute Attn:IPServices, K1-53

20070064483 - Clock synchronized non-volatile memory device: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070064480 - Multi-bit flash memory device having improved program rate: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain... Agent: Harrity & Snyder, L.L.P.

20070064482 - Semiconductor integrated circuit device: A semiconductor integrated circuit device has a first memory cell group including a plurality of rewritable nonvolatile memory cells arranged on a semiconductor chip and a second memory cell group including a plurality of rewritable nonvolatile memory cells arranged on the semiconductor chip. Setting of the write threshold voltage of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070064481 - Storage device: Memory cell can stores a multi-valued value more than a binary value in a single storage cell by changing the amount of electric charge to be stored. Data logic stores storage data, each digit of which is binary as a binary value in each memory cell for each digit. Furthermore,... Agent: Staas & Halsey LLP

20070064484 - Non-volatile programmable memory cell for programmable logic array: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor,... Agent: Sierra Patent Group, Ltd.

20070064485 - Page buffer flash memory device and programming method using the same: A page buffer of a flash memory device is configured to program two pages in a single programming operation. The page buffer of the flash memory device includes a first bit line selection unit, a second bit line selection unit, a separation unit, a precharge unit, a first register, and... Agent: Townsend And Townsend And Crew, LLP

20070064486 - Display device and fabricating method thereof: A display device that lends itself to a cost-effective and simplified manufacturing process is presented. The display device includes an insulating substrate; a common voltage line formed on the insulating substrate; an insulating layer provided on the common voltage line; and a contact hole extending through the insulating layer to... Agent: Macpherson Kwok Chen & Heid LLP

20070064487 - Program method and circuit of non-volatile memory: A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to... Agent: J C Patents, Inc.

20070064488 - Eeprom and method of driving the same: An EEPROM (Electrically Erasable and Programmable Read Only Memory) has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a common gate electrode and constitute one memory cell. A program operation and an erase operation are carried out by using... Agent: Sughrue Mion, PLLC

20070064479 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell, and a reference cell including a same structure as the memory cell. A detecting circuit detects a timing when a voltage of a reference bit line connected with the reference cell becomes lower than or equal to a setting voltage, and... Agent: Sughrue Mion, PLLC

20070064489 - Method and circuitry to generate a reference current for reading a memory cell, and device implementing same: There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state... Agent: Neil A. Steinberg

20070064490 - Non-volatile semiconductor memory device: A memory cell array comprises a group of memory cells capable of retaining two-bit information. The memory cell has a pair of transistors having charge storage regions and arranged along a row direction of the memory cell array. Word lines are provided between the memory cells adjacent to each other... Agent: Mcdermott Will & Emery LLP

20070064492 - Optimizing the speed of an fc-al switch domain in a data storage network: In a fibre channel, arbitrated loop (FC-AL) network environment, an operating speed of devices within a switch domain within the network is optimized. The FC-AL switch domain is isolated from an attached storage controller, and a first signal is transmitted to each of a plurality of storage devices within the... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070064491 - Radio resource management: The present invention relates to radio resource management in a wireless communication system. Specifically, the present invention relates to a method and apparatus for a method of managing downlink radio resources for a multi-sector base transceiver site in which power can be shared between the sectors in which radio resource... Agent: Motorola, Inc.

20070064494 - Embedded eeprom array techniques for higher density: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to... Agent: Texas Instruments Incorporated

20070064493 - Flash memory programming using an indication bit to interpret state: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current... Agent: Harrity & Snyder, L.L.P.

20070064495 - Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070064496 - Cell string of flash memory device and method of manufacturing the same: Disclosed herein are a cell string of a flash memory device and a method of manufacturing the same. The cell string of a flash memory device includes a plurality of memory cells connected to a single bit line and arranged with first distance between the memory cells, and a source... Agent: Marshall, Gerstein & Borun LLP

20070064498 - Flash memory devices including multiple dummy cell array regions: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main... Agent: Myers Bigel Sibley & Sajovec

20070064497 - Non-volatile one time programmable memory: A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in... Agent: Leffert Jay & Polglaze, P.A.

20070064499 - Semiconductor memory device and method for writing data into the semiconductor memory device: A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory cell (100a) is coupled to the wordline (40), one of the second bitlines (22a) and the first bitline (21a).... Agent: Slater & Matsil LLP

20070064502 - Digital-to-analog conversion device: A digital-to-analog (D/A) conversion device including a data-latch unit, a D/A conversion unit and a gain amplifier is provided. Wherein, the amplitude of the supply voltages for the reference voltage of the D/A conversion unit is not greater than that of the data-latch unit so that the switches in a... Agent: J.c. Patents, Inc.

20070064504 - Dual reference input receiver of semiconductor device and method of receiving input data signal: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input... Agent: Volentine Francos, & Whitt PLLC

20070064500 - Integrated circuit with dynamic memory allocation: An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting... Agent: Philips Intellectual Property & Standards

20070064503 - Internal voltage generation control circuit and internal voltage generation circuit using the same: An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command... Agent: Marshall, Gerstein & Borun LLP

20070064501 - Wavelength-maintaining optical signal regenerator: The invention relates to a wavelength-maintaining purely optical signal regenerator to which degraded optical signals with a high data rate are transmitted and regenerated without opto-electronic or wavelength conversion using compact, non-linear semiconductor components with low power consumption. Said regenerator comprises: an optical clock regeneration stage (2) which generates synchronized... Agent: Law Offices Of Karl Hormann

20070064506 - Small signal threshold and proportional gain distributed digital communications: An apparatus for gain distribution in a system comprising a plurality of distributed antennas and a total system dynamic range is disclosed. The apparatus includes means for sensing a signal level at each of the plurality of distributed antennas, means for comparing at least one of the plurality of signal... Agent: Fogg And Associates, LLC

20070064505 - Test mode method and apparatus for internal memory timing signals: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals... Agent: Edell, Shapiro & Finnan, LLC

20070064508 - Fuse trimming circuit: The present invention provides a fuse trimming circuit that can reduce power consumption and improve operation reliability. The fuse trimming circuit is provided with a fuse-state determining circuit, which determines whether a fuse element is in an unblown state or in a blown state by comparing drain currents flowing to... Agent: Nixon Peabody, LLP

20070064507 - Semiconductor memory device having bit registering layer and method of driving the same: The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a... Agent: Harness, Dickey & Pierce, P.L.C

20070064510 - Method and apparatus for evaluating and optimizing a signaling system: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference.... Agent: Hunton & Williams LLP/rambus Inc. Intellectual Property Department

20070064509 - Method and device for transmission of adjustment information for data interface drivers for a ram module: A method and a device are described for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller, with control bits for adjustment purposes being sent during an adjustment mode by the controller as a... Agent: Morrison & Foerster LLP

20070064511 - Semiconductor device: It is an object of the present invention to provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. A semiconductor device of the invention has three factors of a data holding unit, a precharge... Agent: Fish & Richardson P.C.

20070064512 - Flash memory device and associated recharge method: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage... Agent: Volentine Francos, & Whitt PLLC

20070064513 - Semiconductor apparatus: In a semiconductor apparatus, a power supply voltage generating circuit (21) and an internal circuit (22) using a power supply voltage generated by the power supply voltage generating circuit are supplied with different internal circuit preset signals (PRESET 1 and PRESET 2) optimized for the power supply voltage generating circuit... Agent: Mcginn Intellectual Property Law Group, PLLC

20070064514 - Control unit and portable terminal: A control unit capable of reliably preventing loss of data also when losing power during data processing is obtained. This control unit comprises a volatile memory temporarily storing data used in the control unit and a nonvolatile memory holding data of the volatile memory, for writing the same data as... Agent: Mcdermott Will & Emery LLP

20070064516 - Methods and apparatus for lancet actuation: A lancet driver is provided wherein the driver exerts a driving force on a lancet during a lancing cycle and is used on a tissue site. The driver comprises of a drive force generator for advancing the lancet along a path into the tissue site, and a sensor configured to... Agent: Heller Ehrman LLP

20070064515 - Reconfigurable input/output in hierarchical memory link: A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected... Agent: Mills & Onello LLP

20070064517 - Output control signal generating circuit: An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used... Agent: Mcdermott Will & Emery LLP

20070058407 - Semiconductor memory device: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of... Agent: Buchanan, Ingersoll & Rooney PC

20070058410 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: Stattler Johansen & Adeli LLP

20070058409 - Semiconductor memory arrangement with branched control and address bus: A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address... Agent: Edell, Shapiro & Finnan, LLC

20070058408 - Semiconductor memory array with serial control/address bus: A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and... Agent: Edell, Shapiro & Finnan, LLC

20070058411 - Semiconductor storage device including electrical fuse module: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101),... Agent: Steptoe & Johnson LLP

20070058412 - System and method for improved low flow medical pump delivery: A medical pump with an improved continuity low flow delivery system and method for use with a pumping chamber, for example in a cassette, is disclosed. The pump includes a pump drive for exerting a force on the pumping chamber and a sensor for sensing the force/pressure exerted by the... Agent: Brian R. Woodworth

20070058413 - Active float for the dummy bit lines in feram: Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity.... Agent: Texas Instruments Incorporated

20070058416 - Inspection method for semiconductor memory: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070058415 - Method for depositing ferroelectric thin films using a mixed oxidant gas: Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the... Agent: Harness, Dickey & Pierce, P.L.C

20070058414 - Semiconductor memory device having error checking and correcting circuit: A semiconductor memory device includes a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level, a bit line which reads the binary data from the memory cell,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070058417 - Method for writing data into a memory cell of a conductive bridging random access memory, memory circuit and cbram memory circuit: The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit. The embodiments of the prevent invention provide a method and a memory... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070058418 - Semiconductor memory device having memory cells requiring no refresh operation: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second)... Agent: Mcdermott Will & Emery LLP

20070058421 - Global bit line restore timing scheme and circuit: A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset... Agent: International Business Machines Corporation

20070058419 - Memory cell having p-type pass device: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response... Agent: Blakely Sokoloff Taylor & Zafman

20070058420 - Power supply voltage control circuit: A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070058422 - Programmable magnetic memory device: A memory device has an information plane (32) for storing data bits in a magnetic state of an electro-magnetic material at an array of bit locations (31). The device further has an array of electro-magnetic sensor elements (51) that are aligned with the bit locations. The information plane (32) is... Agent: Philips Intellectual Property & Standards

20070058424 - Semiconductor memory device: A semiconductor memory device includes a write line, at least three first data-writing circuits which are connected to the write line, and memory cells which include a magnetoresistive element, are connected electrically and/or magnetically to the write line, and are arranged between the first data-writing circuits.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070058423 - Upside-down magnetoresistive random access memory: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070058425 - Phase change random access memory device having variable drive voltage circuit: A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines,... Agent: Volentine Francos, & Whitt PLLC

20070058426 - Semiconductor memory device comprising one or more injecting bilayer electrodes: The subject invention provides systems and methods that facilitate formation of semiconductor memory devices comprising memory cells with one or more injecting bilayer electrodes. Memory arrays generally comprise bit cells that have two discrete components; a memory element and a selection element, such as, for example, a diode. The invention... Agent: Amin, Turocy & Calvin, LLP

20070058427 - Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same: A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions... Agent: Neil A. Steinberg Suite 1150

20070058428 - Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells: A NAND-type nonvolatile semiconductor memory device comprising a cell string that comprises a dummy cell interposed between and connected in series to a string selection transistor and a nonvolatile memory cell is provided. The NAND-type nonvolatile semiconductor memory device further comprises a dummy word line driver adapted to activate a... Agent: Volentine Francos, & Whitt PLLC

20070058429 - Nonvolatile semiconductor memory device: The nonvolatile semiconductor memory device according the this invention has a plurality of memory cells arranged in a matrix form and each having a floating gate; at least one first diode connected between drains of said plurality of memory cells and a ground terminal; and at least one second diode... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070058430 - Integrated circuit with a data memory protected against uv erasure: A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method comprises the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the... Agent: Seed Intellectual Property Law Group PLLC

20070058432 - non-volatile semiconductor memory device: A non-volatile semiconductor memory device of the present invention is provided. The non-volatile semiconductor memory device of the present invention comprises a memory cell array having a plurality of electrically-programmable memory cells, said memory cell storing 2 bits, a lower bit and an upper bit are addressed by a lower... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070058431 - Method of operating flash memory chips: A method of operating a packaged flash memory module includes applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module; applying a... Agent: Townsend And Townsend And Crew, LLP

20070058433 - Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070058434 - Nonvolatile memory cell programming: A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively... Agent: Freescale Semiconductor, Inc. Law Department

20070058436 - Efficient verification for coarse/fine programming of non volatile memory: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory... Agent: Vierra Magen/sandisk Corporation

20070058435 - Read and erase verify methods and circuits suitable for low voltage non-volatile memories: In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070058438 - Differential amplifier circuit and semiconductor device: A differential amplifier circuit in which an input offset voltage is very small. The differential amplifier circuit includes an input-stage differential amplifier section and a cascode-connected single-ended output section connected to the input-stage differential amplifier section. The input-stage differential amplifier section has a folded-cascode-connection. An inverted signal and non-inverted signal... Agent: Mcginn Intellectual Property Law Group, PLLC

20070058437 - Interface circuit: An interface circuit comprises at least one supply input and at least one data input with a protective circuit coupled between the at least one supply input and the at least one data input. A power supply circuit is coupled to the at least one supply input. The interface circuit... Agent: Maginot, Moore & Beck Chase Tower

20070058439 - Systems and methods for a reference circuit in a dual bit flash memory device: A dual bit flash device comprising a core cell array, each cell of the core cell array is configured to store two bits of data, and a single reference array, each cell of the single reference array comprising a first bit programmed to a low threshold voltage and a second... Agent: Baker & Mckenzie LLP Patent Department

20070058440 - Hole annealing methods of non-volatile memory cells: Hole annealing methods are described after erasure of nitride storage memory cells for compensating trapped holes to minimize the holes from detrapping in order to reduce the amount of threshold voltage from drifting significantly higher. A soft hot electron program is used to selected nitride storage memory cells that have... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070058443 - Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.... Agent: Slater & Matsil LLP

20070058441 - Semiconductor device: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other.... Agent: Miles & Stockbridge PC

20070058442 - Sonos memory with inversion bit-lines: A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the... Agent: Law Office Of Monica H Choi

20070058446 - Erase and program method of flash memory device for increasing program speed of flash memory device: The present invention relates to erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method according to the present invention, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore,... Agent: Marshall, Gerstein & Borun LLP

20070058445 - Method and apparatus for protection from over-erasing nonvolatile memory cells: Methods and apparatuses for protecting charge trapping memory cells from over-erasing in response to an erase command are disclosed.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070058444 - Method and circuit for erasing a non-volatile memory cell: The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element may be located and/or activated across two bit-lines defining... Agent: Tiajoloff & Kelly

20070058448 - Bitline variable methods and circuits for evaluating static memory cell dynamic stability: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070058449 - Semiconductor device and method thereof: A semiconductor device and method thereof. The semiconductor device may include a protection unit receiving an input signal and outputting a switching control signal based on the received input signal, the received input signal indicating an operating mode of a controller and a switching device receiving the switching control signal,... Agent: Harness, Dickey & Pierce, P.L.C

20070058447 - Technique to suppress bitline leakage current: Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070058453 - Apparatus and method for centralized power management: The invention describes a system and method for arranging to provide power to a power monitor device. The disclosure describes the system and method receiving a request for power for at least one device specified by a power monitor device. The disclosure describes receiving at least one proposal from an... Agent: Baker Botts L.L.P.

20070058450 - Limited use data storing device: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.... Agent: Searete LLC Clarence T. Tegreene

20070058451 - Semiconductor memory device, semiconductor integrated circuit system using the same, and control method of semiconductor memory device: The invention relates to a semiconductor memory device and a semiconductor integrated circuit system using the same and a control method of a semiconductor memory device. An object of the invention is to provide a semiconductor memory device which reduces the number of accesses to decrease the burden on a... Agent: Arent Fox PLLC

20070058452 - Voltage glitch detection circuits and methods thereof: Voltage glitch detection circuits and methods thereof. In a first example, the voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data... Agent: Harness, Dickey & Pierce, P.L.C

20070058454 - Input circuit for a memory device, and a memory device and memory system employing the input circuit: In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude... Agent: Harness, Dickey & Pierce, P.L.C

20070058455 - Method and program for converting boundary data into cell inner shape data: A cutting point calculation step defines the cell complex that contains the boundary data, and calculating a cutting point where the boundary data cuts an edge or vertex of the rectangular parallelepiped cell of the cell complex. A cycle formation step classifies the rectangular parallelepiped cells into a boundary cell... Agent: Griffin & Szipl, PC

20070058456 - Integrated circuit arrangement: An integrated circuit arrangement comprises at least one circuit to be controlled and a control logic for controlling the at least one circuit to be controlled. Furthermore, a switch is connected between the circuit to be controlled and the control logic. The switch is adapted to connect the control logic... Agent: Slater & Matsil LLP

20070058457 - Internal voltage generator of semiconductor integrated circuit: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least... Agent: Venable LLP

20070058458 - Low power dissipation voltage generator: A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a source transistor to couple a substrate voltage, Vbb, to an output voltage node. The transistor is selectively activated by a current mirror circuit and... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070058460 - Low power chip select (cs) latency option: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents... Agent: Jones Day

20070058459 - Semiconductor memory device with no latch error: A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal. A control circuit... Agent: Mcginn Intellectual Property Law Group, PLLC

20070058462 - Memory address repair without enable fuses: A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a... Agent: Jones Day

20070058465 - Nand flash memory cell programming: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070058463 - Rescue circuit line, display device having the same and method for manufacturing the same: A display device includes a rescue circuit line structure having a first conductive pattern for interconnecting electrically two circuit elements. The first conductive pattern is formed with an open for electrically disconnecting the circuit elements. A dielectric layer is disposed above the first conductive pattern in such a manner to... Agent: Birch Stewart Kolasch & Birch

20070058461 - Semiconductor device: A semiconductor device has: a memory element which is arranged on a semiconductor substrate and records information therein; a terminal for inputting first voltage for recording the information to the memory element and second voltage lower than the first voltage for reading out the information from the memory element; and... Agent: Fitzpatrick Cella Harper & Scinto

20070058464 - Semiconductor storage device, electronic apparatus, and mode setting method: Disclosed herein is a semiconductor storage device operable in a plurality of operation modes each having a separate maximum current consumption. The device includes: a data communication section configured to be capable of performing data communication in a plurality of communication modes; an attribute information storage section configured to store... Agent: Robert J. Depke Lewis T. Steadman

20070058466 - Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20070058467 - Semiconductor device, electro-optical device, and electronic instrument: A semiconductor device includes first and second signal lines SL1 and SL2 through which signals with the same phase and the same amplitude are transmitted, and third and fourth signal lines SL3 and SL4 through which signals with different phases or different amplitudes are transmitted. The line-to-line distance when the... Agent: Harness, Dickey & Pierce, P.L.C

20070058468 - Shielded bitline architecture for dynamic random access memory (dram) arrays: A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array using a bitline from an adjacent, non-active subarray as a reference for a bitline in an active array.... Agent: Hogan & Hartson LLP

20070058469 - Memory device and method having data path with multiple prefetch i/o configurations: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070058470 - Serial presence detect functionality on memory component: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070058471 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: John Stattler Stattler Johansen & Adeli LLP

20070058473 - Anti-fuse memory circuit: First and second anti-fuse elements are provided for storing 1-bit data. A program voltage generating circuit generates a programming voltage and applies it to the first and second anti-fuse elements. A read voltage generating circuit generates a readout voltage and applies it to the first and second anti-fuse elements. First... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070058472 - Fuse structure for semiconductor device and controlling method thereof: A fuse structure for a semiconductor device including a plurality of fuses, n first control lines, m second control lines, n first switches, and m second switches is described. In the above fuse structure, the fuses are including a first terminal and a second terminal respectively and arranged in (n×m)... Agent: J C Patents, Inc.

20070058474 - Internal voltage generator: An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back bias enable signal and the back bias voltage in response to an activated self refresh signal and a... Agent: Blakely Sokoloff Taylor & Zafman

20070058475 - Storage device employing a flash memory: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070058476 - Semiconductor memory device: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input... Agent: Katten Muchin Rosenman LLP

20070058477 - Accessing apparatus capable of reducing power consumption and accessing method thereof: An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070058478 - Interface circuit: An interface circuit includes: a first synchronizing circuit for synchronizing a signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock; a second synchronizing circuit for synchronizing a signal having a delay less than the predetermined period with... Agent: Young & Thompson

20070058480 - Nand flash memory device with burst read latency function: A NAND flash memory device may include an interface block which receives an external read enable signal to output an internal clock signal during a read operation. The NAND flash memory device may also include a buffer clock controlling circuit which operates in response to a data output enable signal... Agent: Volentine Francos, & Whitt PLLC

20070058479 - Semiconductor integrated circuit device: The present invention provides a semiconductor integrated circuit device provided with an interface circuit, which has realized speeding-up. A first input circuit inputs a data strobe signal therein, and a second input circuit inputs therein data formed in sync with the timing of a change in the data strobe signal.... Agent: Stanley P. Fisher Reed Smith LLP

20070058481 - Mram internal clock pulse generation with an atd circuit and the method thereof: A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended transition detection signal output. The magnetic random access memory has... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070053218 - Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction: A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A... Agent: Volentine Francos, & Whitt Pllc

20070053219 - Micro-machinery memory device: A micro-motor memory device includes at least one rotor having at least one indicator for rotating about an axis; and at least one stator placed adjacent to the rotor for electromagnetically or physically engaging the rotor to rotate the indicator to at least one predetermined angular position for representing stored... Agent: Howard Chen Preston Gates & Ellis LLP

20070053220 - Ferroelectric memory device: An operation switch circuit receives a command specifying operational specifications from a host. An operation control circuit controls the time of voltage application to a plate line based on an output signal from the operation switch circuit, to attain volatile-mode operation in a first memory region and nonvolatile-mode operation in... Agent: Mcdermott Will & Emery LLP

20070053221 - Phase change memory array having equalized resistance: A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first line plus the second line at each one of the memory cells is substantially equal.... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070053222 - Method and apparatus for programming/erasing a non-volatile memory: A non-volatile memory (NVM) that can be optimized for data retention or endurance is divided into portions that are optimized for one or the other or potentially some other storage characteristic. For the portion allotted for data retention, the memory cells are erased to a relatively greater extent. For the... Agent: Freescale Semiconductor, Inc. Law Department

20070053223 - Non-volatile memory devices having l-shaped floating gate electrodes and methods of forming same: A flash EEPROM array includes a first row of EEPROM cells having a first floating gate electrode therein and a second row of EEPROM cells having a second floating gate electrode therein. The first floating gate electrode includes at least one horizontal segment and at least one vertical segment, which... Agent: Myers Bigel Sibley & Sajovec

20070053224 - Method and device for programming cbram memory cells: Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter... Agent: Edell, Shapiro & Finnan, Llc

20070053225 - Structures and methods for enhancing erase uniformity in an nrom array: A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells,... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070053228 - Flash memory device and voltage generating circuit for the same: A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit... Agent: F. Chau & Associates, Llc

20070053227 - High-voltage switch with low output ripple for non-volatile floating-gate memories: A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal.... Agent: Seed Intellectual Property Law Group Pllc

20070053226 - Peripheral voltage generator: Provided is a peripheral voltage generator for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current used in a deep-power down mode and a self refresh mode to thereby enhance operational characteristics. The peripheral voltage generator includes a reference voltage generating unit for... Agent: Mcdermott Will & Emery LLP

20070053229 - Redundancy substitution method, semiconductor memory device and information processing apparatus: A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge... Agent: Arent Fox Pllc

20070053230 - Semiconductor device including fuse and method for testing the same capable of supressing erroneous determination: In a semiconductor device including first and second power supply terminals, a measuring terminal, and at least one trimming detection circuit connected between the measuring terminal and one of the first and second power supply terminals, the trimming detection circuit is constructed by a current supplying element, a series arrangement... Agent: Sughrue Mion, Pllc

20070053231 - Flood mode implementation for continuous bitline local evaluation circuit: A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.

20070053232 - Bitline precharge voltage generator: A bitline precharge voltage generator can generate multiple bitline precharge voltages when bitlines are precharged, thereby providing a stable operation regardless of a core voltage used as a high data voltage of a memory cell. In the bitline precharge voltage generator, a core voltage level detecting unit detects a core... Agent: Mcdermott Will & Emery LLP

20070053233 - Method for checking the block erasing of a memory: A method checks the state of a set of memory cells of a memory comprising memory cells arranged in a memory array, means for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive... Agent: Seed Intellectual Property Law Group Pllc

20070053234 - Semiconductor memory device: A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair; a back bias generating circuit which generates a back bias voltage to be applied to the first NMOS... Agent: Mcdermott Will & Emery LLP

20070053235 - Semiconductor memory device: Pseudo SRAM capable of arbitrating refresh requests with external access requests is provided. An access waiting circuit 20 for generating an access waiting signal /ECP in response to an external access request signal /CE or the like, an access activating circuit 21 for generating an access activating signal /AE in... Agent: Ibm Microelectronics Intellectual Property Law

20070053236 - Fuse resistance read-out circuit: Methods and apparatus for a more precise readout of fuse resistance than a conventional binary readout are provided. For some embodiments, a digital readout of fuse resistance may be obtained by selectively altering an effective reference resistance to which the fuse resistance is compared. For some embodiments, a direct analog... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070047280 - Apparatus and method to store information: A method to store data is disclosed. The method provides a plurality of data storage media, an automated data library comprising one or more data storage devices, a first plurality of storage cells, and a robotic accessor. The method further provides a storage vault comprising a second plurality of storage... Agent: Dale F. Regelman

20070047279 - Middleware method and apparatus and program storage device adapted for linking data sources to software applications: A Middleware Apparatus and associated method and program storage device is functionally an/or operationally interposed between ‘one or more data sources’ and a corresponding ‘one or more applications’. When an application requests data from the data sources, the application transmits a set of ‘data descriptions’ which pertain to the set... Agent: Schlumberger Information Solutions

20070047282 - Method and apparatus for implementing power saving for content addressable memory: A method and apparatus are provided for implementing power saving in a content addressable memory (CAM). A compare array is matched against a key and if a match occurs then logic coupled to the compare array generates a hit signal. A data array includes precharge circuitry and data output latches... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070047281 - Storage element with clear operation and method thereof: A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage... Agent: Freescale Semiconductor, Inc. Law Department

20070047283 - Semiconductor device: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as... Agent: Mcdermott Will & Emery LLP

20070047285 - Layout structure for use in flash memory device: A flash memory device includes a core region, high-voltage pump regions disposed at one side of the core region, and a peripheral control region disposed at one side of the core region and between the high-voltage pump regions.... Agent: Volentine Francos, & Whitt PLLC

20070047284 - Self-identifying stacked die semiconductor components: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070047286 - Semiconductor memory device: A semiconductor memory device comprises plural memory cells MC arranged in a matrix, plural bit lines BL and plural plate line voltage supply lines SCP which are arranged in a row direction, plural sense amplifier circuits SA which are arranged in a column direction and are electrically connected to the... Agent: Wenderoth, Lind & Ponack L.L.P.

20070047287 - Method and apparatus for storing a three-dimensional arrangement of data bits in a solid-state body: A method which serves for writing a three-dimensional arrangement of data bits to a solid-state body comprises the steps of selecting a protein having fluorescence properties that can be altered by means of an optical write signal; providing the solid-state body made from the protein, the protein being present in... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070047290 - Ferroelectric information storage device and method of writing/reading information: An information storage device includes a ferroelectric layer having a first surface and a second surface opposite the first surface. A common electrode layer is formed on the first surface of the ferroelectric layer. At least two conductive track layers separated from each other are positioned on the second surface... Agent: Sughrue Mion, PLLC

20070047288 - Ferroelectric random access memory: A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070047289 - Semiconductor integrated circuit device: A semiconductor integrated circuit device capable of lengthening a life of a FeRAM. A RAM stores the same data as those of the FeRAM in the same address as that of the FeRAM. An FF (flip-flop) section stores validity of the data at each address on the RAM. When data... Agent: Arent Fox PLLC

20070047291 - Integrated memory circuit comprising a resistive memory element and a method for manufacturing such a memory circuit: The present invention relates to an integrated memory circuit for storing information, the memory circuit comprising a memory cell having a memory element with a first contact for connecting to a write/read unit and a second contact for connecting to a reference potential provided by a potential source and a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070047292 - Nonvolatile memory cell: Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between... Agent: Dickstein Shapiro LLP

20070047293 - Dual port gain cell with side and top gated read transistor: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the... Agent: Scully Scott Murphy & Presser, PC

20070047295 - Magnetic memory device and method of fabricating the same: A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed... Agent: F. Chau & Associates, LLC

20070047294 - Oscillating-field assisted spin torque switching of a magnetic tunnel junction memory element: Devices and techniques for applying a resonant action by an applied oscillating magnetic field to a magnetic tunnel junction (MTJ) and an action of an applied DC current across the MTJ to effectuate a switching of the MTJ when writing data to the MTJ.... Agent: Fish & Richardson, PC

20070047296 - Memory device that programs more than two states into memory cell: A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory cell. The second circuit is configured... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070047297 - Resistance variable memory element with threshold device and method of forming the same: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon... Agent: Dickstein Shapiro LLP

20070047298 - Method and apparatus for reducing operation disturbance: A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070047300 - Flash memory device with improved read speed: A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select... Agent: Volentine Francos, & Whitt PLLC

20070047299 - Method for accessing a multilevel nonvolatile memory device of the flash nand type: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary... Agent: Seed Intellectual Property Law Group PLLC

20070047303 - Electrically erasable programmable read-only memory cell transistor and related method: An electrically erasable programmable read-only memory (EEPROM) cell transistor and a method of fabricating the EEPROM cell transistor are provided. The EEPROM cell transistor comprises a semiconductor substrate; a first tunnel oxide layer formed on the semiconductor substrate; and a first floating gate electrode formed on the first tunnel oxide... Agent: Volentine Francos, & Whitt PLLC

20070047301 - Multiple select gate architecture: Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage.... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070047304 - Non-volatile semiconductor memory device and method of manufacturing the same: In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel... Agent: Harness, Dickey & Pierce, P.L.C

20070047302 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a... Agent: Saile Ackerman LLC

20070047305 - Zone boundary adjustments for defects in non-volatile memories: A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend... Agent: Parsons Hsue & De Runtz LLP

20070047306 - Non-volatile memory copy back: Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory controller for data repair... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070047307 - High speed operation method for twin monos metal bit array: The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates... Agent: Stephen B. Ackerman

20070047308 - Memory controller, flash memory system and control method for flash memory: A memory controller receives data to be stored in a flash memory by a host system in synchronism with a clock (external clock) to be a reference for an operation of the host system, and outputs the received data in synchronism with an internal clock of the memory controller. The... Agent: Howard & Howard Attorneys, P.C.

20070047310 - Nand memory device and programming methods: A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070047313 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, a source line coupled to one end of the NAND cell unit, and a bit line coupled to the other end of the NAND cell unit, wherein... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070047312 - Operation of multiple select gate architecture: Methods of operating non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells facilitate mitigation of gate-induced drain leakage and program disturb.... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070047311 - Selective threshold voltage verification and compaction: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20070047309 - Twin monos array for high speed application: The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.... Agent: Stephen B. Ackerman

20070047318 - Nonvolatile semiconductor memory device and programming or erasing method therefor: In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use... Agent: Mcdermott Will & Emery LLP

20070047317 - Nonvolatile semiconductor memory devices: A nonvolatile semiconductor memory device may include a cell array and a program modulation unit. The cell array may further include a plurality of word lines, a plurality of bit lines, a plurality of cell transistors and a plurality of source lines. The plurality of bit lines may intersect the... Agent: Harness, Dickey & Pierce, P.L.C

20070047315 - Program and read trim setting: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polgaze

20070047314 - Programming method for nand eeprom: A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20070047316 - Reading method of a nand-type memory device and nand-type memory device: A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline... Agent: Seed Intellectual Property Law Group PLLC

20070047319 - Scalable flash/nv structures and devices with extended endurance: According to an embodiment of a method for operating a nonvolatile memory device, one or more non-volatile memory cells in one or more arrays are written by applying a voltage across a dielectric to store charge on charge centers in the high K dielectric, and one or more non-volatile memory... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070047320 - Nor flash memory devices in which a program verify operation is performed on selected memory cells and program verify methods associated therewith: A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.... Agent: Myers Bigel Sibley & Sajovec

20070047322 - Circuit for generating step-up voltage in non-volatile memory device: A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response to a clock signal and switches the high voltage transfer switch, a high voltage switching controller, which... Agent: Mayer, Brown, Rowe & Maw LLP

20070047321 - Memory system with two voltage sources: A memory system with two voltage sources comprises a controlling chip which includes a built-in DC/DC converter for transforming low voltage to high voltage, used for transforming 1.8/3.3 voltage to 3.3 voltage. This does not only prevent the phenomenon of voltage drifting but improves the stability of the system.... Agent: Rabin & Berdo, P.C. Suite 500

20070047323 - Storage apparatus and manufacturing method thereof: A method of manufacturing a storage apparatus includes preparing a first substrate on which a plurality of row lines are arranged in parallel, preparing a second substrate on which a plurality of column lines are arranged in parallel, dispensing as a droplet a solution, in which particles are dispersed in... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070047325 - Method and apparatus for discharging a memory cell in a memory device after an erase operation: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the... Agent: Sawyer Law Group LLP

20070047324 - Nand memory device and programming methods: A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines.... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070047326 - Programming memory devices: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070047327 - Erase method for flash memory: A non-volatile memory device and programming process is described that erases blocks of non-volatile memory cells by the application of differing word line erase voltages to selected word lines during an erase cycle. This facilitates for a faster on average erase operation, a tighter erased cell Vt distribution, an increase... Agent: Leffert Jay & Polglaze, P. A. Attn: Andrew C. Walseth

20070047328 - Flash memory device with multiple erase voltage levels: In some embodiments, a string of nonvolatile memory cells may be erased by driving their control gates with erase voltages that may have different levels for different cells. The cells may be divided into two or more groups, and the cells in each group may be driven by the same... Agent: Marger Johnson & Mccollom, P.C.

20070047329 - Configurable flash memory: A flash memory may be reconfigurable so that the memory space arrangement of the flash array may be changed for particular applications. In one embodiment, a command or comment may be received by the flash memory. In response to the command, the flash memory may be reconfigured so that the... Agent: Trop Pruner & Hu, PC

20070047330 - Non-volatile look-up table for an fpga: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC... Agent: Sierra Patent Group, Ltd.

20070047333 - Generation of back-bias voltage with high temperature sensitivity: A level detector within a back-bias voltage generator includes a toggling unit and a temperature detector. The toggling unit causes an enable signal to be activated when an absolute value of a back-bias voltage is less than an absolute value of a monitoring level. The temperature detector controls the toggling... Agent: Law Office Of Monica H Choi

20070047332 - Reference voltage generating circuit and constant voltage circuit: A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of... Agent: Cooper & Dunham, LLP

20070047331 - Semiconductor memory device having a develop reference voltage generator for sense amplifiers: I describe and claim a device and method for generating develop voltage signals. The device includes a sense amplifier to sense a voltage difference between a plurality of bit lines responsive to a develop voltage signal, and a voltage generator to generate the develop voltage signal responsive to a reference... Agent: Marger Johnson & Mccollom, P.C.

20070047334 - Semiconductor memory device having trimmed voltage generator and method of generating trimmed voltage in semiconductor memory device: A semiconductor memory device including a trimmed voltage generator and a method of generating a trimmed voltage in the semiconductor memory device, in which the semiconductor memory device includes a voltage trimming unit, memory cell array, and a trimming current generator. The voltage trimming unit outputs a first trimming current... Agent: F. Chau & Associates, LLC

20070047335 - Method and apparatus for generating temperature compensated read and verify operations in flash memories: Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current having a temperature... Agent: Trask Britt, P.C./ Micron Technology

20070047336 - Semiconductor memory with wordline timing: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070047337 - Interface circuit and semiconductor device: A circuit that enables a loop-back test by adjusting phases of data and strobe signals at the input and output in an interface wherein the phase relationships between the data and the strobe signal for sampling the data are different between the input and output. In order to test a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070047338 - External delayed switch apparatus for cooling fans: An external delayed switch apparatus for cooling fans aims to provide electric power to at least one cooling fan located in a computer to continuously operate to lower temperature when the computer is shut down. The computer has a power supply which includes a standby power system and a main... Agent: Birch Stewart Kolasch & Birch

20070047339 - Memory control device and memory control method thereof: A memory control device and a memory control method are provided to compensate for additional delay subsequent to the change in environmental factors and to permit a smooth writing operation. The memory control device includes a controller that calculates a number of delay cells that are necessary to delay a... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070047340 - Synchronous memory device: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially... Agent: F. Chau & Associates, LLC

20070047343 - Automation of fuse compression for an asic design system: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory.... Agent: Schmeiser, Olsen & Watts

20070047341 - Ferroelectric random access memory: A unit cell is composed of a memory cell transistor and a ferroelectric storage element connected in parallel between a source and a drain of the memory cell transistor. A memory cell block is composed of a plurality of unit cells connected in series. One end of the memory cell... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070047342 - Storage device and control method of storage device: In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in... Agent: Wagner, Murabito & Hao LLP

20070047344 - Hierarchical memory correction system and method: A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a... Agent: Hewlett Packard Company

20070047345 - Semiconductor device, testing and manufacturing methods thereof: In order to easily perform a timing test on a memory interface included in a semiconductor device so as to satisfy a restriction on latency, the present invention provides a semiconductor device with the memory interface including: a clock output terminal that outputs a clock signal associated with an operation... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070047346 - Semiconductor integrated circuit: A semiconductor integrated circuit for intentionally and flexibly changing a monitoring subject bit if debugging is performed during software processing when a status change occurs. A replacement data register and a comparison address register, which are settable from a microprocessor, determine matching of an address input from the microprocessor and... Agent: Freescale Semiconductor, Inc. Law Department

20070047348 - Semiconductor memory device: A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease... Agent: Mcdermott Will & Emery LLP

20070047347 - Semiconductor memory devices and a method thereof: A semiconductor memory device and a method thereof are provided. The example method may include determining whether a currently tested cell is defective and repairing the currently tested cell, if the currently tested cell is determined to be defective, before determining whether a next tested cell is defective. The example... Agent: Harness, Dickey & Pierce, P.L.C

20070047352 - Charge pump: A charge pump is disclosed, comprising a plurality of sub-charge pumps connected in series, each comprising a charging switch module turned on or off according to a charging clock signal and a capacitor connected between the charging switch module and a reference clock signal. The charge pump further comprises at... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070047351 - High-performance memory and related method: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging... Agent: North America Intellectual Property Corporation

20070047349 - Methods and apparatus for low power sram: Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070047350 - Semiconductor memory devices with open bitline architectures and methods of controlling the bitlines of such semiconductor memory devices: Semiconductor memory devices and methods of controlling bitlines of such devices in which bitlines of a memory cell array adjacent to an activated memory cell array are precharged to the same voltage. The semiconductor memory devices may include: a sense amplifier which is connected between a pair of bitlines, consisting... Agent: Myers Bigel Sibley & Sajovec

20070047353 - Flash memory device with reduced erase time: A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage during the erase... Agent: Volentine Francos, & Whitt PLLC

20070047354 - Semiconductor module: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and... Agent: Mcdermott Will & Emery LLP

20070047359 - Flash memory device: A flash memory device (1) includes a cover (10), a metal shield (20) received in the cover (10), a printed circuit board (6) accommodated in the metal shield (20), a cap member (30) for shielding the front the portion of the metal shield (20) and a latching device for interconnecting... Agent: Wei Te Chung Foxconn International, Inc.

20070047355 - Method for detecting a leakage current of a semiconductor memory: A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070047357 - Semiconductor memory device: A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period,... Agent: Harness, Dickey & Pierce, P.L.C

20070047360 - Semiconductor storage device having page copying function: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to... Agent: Frommer Lawrence & Haug

20070047358 - Sensing margin varying circuit and method thereof: A sensing margin varying circuit and method thereof are provided. The example sensing margin varying circuit may control the skew of a ready signal and may include a plurality of semiconductor elements which are connected to a plurality of accelerating transistors positioned on a current path between a node outputting... Agent: Harness, Dickey & Pierce, P.L.C

20070047356 - Wide databus architecture: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070047363 - Memory: A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads and rewrites data from and in the memory cell in... Agent: Mcdermott Will & Emery LLP

20070047362 - Memory control system and memory control circuit: A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit... Agent: Young & Thompson

20070047361 - Semiconductor-memory device and bank refresh method: A semiconductor memory device has a plurality of banks in which operations are performed for the banks in accordance with a command supplied from an external controller. The semiconductor memory device comprises a latch circuit for latching a bank selection signal indicative of a bank which was precharged last among... Agent: Foley And Lardner LLP Suite 500

20070047364 - Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and... Agent: Ryan, Mason & Lewis, LLP

20070047365 - Semiconductor device: There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data... Agent: Buchanan, Ingersoll & Rooney PC

20070047366 - Non-volatile memory device: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first... Agent: Marshall, Gerstein & Borun LLP

20070047369 - Semiconductor device and control method of the same: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among... Agent: Wagner, Murabito & Hao LLP

20070047368 - Semiconductor memory device having layered bit line structure: A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070047367 - Semiconductor memory devices, block select decoding circuits and method thereof: Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two... Agent: Harness, Dickey & Pierce, P.L.C

20070047370 - Memory arrangement and method for addressing a memory arrangement: A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree.... Agent: Brinks Hofer Gilson & Lione

20070047372 - Semiconductor memory system and semiconductor memory chip: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder... Agent: Edell, Shapiro & Finnan, LLC

20070047371 - Semiconductor transistor with multi-level transistor structure and method of fabricating the same: Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell... Agent: Harness, Dickey & Pierce, P.L.C

20070047373 - Storage device, control method of storage device, and control method of storage control device: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding... Agent: Wagner, Murabito & Hao LLP

20070047375 - Duty cycle detector with first and second oscillating signals: A duty cycle detector including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period proportional to the first duty cycle. The second circuit... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070047374 - Memory controller and memory system: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070047378 - Method and apparatus for obtaining memory status information cross-reference to related applications: In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with... Agent: Qualcomm Incorporated Patent Department

20070047376 - Method and apparatus for synchronizing data from memory arrays: According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps.... Agent: Jones Day

20070047377 - Printed circuit board for memory module, method of manufacturing the same and memory module/socket assembly: Example embodiments of the present invention may include a printed circuit board, a method of manufacturing the printed circuit board, and a memory module/socket assembly. Example embodiments of the present invention may increase the number of contact taps on a memory module, in addition, a force required to insert the... Agent: Harness, Dickey & Pierce, P.L.C