Static information storage and retrieval inventions 03/07

20070070669 - Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a... Agent: Deniro/rambus

20070070670 - Semiconductor memory device: A semiconductor memory device includes a bank including a plurality of cell blocks; a first group of local input/output lines to transfer data stored on a first group of the cell blocks according to a first data output mode; a second group of local input/output lines to transfer data stored... Agent: Mcdermott Will & Emery LLP

20070070671 - Integrated semiconductor memory with transmission of data via a data interface: During a read access to a memory cell array of an integrated semiconductor memory device, data of a data word is fed to a data generator circuit which can be operated in the operating modes of noninverted and bitwise inverted transmission of data. The data generator circuit generates a control... Agent: Edell, Shapiro & Finnan, LLC

20070070672 - Semiconductor device and driving method thereof: A semiconductor device includes a first internal voltage generator generating an internal voltage using a first external power supply voltage in a normal mode; a second internal voltage generator generating the internal voltage using a second external power supply voltage supplied through a no connection (N/C) pin in a test... Agent: Blakely Sokoloff Taylor & Zafman

20070070673 - Power delivery and power management of many-core processors: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide... Agent: Blakely Sokoloff Taylor & Zafman

20070070674 - Semiconductor memory device: Provided are semiconductor design technologies, especially a bit line sense amplifier array of a semiconductor memory device. The semiconductor memory device includes a plurality of unit bit line sense amplifiers, a pull-up power line which is a power line of the plurality of unit bit line sense amplifiers, a single... Agent: Blakely Sokoloff Taylor & Zafman

20070070675 - Semiconductor memory device: An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read signal, a... Agent: Mcdermott Will & Emery LLP

20070070677 - Internal signal generator for use in semiconductor memory device: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command.... Agent: Mcdermott Will & Emery LLP

20070070676 - Pipe latch device of semiconductor memory device: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when... Agent: Mcdermott Will & Emery LLP

20070070678 - Semiconductor storage device: The present invention is a semiconductor storage device comprising a plurality of memory cells disposed in an array in the row and column directions and a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in... Agent: Arent Fox PLLC

20070070679 - Circuitry for a programmable element: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part... Agent: Trask Britt, P.C./ Micron Technology

20070070680 - Electric circuit: As for a transistor, overlapped are factors such as a variation of a gate insulation film which occurs due to a difference of a manufacturing process and a substrate used and a variation of a crystalline state in a channel forming region and thereby, there occurs a variation of a... Agent: Fish & Richardson P.C.

20070070681 - Memory device comprising an array of resistive memory cells: A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and the bit... Agent: Morrison & Foerster LLP

20070070682 - Storage device and semiconductor device: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from... Agent: David R. Metzger Sonnenschein Nath & Rosenthal LLP

20070070684 - Dynamic therapy bed system: A therapeutic mattress system is provided for treating a patient. The mattress system has a mattress having plurality of vertically elongated cells extending from a base layer that are arranged in a row and column grid arrangement. Each cell has a sidewall and a patient support surface extending therefrom, and... Agent: Wallenstein & Wagner, Ltd.

20070070683 - Random access memory including first and second voltage sources: A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070070685 - Atomic probes and media for high density data storage: A device in accordance with embodiments of the present invention comprises an atomic probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the atomic probe can include a core having a conductive coating. The core can comprise an insulating or conducting material, and the coating... Agent: Fliesler Meyer LLP

20070070687 - Adjustable current source for an mram circuit: A word current source for a magnetoresistive random access memory (MRAM) circuit includes an n-channel transistor including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the MRAM circuit. A positive supply voltage is coupled to the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070686 - Method and device for performing active field compensation during programming of a magnetoresistive memory device: The present invention provides an array (20) og magnetoresistive memory elements (10). The array (20) comprises: means for applying a current or voltage for generating a programming magnetic field at a selected magnetoresistive memory element (10s), a magnetic field sensor unit (50) for measuring an external magnetic field in the... Agent: Philips Intellectual Property & Standards

20070070688 - Word driver and decode design methodology in mram circuit: A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070689 - Magneto-resistive element: A magneto-resistive element according to an aspect of the present invention includes a free layer whose magnetized state changes and a pinned layer whose magnetized state is fixed. The free layer comprises first and second ferromagnetic layers and a non-magnetic layer which is arranged between the first and second ferromagnetic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070690 - Method for using a multi-use memory cell and memory array: A method for using a multi-use memory cell and memory array are disclosed. In one preferred embodiment, a memory cell is operable as a one-time programmable memory cell or a rewritable memory cell. The memory cell comprises a memory element comprising a semiconductor material configurable to one of at least... Agent: Brinks Hofer Gilson & Lione

20070070691 - Apparatus and method for simultaneous testing of multiple orthogonal frequency division multiplexed transmitters with single vector signal analyzer: Apparatus and method for testing signals from two or more OFDM transmitters simultaneously with a single VSA.... Agent: Vedder Price Kaufman & Kammholz

20070070692 - Compressed event counting technique and application to a flash memory system: A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embodiments include updating the compressed count based... Agent: Parsons Hsue & De Runtz LLP

20070070693 - Semiconductor integrated circuit device including storage unit having nonvolatile and volatile memory element sections: A semiconductor integrated circuit device includes a storage unit arranged on a semiconductor chip to store a plurality of data, and a plurality of registers provided on the semiconductor chip, the registers storing the data transferred from the storage unit, respectively. The storage unit has a nonvolatile memory element section... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070694 - Storage device employing a flash memory: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070070695 - Circuit and method of generating internal supply voltage in semiconductor memory device: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first... Agent: Mills & Onello LLP

20070070696 - Drift compensation in a flash memory: A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070070697 - Semiconductor memory device: A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the second... Agent: Mcdermott Will & Emery LLP

20070070698 - Compact virtual ground diffusion programmable rom array architecture, system and method: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with each pair of adjacent columns,... Agent: Shreen K. Danamraj Danamraj & Youst, P.C.

20070070699 - Nonvolatile semiconductor memory device having dummy bit line with multiple sections: A nonvolatile semiconductor memory device is disclosed having a dummy bit line formed from a plurality of dummy bit line sections. The particular dummy bit line sections are variously connected a common source line and a P-type well region.... Agent: Volentine Francos, & Whitt PLLC

20070070700 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled... Agent: Leffert Jay & Polglaze, P.A.

20070070701 - Nand flash memory device and programming method: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating... Agent: Volentine Francos, & Whitt PLLC

20070070702 - Nonvolatile semiconductor memory device which stores multi-value information: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit)... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070070703 - Flash memory array system including a top gate memory cell: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070070704 - Nonvolatile memory with program while program verify: A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20070070706 - Bit line control circuit for semiconductor memory device: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for... Agent: Mcdermott Will & Emery LLP

20070070707 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of... Agent: Mcdermott Will & Emery LLP

20070070705 - Semiconductor memory device for driving a word line: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of... Agent: Mcdermott Will & Emery LLP

20070070708 - Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070711 - Driving signal generator for bit line sense amplifier driver: A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving signal generating... Agent: Mcdermott Will & Emery LLP

20070070710 - Nonvolatile semiconductor memory device and data writing method: The present invention aims to eliminate variations in threshold voltage subsequent to the writing of data in an EPROM. When a parasitic resistance between the source of a memory cell (M00) of an even-numbered row and its corresponding bit line (BL0) is larger by a resistance (R00) than a parasitic... Agent: Nixon Peabody, LLP

20070070709 - Write circuit of memory device: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the... Agent: Mcdermott Will & Emery LLP

20070070712 - Data input/output multiplexer of semiconductor device: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer... Agent: Mcdermott Will & Emery LLP

20070070713 - Data output device of semiconductor memory device: There is provided a data output device for stably operating in a high frequency circumstance. The data output device includes a selection unit for receiving a second address information signal to directly output or inversely output the received signal as a third address information signal in response to a first... Agent: Mcdermott Will & Emery LLP

20070070716 - Semiconductor integrated circuit device: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable... Agent: Miles & Stockbridge PC

20070070715 - Semiconductor memory device: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An... Agent: Mcdermott Will & Emery LLP

20070070714 - Synchronous semiconductor memory device: A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signal in response to internal command signals; a delay unit for delaying... Agent: Mcdermott Will & Emery LLP

20070070717 - Semiconductor memory device for adjusting impedance of data output driver: An apparatus for comparing inputted signals by removing an offset voltage during adjusting an output impedance of a semiconductor memory device, includes a voltage comparator for comparing a first input signal applied to its positive input node with a second input signal applied to its negative input node to output... Agent: Mcdermott Will & Emery LLP

20070070719 - Core voltage generator and method for generating core voltage in semiconductor memory device: Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to... Agent: Mcdermott Will & Emery LLP

20070070721 - Device for controlling internal voltage: A device controls internal voltage. Increased reliability of a semiconductor memory device is obtained by increasing or decreasing a level of internal reference voltage according to change of the device. Fuse ROMs generate fuse signals having different levels according to a cutting condition of each fuse. A bit counter performs... Agent: Mcdermott Will & Emery LLP

20070070723 - Internal voltage generator for semiconductor memory device: An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the... Agent: Mcdermott Will & Emery LLP

20070070725 - Internal voltage supplying device: An internal voltage supplying device includes a level sensing means for sensing a level of a high voltage with respect to a core voltage, an oscillation signal generating means for generating an oscillation signal controlled by the level sensing means, and a pumping means for pumping charges during an activation... Agent: Blakely Sokoloff Taylor & Zafman

20070070724 - Semiconductor memory device for controlling reservoir capacitor: A semiconductor memory device is provided. Especially, there is disclosed a technique capable of increasing a net die by employing a cell capacitor as a reservoir capacitor according to a set mode. The semiconductor memory device of the present invention uses the cell capacitor as the reservoir capacitor in a... Agent: Blakely Sokoloff Taylor & Zafman

20070070722 - Voltage generator: A voltage generator reduces a stand by current in a stand by or a self-refresh mode and shortens a response time in an active mode by selectively driving a control transistor of a final driver. A core voltage control unit provides a power voltage. Pull-up and pull-down driving signals are... Agent: Mcdermott Will & Emery LLP

20070070720 - Voltage generator for use in semiconductor device: A voltage generator for use in a semiconductor memory device includes an output voltage controller for generating a bias voltage using a reference voltage of which a voltage level is half of a core voltage level. Pull-up/pull-down driving signals are output by generating a voltage which is higher or lower... Agent: Mcdermott Will & Emery LLP

20070070718 - Voltage regulator for memory device: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply... Agent: Rabin & Berdo, PC

20070070726 - Over-driving circuit in semiconductor memory device: A semiconductor memory over-driving scheme for a semiconductor memory device makes it possible to secure a high-speed sensing operation of a memory sense amplifier, regardless of a change of a power supply voltage. Over-driving efficiency is improved by controlling the discharging time and the drivability using different sized the drivers... Agent: Mcdermott Will & Emery LLP

20070070727 - Semiconductor memory device including reset control circuit: A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a... Agent: Mcdermott Will & Emery LLP

20070070728 - Semiconductor memory with reset function: A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC further includes a reset circuit is configured to generate... Agent: Townsend And Townsend And Crew, LLP

20070070733 - Circuit and method for outputting aligned strobe signal and parallel data signal: An output circuit includes a detector receiving a parallel data signal, detecting a level change degree for the parallel data signal between a first time point and a second time point, and outputting a select signal according to the level change degree; a delay adjusting device receiving and differentially delaying... Agent: Madson & Austin Gateway Tower West

20070070731 - Delay locked operation in semiconductor memory device: A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling... Agent: Mcdermott Will & Emery LLP

20070070729 - High access speed flash controller: A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write (R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and... Agent: Bruce H. Troxell

20070070732 - Method for generating adjustable mram timing signals: A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit generates a timing control signal. A number of variable timing circuits are each coupled to receive at least... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070730 - Semiconductor memory device: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an... Agent: Mcdermott Will & Emery LLP

20070070737 - Method and auxiliary device for creating and checking the circuit diagram for a circuit which is to be integrated: Method and apparatus for creating and checking a circuit diagram for a circuit which is to be integrated. On the basis of this circuit diagram, a layout for the circuit which is to be integrated is designed. Both when designing the circuit diagram and in a layout description extracted from... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070738 - Motor and controller inversion: commanding torque to position-controlled robot: Systems and methods are presented that cancel the dynamics of a motor and a joint controller in the presence of communication time delays, measurement noise, and controller parameter uncertainties inherent in a robot system. A cancellation system includes feedback of the measured output Ê of a controller block C. A... Agent: Honda/fenwick

20070070734 - Reconfigurable memory block redundancy to repair defective input/output lines: An embodiment of the present invention is a technique to provide a reconfigurable repair circuit in a memory device. A table structure contains a plurality of entries, each entry having a defective address word and a redundant address word. The redundant address word corresponds to a redundant block and is... Agent: Blakely Sokoloff Taylor & Zafman

20070070735 - Redundant circuit for semiconductor memory device: A redundant circuit includes a plurality of bit line sense amp arrays including different local data buses, sharing one bit line sense amp, and being formed adjacently to each other, an input/output fuse unit for outputting a selection signal with different logic state depending on whether or not a first... Agent: Blakely Sokoloff Taylor & Zafman

20070070736 - Semiconductor device: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces... Agent: Young & Thompson

20070070743 - Multi-port semiconductor memory device: A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the... Agent: Blakely Sokoloff Taylor & Zafman

20070070739 - Semiconductor memory device and its test method: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070070741 - Semiconductor memory device for measuring internal voltage: A semiconductor memory device includes a plurality of internal voltage measuring units, each for driving data input from a memory bank to output the data when a test signal is deactivated, and outputting a corresponding one of internal voltages used in the semiconductor memory device when the test signal is... Agent: Mcdermott Will & Emery LLP

20070070740 - Semiconductor memory device having data-compress test mode: A semiconductor memory device performs a data-compress test under the same conditions as a normal mode. The semiconductor memory device includes a cell bank for including plural memory cell units for data storage and a data sense amplifying block for sensing and amplifying plural output data of the cell bank... Agent: Mcdermott Will & Emery LLP

20070070742 - Test mode controller: A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate... Agent: Mcdermott Will & Emery LLP

20070070744 - Fast pre-charge circuit and method of providing same for memory devices: A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector distance from driver of the integrated circuit memory device, and the... Agent: Baker & Mckenzie LLP Patent Department

20070070748 - Method for discharging and equalizing sense lines to accelerate correct mram operation: A method and apparatus for discharging and equalizing sense lines embedded in a magnetoresistive random access memory integrated circuit (MRAM IC) includes using a current source connected to a current source node. A sense line is connected to the current source node. A bit decode element is coupled to turn... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070070745 - Redundant wordline deactivation scheme: Embodiments of the present inventions provide a method and apparatus for reducing power consumption of a memory device. In one embodiment, the method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070747 - Semiconductor memory device: A semiconductor memory device includes an equalizing signal generation circuit comprising a clamping circuit that clamps a voltage level less than the voltage level of a high voltage level by being controlled by the high voltage, and an equalizing signal driver receiving an output signal of the equalizing signal generation... Agent: Mcdermott Will & Emery LLP

20070070749 - Semiconductor memory device and data read and write method thereof: A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting... Agent: Marger Johnson & Mccollom, P.C.

20070070746 - Semiconductor memory device and its driving method: A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD, when the equalization signal is repeated by a repeater. In order to improve bit line precharging performance... Agent: Mcdermott Will & Emery LLP

20070070750 - Apparatus and method for data transmission, and apparatus and method for driving image display device using the same: An apparatus and method for data transmission and an apparatus and method for driving an image display device using the same are disclosed, in which transition of data is minimized during data transmission to minimize electromagnetic interference. The apparatus for data transmission includes a data modulator modulating low bits excluding... Agent: Mckenna Long & Aldridge LLP Song K. Jung

20070070751 - Bit line sense amplifier control circuit: A bit line sense amplifier control circuit comprises a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal... Agent: Heller Ehrman LLP

20070070752 - Semiconductor memory device and method for driving bit line sense amplifier thereof: A semiconductor memory device includes an amplifying unit for amplifying a voltage difference between a bit line pair; a power supply driver for supplying a power to the amplifying unit in response to a second driving signal; a control unit for generating a first driving signal of the power supply... Agent: Blakely Sokoloff Taylor & Zafman

20070070753 - Single transistor sensing and double transistor sensing for flash memory: A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other... Agent: Dla Piper Rudnick Gray Cary Us, LLP

20070070754 - Low equalized sense-amp for twin cell drams: Embodiments of the invention provide a method and apparatus for accessing a twin cell memory device. In one embodiment, a twin memory cell is accessed using a first bitline and a second bitline. The method includes precharging the first bitline and the second bitline to a low voltage. A wordline... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070757 - Over-driving circuit for semiconductor memory device: An over-driving circuit for a semiconductor memory device is capable of rapidly securing a sensing operation of a bit line sense amplifier regardless of a level change of a power supply voltage. Timings are adjustsed for supplying an over-driving voltage and for discharging based on a level change of a... Agent: Mcdermott Will & Emery LLP

20070070759 - Scalable embedded dram array: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070070755 - Semiconductor memory device having shared bit line sense amplifier scheme and driving method thereof: A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper... Agent: Mcdermott Will & Emery LLP

20070070756 - Semiconductor memory device sharing sense amplifier: A semiconductor memory device contains a reduced number of signal lines of a core area required for data access. The semiconductor memory device includes a sense amplifier for selectively sensing and amplifying data signals on a first pair of bit lines arranged at a first cell array and a second... Agent: Mcdermott Will & Emery LLP

20070070758 - Semiconductor memory with sense amplifier and switch: A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070070761 - Internal voltage generator: An internal voltage generator includes: an internal voltage driving unit for supplying an internal voltage corresponding to a reference voltage maintaining a predetermined voltage level regardless of a temperature variation; and a temperature compensation current sinking unit for sinking a current generated by an internal voltage in response to a... Agent: Mcdermott Will & Emery LLP

20070070760 - Memory device with self refresh cycle control function: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent... Agent: Mcdermott Will & Emery LLP

20070070762 - Method and apparatus for optimizing data buffering: A method for storing data in a first buffer and a second buffer is disclosed. The method includes: sequentially storing an incoming data into the first buffer and the second buffer according to a first threshold; transferring data stored in the second buffer to the first buffer when an amount... Agent: North America Intellectual Property Corporation

20070070766 - High voltage generator and semiconductor memory device: A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power... Agent: Mcdermott Will & Emery LLP

20070070764 - Memory: This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion... Agent: Mcdermott Will & Emery LLP

20070070767 - Multi-port memory device having self-refresh mode: The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh... Agent: Blakely Sokoloff Taylor & Zafman

20070070768 - Refresh control circuit and method for multi-bank structure dram: A refresh control circuit for use in a semiconductor memory device having a plurality of banks, including: a bank number signal generator for generating a plurality of bank number signals having a predetermined delay time between generation timings of the plurality of bank number signals based on a refresh signal... Agent: Blakely Sokoloff Taylor & Zafman

20070070763 - Semiconductor memory device: A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and... Agent: Blakely Sokoloff Taylor & Zafman

20070070765 - Semiconductor memory device with advanced refresh control: A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank;... Agent: Mcdermott Will & Emery LLP

20070070769 - Circuit and method for controlling a standby voltage level of a memory: A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of... Agent: Ibm Microelectronics Intellectual Property Law

20070070771 - Method and a control unit for controlling a power level: A method and a control unit for controlling a power level being drawn from a power source (26). Based on a determined rate of change of a measured voltage (1) an estimated remaining runtime is calculated. The estimated remaining runtime represents a time where specific run criteria will no longer... Agent: Mccormick, Paulding & Huber LLP

20070070770 - Method and system of operating mode detection: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes... Agent: Toler Schaffer, LLP

20070070772 - Voltage generator for peripheral circuit: A voltage generator for a peripheral circuit, the voltage generator includes: a voltage supplier supplying a peripheral circuit voltage having a voltage level maintained at a reference voltage level, the peripheral circuit voltage outputted in response to a driving signal; and a voltage level compensator increasing the voltage level of... Agent: Blakely Sokoloff Taylor & Zafman

20070070773 - Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same: A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage,... Agent: Texas Instruments Incorporated

20070070775 - Device for driving global signal: A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the... Agent: Mcdermott Will & Emery LLP

20070070774 - Memory device having latch for charging or discharging data input/output line: A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is... Agent: Mcdermott Will & Emery LLP

20070070776 - Semiconductor memory device: A semiconductor device reduces unnecessary operating current while an internal row/column address is generated. The semiconductor memory device includes an address input unit for transferring an address signal inputinput from an external device; an internal column address generating unit for receiving the transferred address signal to generate an internal column... Agent: Mcdermott Will & Emery LLP

20070070777 - Semiconductor memory device: A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second... Agent: Mcdermott Will & Emery LLP

20070070778 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent: Blakely Sokoloff Taylor & Zafman

20070070779 - Multi-port semiconductor memory: A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is... Agent: Nixon Peabody, LLP

20070070781 - Internal address generator: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate... Agent: Mcdermott Will & Emery LLP

20070070782 - Memory device input buffer, related memory device, controller and system: Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the... Agent: Volentine Francos, & Whitt PLLC

20070070780 - Output driving device: An output driving device includes a pull-up driver for pull-up driving an output node in response to a pull-up control signal; a pull-down driver for pull-down driving the output node in response to a pull-down control signal; and a first n-type metal oxide semiconductor (NMOS) transistor for pull-up driving the... Agent: Mcdermott Will & Emery LLP

20070070783 - Semiconductor memory device: A semiconductor memory device includes a cell matrix having a number of cells, a multiplicity of column decoders for selectively activating the cells in response to code signals containing column address information for the cells, wherein each column decoder contains a pre-driving unit for providing a state output signal transiting... Agent: Blakely Sokoloff Taylor & Zafman

20070070785 - Semiconductor memory device: A semiconductor memory device changes a pulse width of an over driving signal according to operation modes, which differ by a degree of accessing memory banks during an over driving operation. An over driver supplies an RTO line of the bit line sense amplifier with an over driving voltage in... Agent: Mcdermott Will & Emery LLP

20070070786 - Semiconductor storage device: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, a plurality of word lines connected to the memory cells, a row decoder including a plurality of decode sections and configured to receive first and second address signals... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070070784 - Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device: A semiconductor memory device includes a bit line sense amplifying block that senses and amplifies bit line data. A first driving block drives a pull up power line of the bit line sense amplifying block using a voltage applied to a normal driving voltage terminal. A second driving block drives... Agent: Mcdermott Will & Emery LLP

20070070787 - Semiconductor memory device: A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an address buffer control signal in response to... Agent: Mcdermott Will & Emery LLP

20070070788 - Apparatus and method for dynamically controlling data transfer in memory device: Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. In one embodiment, the secondary sense amplifier is set (causing data... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070070794 - Arbitration for memory device with commands: A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or... Agent: Law Office Of Monica H Choi

20070070791 - Clock control device: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in... Agent: Mcdermott Will & Emery LLP

20070070797 - Data transmission device in semiconductor memory device: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through... Agent: Mcdermott Will & Emery LLP

20070070798 - Internal address generator for use in semiconductor memory device: An internal address generator for use in a semiconductor memory device includes an address detector, a drive pulse generator, and a delay unit. The address detector generates a comparison signal by comparing a first address currently input with a second address previously input. The drive pulse generator generates a drive... Agent: Mcdermott Will & Emery LLP

20070070799 - Memory and method of controlling access to memory: The present invention provides a memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access... Agent: Ibm Microelectronics Intellectual Property Law

20070070789 - Module apparatus and method for controlling auto on/off of clock for saving power: A module apparatus and method for saving power by automatically controlling an ON/OFF state of a clock is provided. The module apparatus comprises a core performing special functions and storing operation information, and a clock controller applying or not applying an external clock input according to the operation information transmitted... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070070795 - Multi-port memory device with serial input/output interface: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data... Agent: Blakely Sokoloff Taylor & Zafman

20070070790 - Output control device: An output controller includes a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe... Agent: Mcdermott Will & Emery LLP

20070070792 - Output controller with test unit: There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an initial synchronizing unit for outputting a first output enable signal when a read CAS signal is activated; a plurality... Agent: Mcdermott Will & Emery LLP

20070070793 - Semiconductor memory device: A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing... Agent: Blakely Sokoloff Taylor & Zafman

20070070796 - Semiconductor memory device having data-compress test mode: A semiconductor memory device includes a plurality of column circuit units selectively operated with a burst length set in a mode register set. A plurality of column control blocks control column access to unit cells, each block activated by each of plural column control signals, and a column control signal... Agent: Mcdermott Will & Emery LLP

20070070800 - Externally worn vasovagal syncope detection device: A device is worn adjacent to tissue of a patient to detect vasovagal syncope (VVS). The device includes a photoplethysmographic sensor that measures a plethysmographic signal through tissue, and a processor that derives an indicator of an autonomous nervous system (ANS) activity from the plethysmographic signal and estimates a probability... Agent: Medtronic, Inc.

20070064461 - Low power content addressable memory: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare... Agent: Shemwell Gregory & Courtney LLP

20070064462 - Memory system and data transmission method: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory... Agent: Scully Scott Murphy & Presser, PC

20070064463 - Rom load balancing for bit lines: An apparatus and method to improve a cycle time of a Read Only Memory (ROM). Loading of each bit line is controlled such that no bit line has less than a specified loading fraction of a loading of a maximally loaded bit line. No additional space or additional circuitry is... Agent: Robert R. Williams IBM Corporation

20070064464 - High performance flash memory device capable of high density data storage: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits... Agent: Harrity & Snyder, L.L.P.

20070064466 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled... Agent: Leffert Jay & Polglaze, P.A.

20070064465 - Rom storing information by using pair of memory cells: Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070064467 - Read-only memory: An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the... Agent: Seed Intellectual Property Law Group PLLC

20070064468 - Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device: Provided are a charge trap memory device including a substrate and a gate structure including a charge trapping layer formed of a composite of nanoparticles, and a method of manufacturing the charge trap memory device.... Agent: Cantor Colburn, LLP

20070064469 - Display device and driving method of the same: A first capacitor obtains a gate-source voltage of a first transistor in accordance with a programming current flowing through the first transistor, and a second capacitor obtains a threshold voltage of a second transistor. Then, the electric charges held in the first capacitor and the second capacitor are capacitively coupled.... Agent: Fish & Richardson P.C.

20070064470 - Semiconductor device: A semiconductor device according to an embodiment of the present invention includes: an oscillating circuit including a plurality of logic circuits connected in series; and an error detecting circuit receiving output signals of at least two of the plurality of logic circuits, and suspending an operation of the oscillating circuit... Agent: Young & Thompson

20070064471 - Magnetostatic communication: A system for providing communication of information by modulating a magnetostatic field with a magnetostatic transmitter that modulates said magnetostatic field to contain the information and detecting the information in the modulated field at a distance with a magnetostatic detector that detects the modulated magnetic field containing the information.... Agent: Eddie E. Scott Assistant Laboratory Counsel

20070064472 - Nonvolatile semiconductor memory device performing data writing in a toggle manner: A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between... Agent: Mcdermott Will & Emery LLP

20070064473 - Phase change memory device and program method thereof: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval.... Agent: Volentine Francos, & Whitt PLLC

20070064474 - Resistance variable memory element with threshold device and method of forming the same: A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least two resistance states. The threshold device is configured to switch from a high resistance state to a low resistance state upon... Agent: Dickstein Shapiro LLP

20070064475 - Simulating circuit for magnetic tunnel junction device: A simulating circuit for simulating the operation of a magnetic tunnel junction (MTJ) device having at least a free layer and a fixed layer is provided. The simulating circuit includes a closed switch loop for simulating the magnetization of the free layer and the fixed layer, thus for simulating the... Agent: Rabin & Berdo, PC

20070064476 - Semicoductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof: The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output... Agent: Rossi, Kimms & Mcdowell LLP.

20070064478 - Nanotube- and nanocrystal-based non-volatile memory: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write... Agent: Intel/blakely

20070064477 - System for remote data sharing: Embodiments of the present invention encompass a remote data sharing system that can support connectivity between any JDBC-compliant data source and any Java-compatible remote client, which system can be implemented without programming. The system can comprise at least one JDBC-compliant data source, a gateway running inside a Java-compliant web container,... Agent: Battelle Memorial Institute Attn:IPServices, K1-53

20070064483 - Clock synchronized non-volatile memory device: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070064480 - Multi-bit flash memory device having improved program rate: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain... Agent: Harrity & Snyder, L.L.P.

20070064482 - Semiconductor integrated circuit device: A semiconductor integrated circuit device has a first memory cell group including a plurality of rewritable nonvolatile memory cells arranged on a semiconductor chip and a second memory cell group including a plurality of rewritable nonvolatile memory cells arranged on the semiconductor chip. Setting of the write threshold voltage of... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070064481 - Storage device: Memory cell can stores a multi-valued value more than a binary value in a single storage cell by changing the amount of electric charge to be stored. Data logic stores storage data, each digit of which is binary as a binary value in each memory cell for each digit. Furthermore,... Agent: Staas & Halsey LLP

20070064484 - Non-volatile programmable memory cell for programmable logic array: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor,... Agent: Sierra Patent Group, Ltd.

20070064485 - Page buffer flash memory device and programming method using the same: A page buffer of a flash memory device is configured to program two pages in a single programming operation. The page buffer of the flash memory device includes a first bit line selection unit, a second bit line selection unit, a separation unit, a precharge unit, a first register, and... Agent: Townsend And Townsend And Crew, LLP

20070064486 - Display device and fabricating method thereof: A display device that lends itself to a cost-effective and simplified manufacturing process is presented. The display device includes an insulating substrate; a common voltage line formed on the insulating substrate; an insulating layer provided on the common voltage line; and a contact hole extending through the insulating layer to... Agent: Macpherson Kwok Chen & Heid LLP

20070064487 - Program method and circuit of non-volatile memory: A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to... Agent: J C Patents, Inc.

20070064488 - Eeprom and method of driving the same: An EEPROM (Electrically Erasable and Programmable Read Only Memory) has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a common gate electrode and constitute one memory cell. A program operation and an erase operation are carried out by using... Agent: Sughrue Mion, PLLC

20070064479 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell, and a reference cell including a same structure as the memory cell. A detecting circuit detects a timing when a voltage of a reference bit line connected with the reference cell becomes lower than or equal to a setting voltage, and... Agent: Sughrue Mion, PLLC

20070064489 - Method and circuitry to generate a reference current for reading a memory cell, and device implementing same: There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state... Agent: Neil A. Steinberg

20070064490 - Non-volatile semiconductor memory device: A memory cell array comprises a group of memory cells capable of retaining two-bit information. The memory cell has a pair of transistors having charge storage regions and arranged along a row direction of the memory cell array. Word lines are provided between the memory cells adjacent to each other... Agent: Mcdermott Will & Emery LLP

20070064492 - Optimizing the speed of an fc-al switch domain in a data storage network: In a fibre channel, arbitrated loop (FC-AL) network environment, an operating speed of devices within a switch domain within the network is optimized. The FC-AL switch domain is isolated from an attached storage controller, and a first signal is transmitted to each of a plurality of storage devices within the... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070064491 - Radio resource management: The present invention relates to radio resource management in a wireless communication system. Specifically, the present invention relates to a method and apparatus for a method of managing downlink radio resources for a multi-sector base transceiver site in which power can be shared between the sectors in which radio resource... Agent: Motorola, Inc.

20070064494 - Embedded eeprom array techniques for higher density: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to... Agent: Texas Instruments Incorporated

20070064493 - Flash memory programming using an indication bit to interpret state: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current... Agent: Harrity & Snyder, L.L.P.

20070064495 - Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070064496 - Cell string of flash memory device and method of manufacturing the same: Disclosed herein are a cell string of a flash memory device and a method of manufacturing the same. The cell string of a flash memory device includes a plurality of memory cells connected to a single bit line and arranged with first distance between the memory cells, and a source... Agent: Marshall, Gerstein & Borun LLP

20070064498 - Flash memory devices including multiple dummy cell array regions: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main... Agent: Myers Bigel Sibley & Sajovec

20070064497 - Non-volatile one time programmable memory: A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in... Agent: Leffert Jay & Polglaze, P.A.

20070064499 - Semiconductor memory device and method for writing data into the semiconductor memory device: A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory cell (100a) is coupled to the wordline (40), one of the second bitlines (22a) and the first bitline (21a).... Agent: Slater & Matsil LLP

20070064502 - Digital-to-analog conversion device: A digital-to-analog (D/A) conversion device including a data-latch unit, a D/A conversion unit and a gain amplifier is provided. Wherein, the amplitude of the supply voltages for the reference voltage of the D/A conversion unit is not greater than that of the data-latch unit so that the switches in a... Agent: J.c. Patents, Inc.

20070064504 - Dual reference input receiver of semiconductor device and method of receiving input data signal: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input... Agent: Volentine Francos, & Whitt PLLC

20070064500 - Integrated circuit with dynamic memory allocation: An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting... Agent: Philips Intellectual Property & Standards

20070064503 - Internal voltage generation control circuit and internal voltage generation circuit using the same: An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command... Agent: Marshall, Gerstein & Borun LLP

20070064501 - Wavelength-maintaining optical signal regenerator: The invention relates to a wavelength-maintaining purely optical signal regenerator to which degraded optical signals with a high data rate are transmitted and regenerated without opto-electronic or wavelength conversion using compact, non-linear semiconductor components with low power consumption. Said regenerator comprises: an optical clock regeneration stage (2) which generates synchronized... Agent: Law Offices Of Karl Hormann

20070064506 - Small signal threshold and proportional gain distributed digital communications: An apparatus for gain distribution in a system comprising a plurality of distributed antennas and a total system dynamic range is disclosed. The apparatus includes means for sensing a signal level at each of the plurality of distributed antennas, means for comparing at least one of the plurality of signal... Agent: Fogg And Associates, LLC

20070064505 - Test mode method and apparatus for internal memory timing signals: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals... Agent: Edell, Shapiro & Finnan, LLC

20070064508 - Fuse trimming circuit: The present invention provides a fuse trimming circuit that can reduce power consumption and improve operation reliability. The fuse trimming circuit is provided with a fuse-state determining circuit, which determines whether a fuse element is in an unblown state or in a blown state by comparing drain currents flowing to... Agent: Nixon Peabody, LLP

20070064507 - Semiconductor memory device having bit registering layer and method of driving the same: The semiconductor memory device includes a memory layer having a plurality of memory cells for storing data, and at least one bit registering layer for recording status information on whether the memory cells are defective. The memory layer may be a nanometer-scale memory device, such as a molecular memory, a... Agent: Harness, Dickey & Pierce, P.L.C

20070064510 - Method and apparatus for evaluating and optimizing a signaling system: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference.... Agent: Hunton & Williams LLP/rambus Inc. Intellectual Property Department

20070064509 - Method and device for transmission of adjustment information for data interface drivers for a ram module: A method and a device are described for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller, with control bits for adjustment purposes being sent during an adjustment mode by the controller as a... Agent: Morrison & Foerster LLP

20070064511 - Semiconductor device: It is an object of the present invention to provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. A semiconductor device of the invention has three factors of a data holding unit, a precharge... Agent: Fish & Richardson P.C.

20070064512 - Flash memory device and associated recharge method: A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first high voltage line to the second high voltage... Agent: Volentine Francos, & Whitt PLLC

20070064513 - Semiconductor apparatus: In a semiconductor apparatus, a power supply voltage generating circuit (21) and an internal circuit (22) using a power supply voltage generated by the power supply voltage generating circuit are supplied with different internal circuit preset signals (PRESET 1 and PRESET 2) optimized for the power supply voltage generating circuit... Agent: Mcginn Intellectual Property Law Group, PLLC

20070064514 - Control unit and portable terminal: A control unit capable of reliably preventing loss of data also when losing power during data processing is obtained. This control unit comprises a volatile memory temporarily storing data used in the control unit and a nonvolatile memory holding data of the volatile memory, for writing the same data as... Agent: Mcdermott Will & Emery LLP

20070064516 - Methods and apparatus for lancet actuation: A lancet driver is provided wherein the driver exerts a driving force on a lancet during a lancing cycle and is used on a tissue site. The driver comprises of a drive force generator for advancing the lancet along a path into the tissue site, and a sensor configured to... Agent: Heller Ehrman LLP

20070064515 - Reconfigurable input/output in hierarchical memory link: A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected... Agent: Mills & Onello LLP

20070064517 - Output control signal generating circuit: An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used... Agent: Mcdermott Will & Emery LLP