Static information storage and retrieval inventions 02/07

20070041231 - Memory device activation and deactivation: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.... Agent: Searete LLC Clarence T. Tegreene

20070041232 - Access circuit and method for allowing external test voltage to be applied to isolated wells: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070041234 - Storage device, file storage device, and computer system: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data... Agent: Rader Fishman & Grauer PLLC

20070041233 - Wake-up of ferroelectric thin films for probe storage: A method for improving the stability of ferroelectric storage devices comprises: providing a ferroelectric storage medium including a film of ferroelectric material; and repeatedly applying a voltage to the film of ferroelectric material to improve the stability of polarized bits in the film of ferroelectric material. An apparatus that is... Agent: Pietragallo, Bosick & Gordon LLP

20070041235 - Semiconductor storage device: In a semiconductor storage device with cross point type arrays of memory cells including variable resistor elements, a selected data line and unselected data lines are supplied with a row selecting potential and a row unselecting potential through a data line selecting transistor respectively, a selected bit line and unselected... Agent: Nixon & Vanderhye, PC

20070041236 - Methods and apparatuses for a sense amplifier: Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circuitry reduces a voltage potential across... Agent: Blakely Sokoloff Taylor & Zafman

20070041238 - High density data storage devices with read/write probes with hollow or reinforced tips: Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow conical structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon thereby defining a cantilever structure,... Agent: Fliesler Meyer LLP

20070041237 - Media for writing highly resolved domains: Systems in accordance with the present invention can include a tip contactable with a media, the media including a phase change material in an embodiment (or polarity-dependent memory material or other memory material in other embodiments) disposed between a substrate and an overcoat. The overcoat is a co-deposited film having... Agent: Fliesler Meyer LLP

20070041241 - Memory element: A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic components are... Agent: Dickstein Shapiro LLP

20070041242 - Nonvolatile memory cell, storage device and nonvolatile logic circuit: One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling... Agent: Rader Fishman & Grauer PLLC

20070041240 - Random access memory with a plurality of symmetrical memory cells: The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled device (31, 32), and the groups of memory cells are... Agent: Ibm Microelectronics Intellectual Property Law

20070041239 - Semiconductor memory device: The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not... Agent: Foley And Lardner LLP Suite 500

20070041243 - Magnetic memory device and method of fabricating the same: There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned... Agent: Marger Johnson & Mccollom, P.C.

20070041245 - Set programming methods and write driver circuits for a phase-change memory array: Exemplary embodiments of the present invention provide set programming methods and write driver circuits for a phase-change memory array. An exemplary embodiment of a set programming method may comprise applying a set current pulse to the phase-change cells, which may cause phase-change cells, which may be included within the phase-change... Agent: Harness, Dickey & Pierce, P.L.C

20070041246 - Method using a one-time programmable memory cell: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070041244 - Circuit for inhibition of program disturbance in memory devices: A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through... Agent: Howard Chen, Preston Gates & Ellis LLP

20070041247 - Flash memory device having single page buffer structure: A flash memory device is disclosed that comprises memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, and a second register connected to the common node and the sense node. The flash memory device further comprises a... Agent: Volentine Francos, & Whitt PLLC

20070041248 - Semiconductor storage device and method of manufacturing the same: A method of manufacturing a semiconductor storage device according to an embodiment of the present invention includes forming dummy cells 611, to 618 at a position adjacent to a reference cell 412, and implanting an impurity into the dummy cells 611, to 618 using a mask that covers the reference... Agent: Sughrue Mion, PLLC

20070041249 - Method of erasing non-volatile memory cells: A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage... Agent: Tiajoloff & Kelly

20070041250 - Read port circuit for register file: In one embodiment, a read port circuit comprises a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070041251 - Electrical circuit and a method for operating a programmable metallization cell: Embodiments of the present invention provide methods and apparatuses for programming a programmable metallization cell (PMC) memory cell are provided. In one embodiment, a memory device includes a programmable metallization memory cell, a plate line connected to a first node of the memory cell, and a bitline connected to a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070041252 - Self refresh control device: Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted... Agent: Mcdermott Will & Emery LLP

20070041253 - Methods and systems for generating latch clock used in memory reading: Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070041254 - Synchronous semiconductor memory device for reducing power consumption: Disclosed is a semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchronizing an internal clock with an external clock;... Agent: Mcdermott Will & Emery LLP

20070041255 - System and method for injecting phase jitter into integrated circuit test signals: A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock signal is provided for each of the pin groups to generate respective delayed clock signals. The phase shift produced by each of the phase interpolators... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070041256 - Layout for equalizer and data line sense amplifier employed in a high speed memory device: A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a... Agent: Marger Johnson & Mccollom, P.C.

20070041257 - Low voltage sensing scheme having reduced active power down standby current: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping... Agent: Thorp Reed & Armstrong, LLP

20070041258 - Semiconductor memory device for reducing cell area: A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers... Agent: Mcdermott Will & Emery LLP

20070041259 - Dram density enhancements: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of... Agent: Macpherson Kwok Chen & Heid LLP

20070041260 - Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same: A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in... Agent: Marger Johnson & Mccollom, P.C.

20070041261 - Power-source potential control circuit and method of trimming power-source potential: A power-source potential control circuit has: an output terminal outputting a control signal to a power-source generating device which generates a power-source potential in accordance with the control signal; an input terminal connected to an output of the power-source generating device; and a control unit configured to make a comparison... Agent: Mcginn Intellectual Property Law Group, PLLC

20070041262 - Register file: In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070041263 - Row decoder circuit for electrically programmable and erasable non volatile memories: The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20070041264 - Method and apparatus for synchronizing data between different clock domains in a memory controller: The present invention provides method and apparatus for synchronizing data between different clock domains in a memory controller. In one embodiment, a memory controller is provided that includes a command decoder and synchronizing logic. The command decoder is operable to receive a command in accordance with a first clock domain.... Agent: Sawyer Law Group LLP

20070035980 - System and method for optically interconnecting memory devices: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070035981 - Apparatus and method for dynamic control of double gate devices: An apparatus for implementing dynamic control of a double gate semiconductor device includes a first switch configured to selectively couple a first gate input of the double gate device to a second gate input of the double gate device, and a second switch configured to selectively couple the second gate... Agent: Cantor Colburn LLP - IBM Fishkill

20070035984 - A semiconductor device including a memory unit and a logic unit: In a semiconductor device including a memory unit and a logic unit, a generation of a step in a terminal end surface of an electroconductive plug in a region above a capacitor element is inhibited. Such semiconductor device includes an insulating layer provided on the semiconductor substrate extending from the... Agent: Young & Thompson

20070035982 - Ferroelectric memory device: A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells. The sense... Agent: Harness, Dickey & Pierce, P.L.C

20070035983 - Ferroelectric random access memory device and method for controlling writing sections therefor: A FeRAM device and a writing section control method therefor, in which the device includes a memory cell constructed of one access transistor and one ferroelectric capacitor; and a writing control circuit for controlling a first writing section to write data of a first logic state in the memory cell... Agent: F. Chau & Associates, LLC

20070035989 - Ideal cmos sram system implementation: CMOS static RAM based memory system, which reduces power consumption and increases operation speed by disconnecting cell power supply during write operation. Additional transistors are provided between Sources of the SRAM cell transistors and supply voltage or ground voltage connection. These are switched off during write, in order to interrupt... Agent: Bassem Mohamed Fouli

20070035986 - Sram cell using separate read and write circuitry: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read... Agent: Texas Instruments Incorporated

20070035988 - Sram, semiconductor memory device, method for maintaining data in sram, and electronic device: An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from being destructed by a latch-up phenomenon to maintain the stored data certainly even when a soft... Agent: Staas & Halsey LLP

20070035987 - Static random access memory device having a voltage-controlled word line driver for retain till accessed mode and method of operating the same: A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a word line and a power source configured to vary in voltage to enable the row of SRAM cells to operate in... Agent: Texas Instruments Incorporated

20070035985 - Voltage controlled static random access memory: A static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240′, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood... Agent: Downs Rachlin Martin PLLC

20070035990 - Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is... Agent: Dickstein Shapiro LLP

20070035991 - Read mode for flash memory: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell... Agent: Harrity & Snyder, L.L.P.

20070035992 - Non-volatile semiconductor memory and method for reading a memory cell: A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to a respective local bitline, and, wherein one of the source/drain regions of a neighboring memory cell is connected to one of the local bitlines,... Agent: Slater & Matsil LLP

20070035994 - Method and apparatus for programming multi level cell flash memory device: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic... Agent: Volentine Francos, & Whitt PLLC

20070035995 - Method of programming a four-level flash memory device and a related page buffer: A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read voltage... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070035998 - Nonvolatile memory apparatus: Disclosed is a nonvolatile memory apparatus in which a nonvolatile memory and a controller are mounted and which realizes improved performance of read/write speeds and improved resistance to a retention error. A nonvolatile memory can store information of two bits or more, and can perform a first reading operation of... Agent: Miles & Stockbridge PC

20070035996 - Nonvolatile semiconductor memory device and method of operating the same: A multi-level programmable nonvolatile semiconductor memory device comprises, a charge accumulation layer, a control gate which bias a potential to the charge accumulation layer, wherein the potential of the charge accumulation layer is controlled discretely according to the number of electrons accumulated in the charge accumulation layer.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070035997 - Semiconductor memory device which prevents destruction of data: A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070035999 - Page buffer circuit of flash memory device with dual page program function and program operation method thereof: A flash memory device has a page buffer circuit that has a dual page program function. The page buffer circuit is coupled to at least one pair of first bit lines and at least one pair of second bit lines.... Agent: Townsend And Townsend And Crew, LLP

20070036000 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes first to third memory cell units, first and second bit lines, and first and second source lines. The first to third memory cell units include memory cell transistors serially connected between selection transistors. The first bit line is commonly connected to one end of... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070036001 - Floating-gate nonvolatile semiconductor memory device: After data writing is performed by injecting electrons into a floating gate from a semiconductor substrate of a memory cell, the gate voltage is set at −3 V, and the source voltage, the drain voltage and the substrate voltage are set at 0 V, thereby detrapping the electrons trapped in... Agent: Mcdermott Will & Emery LLP

20070036002 - Programming flash memories: A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted to perform a method of... Agent: Leffert Jay & Polglaze, P.A.

20070035993 - Semiconductor device and method of generating a reference voltage therefor: A semiconductor device includes at least one reference cell (6), a cascode circuit (8) that has at least two current mirror circuits (30, 33 and 30, 34) and outputs voltages dependent on a current flowing through the at least one reference cell (6) to at least two output paths (55,... Agent: Ingrassia Fisher & Lorenz, P.C.

20070036003 - Soft erasing methods for nonvolatile memory cells: Erasure methods are provided for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied... Agent: Myers Bigel Sibley & Sajovec

20070036004 - Hybrid non-volatile memory device: The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping... Agent: Howard Chen Preston Gates & Ellis LLP

20070036005 - Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory: A wrapper circuit effectively converts a muxed-type memory (having time-multiplexed address and data lines) into a non-muxed type memory as seen by the controller (a non-muxed type memory controller). Wrapper circuit includes a select circuit (e.g., multiplexer) and an input/output buffer. The select circuit receives write data and an address... Agent: F. Chau & Associates, LLC

20070036006 - System and method for mode register control of data bus operating mode and impedance: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070036008 - Semiconductor memory device: A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; and a column selection line driver to provide... Agent: Harness, Dickey & Pierce, P.L.C

20070036007 - Sticky bit buffer: A method for programming in parallel reference cells to be used for operating other cells of a memory cell array, the method including: a) reading each of the reference cells of a memory cell array with a sense amplifier, the sense amplifier providing an output indicative of a programmed state... Agent: Tiajoloff & Kelly

20070036009 - Semiconductor memory devices and methods for generating column enable signals thereof: A semiconductor memory device may comprise a column enable signal generator, a row enable signal generator and a final column enable signal generator. The column signal enable generator may generate a latency control signal and generating a buffered clock signal as a column enable signal in response to the latency... Agent: Harness, Dickey & Pierce, P.L.C

20070036010 - Memory apparatus: A memory chip includes a main memory cell; a row-wise redundant memory cell and a column-wise redundant memory cell for relieving a defect existing in the main memory; an identification number designation terminal for storing an identification number corresponding to the main memory cell; an address terminal for receiving the... Agent: Morrison & Foerster LLP

20070036011 - Shared redundant memory architecture and memory system incorporating same: A memory system incorporates shared redundant memories and has a shared redundant memory architecture. The memory system includes a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close... Agent: Hogan & Hartson LLP

20070036012 - Stable source-coupled sense amplifier: An amplifier circuit and method is disclosed. The amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706,708) of the amplifier section are coupled... Agent: Texas Instruments Incorporated

20070036013 - Semiconductor memory with wordline timing: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070036014 - Nonvolatile memory device with multiple references and corresponding control method: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each... Agent: Seed Intellectual Property Law Group PLLC

20070036015 - Semiconductor device temperature sensor and semiconductor storage device: A semiconductor device temperature sensor produces a reference level for temperature detection from two or more reference levels of different temperatures to detect a temperature. The temperature sensor is applied for detecting the temperature of a semiconductor storage device having a memory unit which requires a refresh action. A refresh... Agent: Arent Fox PLLC

20070036016 - Nonvolatile memory cell having current compensated for temperature dependency and data read method thereof: A nonvolatile semiconductor memory device includes a memory cell array, read circuit, program circuit, read voltage generating circuit, memory circuit and switching circuit. The read voltage generating circuit generates and supplies a read voltage to the read circuit. The memory circuit stores information which changes the temperature characteristic of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070036017 - Semiconductor memory device and a refresh clock signal generator thereof: A semiconductor memory device and a refresh clock signal generator thereof are provided. The refresh clock signal generator of the semiconductor memory device includes a voltage generator for receiving a power voltage to generate a voltage which is lower than the power voltage; a ring oscillator enabled in response to... Agent: F. Chau & Associates, LLC

20070036019 - Circuit for selecting a power supply voltage and semiconductor device having the same: A semiconductor memory device capable of reducing the number of pads is provided. The semiconductor memory device may include a pad, a power supply voltage generating circuit and a voltage selection circuit. The power supply voltage generating circuit may generate one or more power supply voltages, which may be used... Agent: Harness, Dickey & Pierce, P.L.C

20070036018 - Semiconductor device and method for driving the same: As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption... Agent: Fish & Richardson P.C.

20070036020 - Bit-deskewing io method and system: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock... Agent: Courtney Staniford & Gregory LLP

20070036021 - Data reprogramming method and system: In a data reprogramming system, a receiving unit receives a plurality of items of data for use in reprogramming. The plurality of items of data are sent to the receiving unit. The plurality of items of data are respectively attached with the same identifier. A data extracting unit verifies the... Agent: Nixon & Vanderhye, PC

20070036023 - Method for detecting data strobe signal: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the... Agent: Rabin & Berdo, PC

20070036022 - Synchronizer for multi-rate input data using unified first-in-first-out memory and method thereof: In a synchronizer for multi-rate input data, a unified FIFO (first-in-first-out) memory receives multi-rate input data, converts the multi-rate input data into a single system operation frequency, and outputs converted data of a plurality of channels of the multi-rate input data, based on the control of a controller.... Agent: F. Chau & Associates, LLC

20070030718 - Magnetic logic system: A driving system and method to effect propagation of a magnetic domain wall through a ferromagnetic conduit are described, wherein oscillating electrical current is passed through the conduit from an oscillating current supply source via at least two electrical contacts adapted to make electrical connection with at least two spaced... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20070030719 - One time programmable memory and method of operation: A one time programmable (OTP) memory has two-bit cells for increasing density. Each cell has two select transistors and a programmable transistor in series between the two select transistors. The programmable transistor has two independent storage locations. One is between the gate and a first source/drain region and the second... Agent: Freescale Semiconductor, Inc. Law Department

20070030720 - Method of dynamically adjusting operation of a memory chip and apparatus of measuring thickness of an ono layer of the memory chip: A method for dynamically adjusting the operation of a memory chip is disclosed. First, a memory chip is provided. The memory chip comprises an ONO layer. Then, the thickness of the ONO layer in the memory chip is measured, and a read word line voltage of the memory chip is... Agent: J C Patents, Inc.

20070030721 - Device selection circuitry constructed with nanotube technology: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon.... Agent: Wilmer Cutler Pickering Hale And Dorr LLP

20070030722 - Memory cell: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070030725 - Apparatus and methods for storing data in a magnetic random access memory (mram): An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments... Agent: Knobbe Martens Olson & Bear LLP

20070030723 - Magnetic memory arrays: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and... Agent: Birch Stewart Kolasch & Birch

20070030724 - Memory element and memory: The present invention provides a memory element including a memory layer that holds information based on a magnetization state of a magnetic substance, and a magnetization pinned layer that is provided for the memory layer with intermediary of an intermediate layer therebetween, the intermediate layer being composed of an insulator.... Agent: Sonnenschein Nath & Rosenthal LLP

20070030728 - High speed low power annular magnetic devices based on current induced spin-momentum transfer: A high speed and low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a... Agent: Darby & Darby P.C.

20070030726 - Magnetic random access memory: A magnetic random access memory includes first write lines separated from one another and extending along a first direction. Second write lines extend in a direction different from the first direction. The MTJ elements are provided between the first write lines and the second write lines. Connection lines connect the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070030727 - Method for switching magnetic moment in magnetoresistive random access memory with low current: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070030732 - Double page programming system and method: A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state.... Agent: Graybeal, Jackson, Haley LLP

20070030733 - Faulty storage area marking and accessing method and system: A faulty storage area marking and accessing method and system applicable to a data storage unit (e.g. an embedded memory integrated in a SoC) having a plurality of storage areas, for providing the data storage unit with an automatic faulty storage area marking function for access control, so as to... Agent: Edwards & Angell, LLP

20070030734 - Reclaiming data storage capacity in flash memories: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where... Agent: Parsons Hsue & De Runtz LLP

20070030735 - Page buffer circuit and method for multi-level nand programmable memories: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or... Agent: Graybeal, Jackson, Haley LLP

20070030736 - Variable source resistor for flash memory: In one embodiment of the invention, a flash memory is provided that includes: a plurality of flash memory cells sharing a common drain node and a common source node; and a current source that controls the current into the common source node.... Agent: Macpherson Kwok Chen & Heid LLP

20070030729 - Method of sensing an eeprom reference cell: An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the... Agent: Schneck & Schneck

20070030730 - Nand flash memory with erase verify based on shorter evaluation time: A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading... Agent: Graybeal Jackson Haley LLP

20070030731 - Non-volatile semiconductor memory device: A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell are connected via a first transistor and a second transistor, respectively. A current mirror type... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070030737 - Nand flash memory cell programming: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070030738 - Technique to suppress leakage current: Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operational mode and the wordline is driven... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070030739 - Method of comparison between cache and data register for non-volatile memory: A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a... Agent: Leffert Jay & Polglaze, P.A.

20070030740 - Semiconductor device and control method of the same: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and... Agent: Wagner, Murabito & Hao LLP

20070030741 - Semiconductor memory device: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto... Agent: Buchanan, Ingersoll & Rooney PC

20070030742 - Combination column redundancy system for a memory array: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070030743 - Semiconductor memory device: A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting... Agent: F. Chau & Associates, LLC

20070030744 - Semiconductor memory device: Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number... Agent: Stevens, Davis, Miller & Mosher, LLP

20070030745 - Referencing scheme for trap memory: A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged... Agent: Stephen B. Ackerman

20070030747 - Data recording device: An data recording device according to an aspect of the present invention includes a memory cell array in a memory chip, a refresh circuit which executes a refreshing of the memory cell array, a refresh control circuit which executes refreshing at a time interval which is shorter than a data... Agent: Nixon & Vanderhye, PC

20070030746 - Memory device testing to support address-differentiated refresh rates: A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are... Agent: Shemwell Mahamedi LLP

20070030748 - Bit line sense amplifier and method thereof: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line... Agent: Harness, Dickey & Pierce, P.L.C

20070030749 - Voltage down converter for high speed memory: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current.... Agent: Borden Ladner Gervais LLP

20070030750 - Low power memory sub-system architecture: Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies,... Agent: Perkins Coie LLP Patent-sea

20070030751 - Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070030752 - Programmable strength output buffer for rdimm address register: A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable... Agent: Koppel, Patrick & Heybl

20070030755 - Apparatus for testing a nonvolatile memory and a method thereof: An apparatus for testing or programming a nonvolatile memory in a micro control system and a method thereof is provided. The micro control system comprises: a nonvolatile memory for storing data; an address register for storing an address; a data register for storing serial data; control logic for controlling the... Agent: F. Chau & Associates, LLC

20070030754 - Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector: A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty cycle irrespective of the duty cycle of the clock input to the DCC circuit. A DCC initialization scheme selectively activates the frequency division and... Agent: Jones Day

20070030753 - Seamless coarse and fine delay structure for high performance dll: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and... Agent: Jones Day

20070030756 - Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same: Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the... Agent: Marger Johnson & Mccollom, P.C.

20070025132 - Dual port cell structure: Disclosed are improved layouts for memory cell and memory cell arrays. A memory cell array of multiple memory cells connected by signal lines that twist in connecting the array. Further, an eight transistor memory cell that comprises different resistive paths as seen by the signal lines electrically connected to the... Agent: Haynes And Boone, LLP

20070025131 - Semiconductor memory module and system: The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the... Agent: Edell, Shapiro & Finnan, LLC

20070025133 - System and method for optical interconnecting memory devices: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070025134 - Flexible otp sector protection architecture for flash memories: A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds... Agent: Sawyer Law Group LLP

20070025135 - Method and apparatus for regulating state of charge in battery assemble: A CPU 52 detects respective voltages across unit cells B1 to Bn and extracts a minimum unit cell having a minimum voltage from the plurality of unit cells B1 to Bn based on the detected voltages. The CPU 52 sets one of cell groups each including two unit cells connected... Agent: Sughrue Mion, PLLC

20070025136 - Ferroelectric random access memory circuits for guarding against operation with out-of-range voltages and methods of operating same: A method of operating a ferroelectric random access memory (FRAM) can include reading a low-voltage FRAM monitoring memory array and preventing a read/write-back of an FRAM memory cell array if data read from the low-voltage FRAM monitoring memory array is corrupted.... Agent: Myers Bigel Sibley & Sajovec

20070025137 - Dynamic memory word line driver scheme: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070025139 - Nano-structured photovoltaic solar cell and related methods: A solar cell includes a substrate having a horizontal surface, and an electrode layer on the substrate. The electrode has a plurality of vertical surfaces substantially perpendicular to the horizontal surface, and light-harvesting rods are coupled to the vertical surface of the electrode.... Agent: Myers Bigel Sibley & Sajovec

20070025138 - Non-volatile switching and memory devices using vertical nanotubes: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.... Agent: Schmeiser, Olsen & Watts

20070025142 - Loadless sram: A loadless static random access memory (SRAM) may have transfer transistors with at least two threshold voltages. In some embodiments, the transfer transistors may have gate structures with different portions that produce electric fields in different directions. In some embodiments the transfer gate structures may extend down the sidewalls of... Agent: Marger Johnson & Mccollom, P.C.

20070025143 - Semiconductor device: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler, Ltd.

20070025140 - Sram cell with independent static noise margin, trip voltage, and read current optimization: An SRAM memory cell structure utilizing a read driver transistor for isolating the read current from the latch nodes of the cell during read operations and a column select write transistor for selection of a single cell during write operations, and a method of operating the same is discussed. The... Agent: Texas Instruments Incorporated

20070025141 - Sram, semiconductor memory device, and method for maintaining data in sram: An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from being destructed by a latch-up phenomenon to maintain the stored data certainly even when a soft... Agent: Staas & Halsey LLP

20070025144 - Write operations for phase-change-material memory: Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated... Agent: Ryan, Mason & Lewis, LLP

20070025145 - Non-volatile memory cell using high-k material and inter-gate programming: A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material.... Agent: Vierra Magen/sandisk Corporation

20070025149 - Nonvolatile semiconductor memory device: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701

20070025150 - Flash memory device capable of preventing program disturbance according to partial programming: A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is divided into two electrically isolated word lines that are arranged in the column regions. The memory device further includes... Agent: Marger Johnson & Mccollom, P.C.

20070025151 - Flash memory device capable of storing multi-bit data and single-bit data: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory... Agent: Volentine Francos, & Whitt PLLC

20070025152 - Nonvolatile semiconductor memory device and a method for programming nand type flash memory: A non-volatile semiconductor memory device comprise a memory cell array having a plurality of memory cell units each having a plurality of electrically-programmable memory cell connected in series, a plurality of word lines each connected to each of control gates of said plurality of memory cells, said plurality of word... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070025153 - Method of operating non-volatile memory device: A method of operating a non-volatile memory is provided, wherein the non-volatile memory at least includes: a gate structure formed by stacking a tunneling dielectric layer, charge trapping layer, a dielectric layer and a gate conducting layer sequentially, and a source region and a drain region. When the operating method... Agent: Jianq Chyun Intellectual Property Office

20070025154 - Semiconductor device and method of controlling the same: A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array;... Agent: Mavis S. Gallenson C/o Ladas & Parry

20070025155 - Method and apparatus for controlling slope of word line voltage in nonvolatile memory device: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences... Agent: Volentine Francos, & Whitt PLLC

20070025156 - System for programming non-volatile memory with self-adjusting maximum program loop: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level,... Agent: Vierra Magen/sandisk Corporation

20070025147 - Non-volatile semiconductor memory device: Charge is trapped into a charge trapping region of one of two reference cells so as to achieve a state equivalent to memory cell characteristics having a smallest amount of current. Charge is trapped into a charge trapping region of the other reference cell so as to achieve a state... Agent: Mcdermott Will & Emery LLP

20070025148 - Semiconductor memory device with a page buffer having an improved layout arrangement: A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer adapted to interface the matrix with a downstream circuitry, the page buffer comprising... Agent: Seed Intellectual Property Law Group PLLC

20070025146 - Sensing circuit for multi-level flash memory: A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number... Agent: Birch Stewart Kolasch & Birch

20070025157 - Method for programming non-volatile memory with self-adjusting maximum program loop: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level,... Agent: Vierra Magen/sandisk Corporation

20070025158 - Semiconductor memory device and related programming method: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein... Agent: Volentine Francos, & Whitt PLLC

20070025159 - Non-volatile memory device having improved program speed and associated programming method: A non-volatile memory device comprises a memory cell array having a plurality of non-volatile memory cells arranged in rows and columns. Selected memory cells are programmed by applying program voltages thereto. Next, data bits stored in the selected cells are read. Then, a first column scan operation is performed to... Agent: Volentine Francos, & Whitt PLLC

20070025160 - Channel discharging after erasing flash memory devices: A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate... Agent: Schneck & Schneck

20070025161 - 3-level non-volatile semiconductor memory device and method of driving the same: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch... Agent: Marger Johnson & Mccollom, P.C.

20070025163 - Maintaining internal voltages of an integrated circuit in response to a clocked standby mode: A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of the memory device is received. If the signal indicates that the memory device is in the clocked standby... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070025162 - Sram cell with column select line: An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a... Agent: Texas Instruments Incorporated

20070025165 - Charge pump for programmable semiconductor memory: A depletion type active capacitor may transfer charge from an oscillator to an address line that needs to be boosted for programming. Such a charge pump may be useful in semiconductor memories such as flash memories, EEPROM memories, and NAND EEPROM memories. In some embodiments, relatively low supply voltages can... Agent: Trop Pruner & Hu, PC

20070025164 - Voltage generating circuit, semiconductor memory device comprising the same, and voltage generating method: A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final... Agent: F. Chau & Associates, LLC

20070025167 - Method for testing a memory device, test unit for testing a memory device and memory device: A method, a memory device and a test unit to test such memory device is provided. The memory device comprises a memory cell array including a multitude of memory cells each having a variable characteristic. The method comprises identifying the characteristic of each memory cell and assigning memory cells of... Agent: Slater & Matsil LLP

20070025168 - Method for testing memory device: Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short time period, thereby reducing the test time. The method for testing a memory device... Agent: Ladas & Parry LLP

20070025166 - Program/erase waveshaping control to increase data retention of a memory cell: System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell... Agent: Amin, Turocy & Calvin, LLP

20070025169 - Memory array with a delayed wordline boost: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a... Agent: Texas Instruments Incorporated

20070025170 - Differential and hierarchical sensing for memory circuits: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal... Agent: Ryan, Mason & Lewis, LLP

20070025171 - Semiconductor memory device: In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential... Agent: Mcdermott Will & Emery LLP

20070025172 - Memory: A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the... Agent: Mcdermott Will & Emery LLP

20070025173 - Memory device and method having multiple address, data and command buses: A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070025174 - Dual port semiconductor memory device: A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors... Agent: Marger Johnson & Mccollom, P.C.

20070025175 - Reducing read data strobe latency in a memory system: A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another.... Agent: Ryan, Mason & Lewis, LLP