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Static information storage and retrieval January USPTO class patent listing 01/07

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
01/25/2007 > 44 patent applications in 28 patent subcategories. USPTO class patent listing

20070019454 - Glitch protect valid cell and method for maintaining a desired state value: A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid.... Agent: Ibm Corp. (rvb) C/o The R. Baca Law Firm, PLLC

20070019455 - Programmable priority encoder: A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated... Agent: Stmicroelectronics, Inc

20070019456 - Semiconductor device and short circuit detecting method: A short circuit detection region includes an insulating film, plural first conductor traces and plural second conductor traces which are embedded in the insulating film with only their surfaces being exposed, and the first conductor trace is constructed by integrally forming a band-shaped portion and plural via portions which are... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070019457 - Semiconductor memory device: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read... Agent: Stanley P. Fisher Reed Smith LLP

20070019458 - Input component: In the present invention, an input component is provided. The input component includes a first area performing a first function while pressed with an external force, and a second area disposed around the first area and performing a second function while the first and the second areas simultaneously pressed with... Agent: Volpe And Koenig, P.C.

20070019459 - Memory: A memory capable of reducing the memory cell size is provided. This memory comprises a plurality of memory cells including diodes, a plurality of bit lines and an n-type impurity region arranged to intersect with the bit lines for functioning as cathodes of the diodes included in the memory cells... Agent: Mcdermott Will & Emery LLP

20070019460 - Nonvolatile latch circuit and system on chip with the same: A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time. The nonvolatile latch circuit does not require an additional data storage period but... Agent: Heller Ehrman White & Mcauliffe LLP

20070019461 - Methods and apparatus for accessing memory: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to... Agent: Leslie J. Payne, Attorney IBM Corporation

20070019462 - Magnetic memory cell, magnetic memory device, and magnetic memory device manufacturing method: The present invention provides a magnetic memory device capable of reducing a loss of a magnetic field generated by currents flowing in a write line and performing writing stably, and a magnetic memory cell mounted on the magnetic memory device. Further, the invention provides a method for easily manufacturing such... Agent: Oliff & Berridge, PLC

20070019464 - Magnetic memory device: A magnetic memory device includes a plurality of storage cells disposed in two dimensions, read lines that supply a read current for reading information from a first power supply to the respective storage cells, and a second power supply that is connected to at least some of the read lines... Agent: Greenblum & Bernstein, P.L.C

20070019463 - Magnetoresistive effect element and magnetic memory: It is made possible to provide a highly reliable magnetoresistive effect element and magnetic memory that operate with low power consumption and low current writing. The magnetoresistive effect element includes: a magnetization free layer including at least two magnetic layers subject to antiferromagnetic coupling and a non-magnetic layer provided between... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070019465 - Detecting switching of access elements of phase change memory cells: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition... Agent: Trop Pruner & Hu, PC

20070019466 - Magnetic random access memory and method for manufacturing the same: A magnetic random access memory is provided including a substrate, a magnetoresistance element which includes a ferromagnetic layer having an invertible spontaneous magnetization, which varies in resistance according to the direction of the spontaneous magnetization, and is formed above the substrate, and a wiring which extends in a first direction... Agent: Sughrue Mion, PLLC

20070019468 - Page buffer circuit with reduced size and methods for reading and programming data with the same: A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the... Agent: Townsend And Townsend And Crew, LLP

20070019469 - Read-out circuit in semiconductor memory device: A read-out circuit comprises a read-out voltage generator circuit converting a memory cell current into a read-out voltage, a reference voltage generator circuit supplying a reference memory cell corresponding to each memory state intermediate between multilevel data with a reference current from a reference loading circuit and converting the reference... Agent: Morrison & Foerster LLP

20070019470 - Systems and methods for improved programming of flash based devices: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device... Agent: Baker & Mckenzie LLP Patent Department

20070019473 - Apparatus and method for improving write/read endurance of non-volatile memory: An apparatus for improving write/read endurance of non-volatile memory includes a non-volatile memory area including a plurality of non-volatile memory cells to store data, and an endurance improving circuit detecting a degradation characteristic of the non-volatile memory cells upon the integrated circuit card being reset and initialized. The apparatus increases... Agent: F. Chau & Associates, LLC

20070019472 - Electronic device including a memory array and conductive lines: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of... Agent: Larson Newman Abel Polansky & White, LLP

20070019475 - Method and apparatus for programming single-poly pfet-based nonvolatile memory cells: Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection... Agent: Impj - Thelen Reid & Priest LLP Thelen Reid & Preiest LLP

20070019476 - Method and apparatus for programming single-poly pfet-based nonvolatile memory cells: Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection... Agent: Impj - Thelen Reid & Priest LLP Thelen Reid & Preiest LLP

20070019477 - Method and apparatus for programming single-poly pfet-based nonvolatile memory cells: Methods and apparatuses for programming a single-poly pFET-based nonvolatile memory cell bias the cell so that band-to-band tunneling (BTBT) is induced and electrons generated by the BTBT are injected onto a floating gate of the cell. Following a predetermined event, the single-poly pFET is biased to induce impact-ionized hot-electron injection... Agent: Impj - Thelen Reid & Priest LLP Thelen Reid & Preiest LLP

20070019474 - Methods/circuits for programming flash memory devices using overlapping bit line setup and word line enable intervals: A method of programming a flash memory device includes charging selection lines with a first voltage while applying program data to bit lines to during a bit line setup interval, then activating a block word line to electrically connect the selection lines to corresponding word lines, and then applying a... Agent: Myers Bigel Sibley & Sajovec

20070019471 - Reduction of programming time in electrically programmable devices: A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is to be applied to the bit cell,... Agent: Schneck & Schneck

20070019467 - Semiconductor memory device: A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070019478 - Method of writing to non-volatile semiconductor memory device storing information depending on variation in level of threshold voltage: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low... Agent: Mcdermott Will & Emery LLP

20070019479 - Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions: A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at... Agent: Harness, Dickey & Pierce, P.L.C

20070019480 - Test circuitry and testing methods: A memory device compares, within the memory device, a signal indicative of a current drawn by one or more select lines to a reference signal, and indicates whether the signal indicative of the current drawn by the one or more select lines exceeds the reference signal.... Agent: Leffert Jay & Polglaze, P.A. Attn: Tod A. Myrum

20070019482 - Method for detecting data strobe signal: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the... Agent: Rabin & Berdo, PC

20070019481 - Semiconductor memories with block-dedicated programmable latency register: An apparatus and method to delay output of data from different regions of a memory device in response to a read enable signal, the delaying of the output of data is based on the location of the regions of the memory device with respect to an output circuit that receives... Agent: Stanzione & Kim, LLP

20070019483 - Redundancy selector circuit for use in non-volatile memory device: A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up;... Agent: Volentine Francos, & Whitt PLLC

20070019484 - Memory device and method for improving speed at which data is read from non-volatile memory: A memory device and method for improving speed at which data is read from non-volatile memory are provided, where the memory device including the non-volatile memory precharges all word lines with a predetermined precharge voltage during standby for a read operation, in which data is read from the non-volatile memory,... Agent: F. Chau & Associates, LLC

20070019485 - Semiconductor memory: Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is... Agent: Mcdermott Will & Emery LLP

20070019486 - High speed array pipeline architecture: A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being... Agent: Jones Day

20070019487 - Reference current generator: In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first transistor is coupled to the referent branch, a second transistor is coupled to the mirror branch... Agent: Rosenberg, Klein & Lee

20070019489 - Disabling clocked standby mode based on device temperature: A method and apparatus for controlling a voltage generator of a memory device are provided. A temperature of the memory device is measured. If the measured temperature is outside a threshold temperature range, the memory device is allowed to be placed in a clocked standby mode (CSM), whereby the voltage... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070019488 - Temperature update masking to ensure correct measurement of temperature when references become unstable: Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature measurement is received. A determination is made of whether the clocked standby... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070019490 - Semiconductor memory device: In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential... Agent: Mcdermott Will & Emery LLP

20070019491 - Refresh control circuit and method for performing a repetition refresh operation and semiconductor memory device having the same: A refresh control circuit and semiconductor devices that may include an address counter for generating a counting address, a repetition address selector for generating a repetition address, a repetition refresh controller for generating a refresh repetition signal based on the counting address and repetition address, and a row decoder for... Agent: Harness, Dickey & Pierce, P.L.C

20070019492 - Integrated electronic device having a low voltage electric supply: A low supply voltage memory device includes a first supply pin and a second supply pin for the connection to a first supply voltage source (VDD) and to a second supply voltage source (VDDQ). The device may include a memory and at least one booster overlapped by way of a... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070019493 - Semiconductor integrated circuit: The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage... Agent: Stanley P. Fisher Reed Smith LLP

20070019494 - Semiconductor memory module with bus architecture: A semiconductor memory module comprises a control chip that drives various memory chips on a circuit board. The memory chips are connected to the control chip via a control clock bus in a loop fly-by topology. The memory chips are arranged on the module circuit board in such a way... Agent: Edell, Shapiro & Finnan, LLC

20070019495 - Address decoding systems and methods: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal.... Agent: Macpherson Kwok Chen & Heid LLP

20070019497 - Semiconductor memory device: In a semiconductor memory device 10, the maximum counter value in a carry-up unit 111 of an address counter 110 is set to 128 bits when an access request is for writing data to a memory array 100. On the other hand, in the semiconductor memory device 10, if the... Agent: Stroock & Stroock & Lavan LLP

20070019496 - Semiconductor memory device for stably controlling power mode at high frequency and method of controlling power mode thereof: The present invention relates to a semiconductor memory device. When a device exits from power mode, after a time until an instruction/address receive control signal substantially turns on or off an address and instruction input buffer unit and a time until the address and instruction buffer unit is turned on... Agent: Mayer, Brown, Rowe & Maw LLP

  
01/18/2007 > 49 patent applications in 34 patent subcategories. USPTO class patent listing

20070014136 - Apparatus, system, and method for accessing persistent files in non-execute-in-place flash memory: Persistent files stored in non-XIP flash memory are accessed during operation of an electronic device. During execution of application code on the device, the persistent files are accessed using an access directory such as a look-up table. The access directory provides information that allows an application or other software code... Agent: Kyocera Wireless Corp.

20070014137 - Banked cache with multiplexer: Systems and methods associated with cache banking are described. One exemplary system embodiment includes an array that is physically banked into multiple banks. While inputs may be provided to the banked array at a first rate, an array access may take more than one cycle at that first rate to... Agent: Hewlett Packard Company

20070014139 - Compare circuit for a content addressable memory cell: A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current.... Agent: Borden Ladner Gervais LLP

20070014138 - Content addressable memory structure: A content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.... Agent: Greenblum & Bernstein, P.L.C

20070014141 - Layout for distributed sense amplifier driver in memory device: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each... Agent: Volentine Francos, & Whitt PLLC

20070014140 - Nonvolatile semiconductor memory apparatus: A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The... Agent: Schneck & Schneck

20070014142 - Flat-cell read-only memory structure: The integrated circuit memory comprises a memory array including a plurality of memory cells in rows and columns, the memory array being divided into a plurality of blocks of the memory cells. Each of the blocks includes a plurality of word lines arranged along the rows and coupled to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070014143 - Magnetic spin valve with a magnetoelectric element: The present invention provides systems and method utilizing magnetoelectric materials such as Cr2O3 to construct tunneling magnetoresistence and/or giant magnetoresistence structures for memory and/or logical circuitry. An applied voltage differential induces a magnetic moment in the magnetoelectric material, which in turn tunes an exchange field between it and one or... Agent: Shook, Hardy & Bacon LLP Intellectual Property Department

20070014144 - Method of operating a programmable resistance memory array: A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include phase-change materials such as chalcogenides.... Agent: Philip Schlazer Energy Conversion Devices, Inc.

20070014145 - Nonvolatile memory circuit based on change in mis transistor characteristics: A memory circuit includes a latch having a first node and a second node, a plate line, a word selecting line, a first MIS transistor having source/drain nodes thereof coupled to the first node and the plate line, respectively, and a gate node thereof coupled to the word selecting line,... Agent: Ladas & Parry LLP

20070014149 - Magnetoresistive element: A magnetoresistive element includes a first magnetic layer which includes a first surface and a second surface and has a first standard electrode potential, a second magnetic layer, a barrier layer which is provided between the second magnetic layer and the first surface of the first magnetic layer, and a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070014146 - Method of forming super-paramagnetic cladding material on conductive lines of mram devices: A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite... Agent: Stephen B. Ackerman

20070014148 - Methods and systems for attaching a magnetic nanowire to an object and apparatuses formed therefrom: Methods and systems are provided for attaching one or magnetic nanowires to an object and apparatuses formed therefrom. An electrophoresis method for attaching one or more nanowires to a sharp tip of an object can include including providing one or more magnetic nanowires in a liquid medium. The method can... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070014147 - Power consumption minimization in magnetic random access memory by using the effect of hole-mediated ferromagnetism: A low-power memory device that uses hole-mediated ferromagnetism creates substantial advantages over conventional systems. Some of these advantages include reducing power consumption by several orders of magnitude and facilitating wireless monitoring of memory cells. In one implementation, an electronic device is described that includes a plurality of memory cells. Each... Agent: Needle & Rosenberg, P.C.

20070014150 - Phase change random access memory (pram) device having variable drive voltages: A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a... Agent: Volentine Francos, & Whitt PLLC

20070014151 - Nanotube-and nanocrystal-based non-volatile memory: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write... Agent: Blakely Sokoloff Taylor & Zafman

20070014152 - Semiconductor memory device capable of increasing writing speed: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070014153 - Pipelined programming of non-volatile memories using early data: The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can... Agent: Parsons Hsue & De Runtz LLP

20070014154 - Flat-cell read-only memory: In a flat-cell ROM including a plurality of memory banks, each of the memory banks comprises a memory array, a plurality of bit lines, a plurality of virtual ground lines, three select lines, and a common row of contacts shared with an adjacent memory bank. The common row of contacts... Agent: Rosenberg, Klein & Lee

20070014155 - Method for controlling nonvolatile memory device: Data is written to a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain with an improved accuracy. The nonvolatile memory device includes four control gates provided between a first and a second impurity-diffused regions that... Agent: Young & Thompson

20070014156 - Non-volatile memory and method with power-saving read and program-verify operations: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation... Agent: Parsons Hsue & De Runtz LLP

20070014157 - Semiconductor device including memory cells and current limiter: A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070014158 - Flash memory device with improved programming performance: A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin

20070014159 - Under voltage protection device: An under voltage protection device is for cooperating with a fan. The under voltage protection device includes a voltage detective unit and a starting unit. The voltage detective unit is for receiving an input voltage and a reference voltage. The starting unit is electrically connected to the voltage detective unit... Agent: Birch Stewart Kolasch & Birch

20070014160 - Non-volatile semiconductor memory: A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of “0”s are stored into the second memory area, and... Agent: Dickstein Shapiro LLP

20070014161 - Non-volatile memory and method with power-saving read and program-verify operations: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation... Agent: Parsons Hsue & De Runtz LLP

20070014162 - Nonvolatile memory device including circuit formed of thin film transistors: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.... Agent: Mcdermott Will & Emery LLP

20070014163 - Nand flash memory devices and methods of lsb/msb programming the same: Multiple bits are programmed in a NAND flash memory device by programming a memory cell with an LSB; storing the LSB into a cache register from the memory cell; programming the memory cell with an MSB that is stored in a main register; storing a data bit into the main... Agent: Myers Bigel Sibley & Sajovec

20070014164 - Data latch controller of synchronous memory device: Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the... Agent: Ladas & Parry LLP

20070014165 - Column redundancy reuse in memory devices: A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy column and an addressable second redundancy column. A first column array... Agent: Slater & Matsil LLP

20070014166 - Redundancy power for communication devices: A system and method to provide redundant power to a failing line in a communication device within a communication network supporting the transmission and reception of data. Through the use of a common Y-Cable connector, a power switch is provided to provide power between an active line and a standby... Agent: Wagner, Murabito & Hao, LLP

20070014167 - Semiconductor memory device with reduced multi-row address testing: A semiconductor memory device and multi-row address test method reduce the time it takes to perform the multi-row address test. The semiconductor memory device comprises normal memory cell blocks, which can include normal memory cells and spare cells that replace defective cells. The device also includes a redundancy signal generator... Agent: Mills & Onello LLP

20070014168 - Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells).... Agent: Stattler Johansen & Adeli LLP

20070014169 - Semiconductor memory device and semiconductor integrated circuit: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070014170 - Negative voltage discharge scheme to improve snapback in a non-volatile memory: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The... Agent: Dickstein Shapiro LLP

20070014171 - Semiconductor memory device: A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first sense amplifier in... Agent: Mcdermott Will & Emery LLP

20070014172 - Memory device capable of performing high speed reading while realizing redundancy replacement: When normal bit lines BL3 and /BL3 are selected, spare bit lines SBL2 and /SBL2 are simultaneously selected, so that column select gates are placed in such a manner that these bit line pairs are connected to respective different read data bus pairs. The column select gates are distributed in... Agent: Burns, Doane, Swecker & Mathis, L.L.P.

20070014173 - Energy adjusted write pulses in phase-change memories: A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generator generates a write pulse for the plurality... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070014175 - Dram and method for partially refreshing memory cell array: A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first... Agent: Mills & Onello LLP

20070014174 - Semiconductor memory device: A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070014176 - Accurate power supply system for flash-memory including on-chip supply voltage regulator, reference voltage generation, power-on reset, and supply voltage monitor: The supply voltage of an on-chip flash memory is regulated with two feedback loops. One loop comprises the flash memory, a register, and a voltage regulator with bandgap reference to regulate the supply voltage. The other loop comprises the flash memory, another register, an amplifier with bandgap reference, and comparators... Agent: George O. Saile

20070014177 - Apparatus and method for supplying power voltages in active and stand-by modes: A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and... Agent: Law Office Of Monica H Choi

20070014178 - Semiconductor memory device, and method of controlling the same: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage... Agent: Arent Fox PLLC

20070014180 - Device and method for selecting 1-row and 2-row activation: I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lower local lines in corresponding rows of memory... Agent: Marger Johnson & Mccollom, P.C.

20070014179 - Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.... Agent: Schneck & Schneck

20070014181 - Semiconductor memory device having connected bit lines and data shift method thereof: Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks each including a plurality of bit lines and a plurality of word lines, a plurality of sense amplifier blocks respectively... Agent: Marger Johnson & Mccollom, P.C.

20070014183 - Nonvolatile semiconductor memory device in which write and erase threshold voltages are set at levels symmetrical about neutral threshold voltage of cell transistor: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070014182 - Nonvolatile semiconductor memory device which reads by decreasing effective threshold voltage of selector gate transistor: A semiconductor device includes memory cells and a driver. Each memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070014184 - Wordline decoder of non-volatile memory device using hpmos: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and... Agent: Marger Johnson & Mccollom, P.C.

  
01/11/2007 > 49 patent applications in 34 patent subcategories. USPTO class patent listing

20070008758 - Time domain bridging circuitry for use in determining output enable timing: A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such variable delays, is disclosed. In one embodiment, a first time... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070008760 - Highly integrated ternary semiconductor memory device: A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged... Agent: Mcdermott Will & Emery LLP

20070008759 - Method and apparatus for interconnecting content addressable memory devices: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host... Agent: Borden Ladner Gervais LLP

20070008761 - Memory architecture and method of manufacture and operation thereof: An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a... Agent: Dickstein Shapiro LLP

20070008762 - Giant magnetoresistance sensor with side longitudinal bias stacks and method for forming same: A giant magnetoresistance (GMR) sensor with side longitudinal bias (LB) stacks is proposed for magnetic recording at ultrahigh densities. The GMR sensor extends from a read region into two side regions. The side LB stacks overlies the GMR sensor in the two side regions, rigidly pinning sense layers through antiparallel... Agent: Zilka-kotab, PC

20070008763 - Memory module and memory system having the same: A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The memory module also comprises of a plurality of chip select pin terminals configured to... Agent: Volentine Francos, & Whitt PLLC

20070008764 - Circuit for addressing a memory: A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can be fed a write reset pulse... Agent: Thomson Licensing Inc.

20070008765 - Ferroelectric random access memory: Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one-end side in a column direction every four cell blocks sequentially adjacent to each other... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070008767 - Ferroelectric random access memory device, display drive ic and electronic equipment: A ferroelectric memory device being short in the bit line direction. The ferroelectric memory device is structured including a first word line extending in the first direction; a plurality of element regions arrayed in the first direction on both sides of the first word line; a plurality of ferroelectric capacitors... Agent: Harness, Dickey & Pierce, P.L.C

20070008766 - Ferroelectric storage device: A ferroelectric storage device includes a ferroelectric capacitor C1, a bit line BL, a first switching element 103 selectively connecting the ferroelectric capacitor C1 and the bit line BL, a first transistor 203 connected to the bit line BL and to a reference potential, a reference ferroelectric capacitor CR1, a... Agent: Arent Fox PLLC

20070008769 - Phase-changeable memory device and method of programming the same: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by... Agent: Mills & Onello LLP

20070008768 - Process for erasing chalcogenide variable resistance memory bits: A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate with an n-well and a chalcogenide variable resistance memory element. The method includes the step of applying to the variable resistance memory element a voltage that is less... Agent: Dickstein Shapiro LLP

20070008770 - Storage devices and semiconductor devices: The present invention provides a storage device including a storage element, a circuit element, and write control means. The storage element has a characteristic exhibiting a resistance changing from a large value to a small value due to application of an electrical signal at least equal to a first threshold... Agent: Sonnenschein Nath & Rosenthal LLP

20070008771 - Tracking circuit for a memory device: A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070008772 - Thin film magnetic memory device having redundant configuration: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory celf columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is... Agent: Mcdermott Will & Emery LLP

20070008773 - Nonvolatile memory cell comprising switchable resistor and transistor: A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in... Agent: Matrix Semiconductor, Inc.

20070008774 - Phase change memory device and method of fabricating the same: A phase change memory device and a method of fabricating the same. The phase change memory device may include a lower electrode which is electrically connected to a transistor formed on a semiconductor substrate, a first insulation layer which covers the lower electrode and the substrate and has a first... Agent: Harness, Dickey & Pierce, P.L.C

20070008776 - Three-dimensional non-volatile sram incorporating thin-film device layer: A shadow RAM or “non-volatile SRAM” memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an SRAM cell, a smaller cell can be provided and result in a lower cost memory device. In certain... Agent: Zagorin O'brien Graham LLP

20070008778 - Methods for operating semiconductor device and semiconductor memory device: Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport... Agent: Chih-hsin Wang

20070008777 - Non-volatile memory cell and operating method thereof: A non-volatile memory is described. The non-volatile memory includes a first source/drain region, a second source/drain region, a charge-trapping layer and a gate layer. The first source/drain region is disposed beside the top sidewall of a trench in a substrate. The second source/drain region is disposed in the substrate at... Agent: Jianq Chyun Intellectual Property Office

20070008779 - Semiconductor memory device: A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same well region, each memory cell having a floating gate and a control gate stacked, said serially connected memory... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070008780 - Circuit and method of driving a word line: A word line driving circuit, which may include a read voltage generator and a word line driver. The read voltage generator may precharge a clamp capacitor with a power supply voltage to stably generate a read voltage in response to a read command. A capacitance of the clamp capacitor may... Agent: Harness, Dickey & Pierce, P.L.C

20070008781 - Non-volatile semiconductor memory device: Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing... Agent: Mcdermott Will & Emery LLP

20070008782 - Method for programming a memory device: A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a... Agent: Harrity & Snyder, L.L.P.

20070008783 - Erase verify for non-volatile memory: A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is... Agent: Fogg Slifer & Polglaze, P.A. Attn: Russell D. Slifer

20070008775 - Memory architecture with enhanced over-erase tolerant control gate scheme: The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and... Agent: Schneck & Schneck

20070008785 - Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements: A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a... Agent: Zagorin O'brien Graham LLP

20070008786 - Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements: A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a... Agent: Zagorin O'brien Graham LLP

20070008784 - Two-bit per i/o line write data bus for ddr1 and ddr2 operating modes in a dram: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge... Agent: Hogan & Hartson LLP

20070008789 - Control circuit for stable exit from power-down mode: A power-down mode exit control circuit enables a memory device to exit from an initially set power-down mode state using a clock enable signal. Specifically, although a clock enable signal is inputted in an unstable state at an initial operation indicating that a supply of a supply voltage is started,... Agent: Blakely Sokoloff Taylor & Zafman

20070008787 - Output circuit and method thereof: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the... Agent: Harness, Dickey & Pierce, P.L.C

20070008788 - Reducing dq pin capacitance in a memory device: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT... Agent: Jones Day

20070008790 - Optical brighteners for display panels: A laminated panel for use as a display panel has a polystyrene plastic core and a cellulosic surface on each face of the core. The surface layers are impregnated with a resin formulation containing an optical brightener, and optionally a dye, and then pressed onto each face of the core... Agent: Ratnerprestia

20070008791 - Dqs strobe centering (data eye training) method: A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a... Agent: Lsi Logic Corporation

20070008792 - Circuitry and method for adjusting signal length: A circuit for adjusting a signal length is adapted for a memory device. The circuit adjusts a signal length of an ATD signal. The circuit includes a timing module, an encoding module and a logical control unit. Wherein, the timing module generates a plurality of timing signals according a pulse... Agent: J C Patents, Inc.

20070008793 - Semiconductor apparatus: Disclosed is an apparatus for detecting power supply dependency and process dependency of a delay circuit to enable control of the delay of the delay circuit and operation acceleration/deceleration. The apparatus includes a first delay circuit receiving a first signal and delaying the first signal received by a preset delay... Agent: Foley And Lardner LLP Suite 500

20070008794 - 256 meg dynamic random access memory: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are... Agent: One Mellon Center Suite 3100

20070008795 - Current limit circuit and semiconductor memory device: A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied;... Agent: Mcdermott Will & Emery LLP

20070008796 - Device and method for regulating the threshold voltage of a transistor: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070008797 - Data input and data output control device and method: A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.... Agent: Harness, Dickey & Pierce, P.L.C

20070008799 - Semiconductor device: In a semiconductor device, an internally-generated power supply voltage VPP is monitored. If the internally-generated power supply voltage VPP is lower than a lower limit voltage, serial refresh is selected as a double refresh operation mode. In the serial refresh, double refresh for a pair address is inserted in a... Agent: Sughrue Mion, PLLC

20070008798 - Temperature dependent self-refresh module for a memory device: A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070008800 - Antifuse capacitor for configuring integrated circuits: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor.... Agent: Okamoto & Benedicto, LLP

20070008802 - Dynamic random access memory and communications terminal including the same: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.... Agent: Volentine Francos, & Whitt PLLC

20070008801 - Memory card and control chip capable of supporting various voltage supplies and method of supporting voltages thereof: A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages thereof are provided. The memory card comprises a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070008803 - Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with: A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status. of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.... Agent: Hogan & Hartson L.L.P.

20070008804 - High voltage wordline driver with a three stage level shifter: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also... Agent: Howard Chen Preston Gates & Ellis LLP

20070008805 - Circuit and method of driving a word line of a memory device: A word line driving circuit may include a first word line driver, a second word line driver and a pass transistor. In response to a word line selecting signal, the first word line driver may drive a word line using a first word line driving voltage signal in a first... Agent: Harness, Dickey & Pierce, P.L.C

20070008806 - Word line decoder suitable for low operating voltage of flash memory device: Provided is a word line decoder suitable to a low operating voltage of a flash memory device. The word line decoder generates a block word line driving signal of a high voltage in response to a block selection signal. The word line decoder includes a first inverter receiving the block... Agent: Mills & Onello LLP

20070008807 - Wordline driver: The present invention describes systems and method for driving wordlines of memory devices. Some embodiments include a selection signal driver to generate a selection signal responsive to a first wordline signal, a main wordline driver to generate a main wordline signal responsive to a second wordline signal, the selection signal... Agent: Marger Johnson & Mccollom, P.C.

20070008808 - Dram memory: A DRAM memory comprises a memory cell bank comprised of memory cells being activated by means of internal row and column access instructions, a command decoder generating, dependent on an external memory access instruction, at least one column access instruction within a first and at least one row access instruction... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070008809 - Semiconductor memory device having different synchronzing timings depending on the value of cas latency: A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver is provided. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal... Agent: Mills & Onello LLP

20070008810 - Clock-independent mode register setting methods and apparatuses: Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the... Agent: Harness, Dickey & Pierce, P.L.C

20070008811 - 256 meg dynamic random access memory: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are... Agent: Jones Day

  
01/04/2007 > 49 patent applications in 34 patent subcategories. USPTO class patent listing
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