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Static information storage and retrieval December patent applications/inventions, industry category 12/06Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/28/2006 > 62 patent applications in 38 patent subcategories. patent applications/inventions, industry category
20060291262 - Semiconductor device and fabrication method therefor: There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit... Agent: James Hao, Esq. Wagner, Murabito & Hao
20060291264 - Capacity dividable memory ic: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas,... Agent: Hungchang Lin
20060291263 - Memory system and method of accessing memory chips of a memory system: A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060291265 - Memory cell driver circuits: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer... Agent: Buckley, Maschoff, Talwalkar LLC
20060291266 - Reducing sneak currents in virtual ground memory arrays: In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The sneak currents may arise when cells in each of two adjacent I/O groups are sensed (or programmed) at the... Agent: Trop Pruner & Hu, PC
20060291267 - Antifuse circuit with current regulator for controlling programming current: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor.... Agent: Okamoto & Benedicto, LLP
20060291268 - Intergrated semiconductor memory and method for producing an integrated semiconductor memory: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result... Agent: Slater & Matsil LLP
20060291270 - Ferroelectric memory device and display-driving ic: A ferroelectric memory device including: a first bit line which extends, from one end toward another end thereof, in a first direction; a plurality of first memory cells, which are connected to the first bit line and store predetermined data; a second bit line which extends, from one end toward... Agent: Harness, Dickey & Pierce, P.L.C
20060291269 - Image projector with flexible reflective analog modulator: An image projector comprises a plurality of flexible reflective analog modulators (FRAMs), an illumination optics for focusing at least one light source thereon, a conversion optics for converting the variations in divergence of the beams reflected therefrom into variations in intensity, and a scanning mechanism coupled to a projection optics... Agent: Wallenstein & Wagner, Ltd.
20060291271 - High density data storage devices having servo indicia formed in a patterned media: Systems in accordance with the present invention can include a tip contactable with a media, the media including a servo pattern, an inhibiting matrix having a plurality of cells disposed within the inhibiting matrix, wherein the servo pattern is defined at least partially by the plurality of cells. A data... Agent: Fliesler Meyer, LLP
20060291274 - Semiconductor integrated circuit: A semiconductor integrated circuit having an internal SRAM that includes at least one row in which a plurality of memory cells are arrayed, the semiconductor integrated circuit comprises: a first bit line and a second bit line that are connected to first ports of the memory cells; a third bit... Agent: Harness, Dickey & Pierce, P.L.C
20060291273 - Sram memory cell and associated read and write method: A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having a drain coupled to the first node (A), a gate coupled to a word... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.
20060291272 - Static random access memory cell using chalcogenide: A static random access memory may be formed using a bitline and a bitline bar coupled to ovonic threshold switches. The ovonic threshold switches may, in turn, be coupled to cross coupled NMOS transistors. In some embodiments, a very compact static random access memory may result.... Agent: Trop Pruner & Hu, PC
20060291276 - Magnetic memory with a magnetic tunnel junction written in a thermally assisted manner, and method for writing the same: The invention relates to a magnetic memory written in a thermally assisted manner, each memory point (40) consisting of a magnetic tunnel junction, and the cross-section of the memory parallel to the plane of the layers forming the tunnel junction being circular or essentially circular. Said tunnel junction comprises at... Agent: Burr & Brown
20060291275 - Magnetoresistive memory cell and process for producing the same: A magnetoresistive memory cell includes a tunnel barrier region between first and second electrode devices. The first electrode device includes a natural antiferromagnet region. A diffusion barrier region is formed in the first electrode device and serves as a chemical and/or physical transformation region of a surface region or interface... Agent: Edell, Shapiro & Finnan, LLC
20060291277 - Phase change random access memory (pram) device: A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers... Agent: Volentine Francos, & Whitt PLLC
20060291278 - Nano-reflectors for thin, flat display devices: A display device is described comprising a first transparent electrode, a second electrode, and a pixel, wherein the pixel, in-between the first electrode and the second electrode, comprises a display molecule connected to a first surface, the display molecule comprises an electron donor, a conjugated bridge and an electron acceptor.... Agent: Andrew Tipton
20060291279 - Semiconductor memory device: A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array power voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit power voltage... Agent: F. Chau & Associates, LLC
20060291280 - Configuration finalization on first valid nand command: A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current... Agent: Attn: Daniel J. Polglaze Leffert Jay & Polglaze, P.A.
20060291282 - Flash memory cell and methods for programming and erasing: Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge... Agent: Eschweiler & Associates, LLC National City Bank Building
20060291281 - Non-volatile memory, manufacturing and operating method thereof: A non-volatile memory having a substrate, a select gate, a pair of charge storage layers, a pair of source/drain regions and a control gate is provided. At least a pair of trenches are formed in the substrate. The select gate is formed on the substrate between the pair of trenches.... Agent: Jianq Chyun Intellectual Property Office
20060291284 - Apparatus and method for driving liquid crystal display device: An apparatus for driving a liquid crystal display device includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines, a gate driver, a data driver, a data converter, and a timing controller. The timing controller controls the drive time of the gate and... Agent: Brinks Hofer Gilson & Lione
20060291283 - Redundant memory content substitution apparatus and method: A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and output a main data word comprising a plurality of main data sub-words where the read address includes a first portion and a second portion.... Agent: Macpherson Kwok Chen & Heid LLP
20060291287 - Method for operating a non-volatile charge-trapping memory device and method for determining programming/erase conditions: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP
20060291286 - Methods of programming silicon oxide nitride oxide semiconductor (sonos) memory devices: A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer... Agent: Volentine Francos, & Whitt PLLC
20060291285 - System and method for programming cells in non-volatile integrated memory devices: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage... Agent: Parsons Hsue & De Runtz LLP
20060291288 - Flash memory device and read method: In a flash memory device following precharge, a bitline and a sense node are coupled and then developed. A voltage apparent at the sense node is detected to recognize a data value of a corresponding memory cell. For a develop period, a bitline-side capacitance is much higher than a capacitance... Agent: Volentine Francos, & Whitt PLLC
20060291290 - Circuit and method for adaptive incremental step-pulse programming in a flash memory device: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has... Agent: Myers Bigel Sibley & Sajovec
20060291289 - Non-volatile memory device having page buffer for verifying pre-erase: Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit... Agent: Marshall, Gerstein & Borun LLP
20060291292 - Non-volatile semiconductor memory and programming method: In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. The method includes a primary programming process which includes providing a first program voltage... Agent: Volentine Francos, & Whitt PLLC
20060291291 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array and a sense amplifier, the device being internally controlled to execute a write sequence with write pulse applications and write-verify operations repeated for writing a set of memory cells selected in the memory cell array, wherein the sense amplifier performs... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060291293 - Bias circuits and methods for enhanced reliability of flash memory device: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in... Agent: Mills & Onello LLP
20060291294 - Method for refreshing a flash memory: A plurality of cells of a flash memory are tested to determine if they need to be refreshed. The cells are read and a plurality of different sensing ratios are used to determine if any of the cells need to be refreshed. Any cells that are determined to need refreshing... Agent: Akin Gump Strauss Hauer & Feld L.L.P.
20060291295 - Method, system and program product for configuring a digital system based upon system-level variables: In a method of data processing, a binary system configuration file is interpreted by reference to a value set of at least one system-level variable in response to a configuration event. The binary system configuration file contains a binary representation of a plurality of system configuration statements specifying a plurality... Agent: Dillon & Yudell LLP
20060291296 - Virtual ground circuit for reducing sram standby power: A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row... Agent: Texas Instruments Incorporated
20060291297 - Semiconductor memory: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal... Agent: Arent Fox PLLC
20060291298 - Liquid crystal display and driving method thereof: A liquid crystal display device includes a comparator which judges a voltage of data; and a pre-charge controller which pre-charges a data line of a liquid crystal display panel with a pre-charge voltage if the voltage of the data is a first voltage, and pre-charges the data line with a... Agent: Brinks Hofer Gilson & Lione
20060291299 - Semiconductor memory device: Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not... Agent: Whitham, Curtis & Christofferson & Cook, P.C.
20060291300 - High speed data access memory arrays: Techniques for reading data from memory cells in memory arrays are provided. Local read bit lines are coupled to logic gates such as NAND gates. The input terminals of each logic gate are coupled to receive signals from two of the local read bit lines. The output of the logic... Agent: Townsend And Townsend And Crew, LLP
20060291301 - Memory device and method for operating the memory device: A memory device comprises a memory cell array (1) with a multitude of memory cells (111). Each of the memory cells (111) is assigned to one of a multitude of blocks (15). Each memory cell (111) is accessible by an access signal in order to alter stored information. Each of... Agent: Slater & Matsil LLP
20060291302 - Programmable data strobe enable architecture for ddr memory applications: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal... Agent: Lsi Logic Corporation
20060291303 - Method and apparatus for programming a memory array: A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines... Agent: Brinks Hofer Gilson & Lione
20060291304 - Method for enhanced block management: A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block is remapped to a spare block, if the block is predicted as a bad block. Remapping is done for... Agent: Blakely Sokoloff Taylor & Zafman
20060291305 - Semiconductor device and program data redundancy method therefor: A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the... Agent: Ingrassia Fisher & Lorenz, P.C.
20060291306 - Semiconductor memory device: A semiconductor memory device has: a memory cell array including a normal region and a redundancy region; a first decoder configured to decode an address signal to generate a first decode signal; a first driver configured to select a memory cell corresponding to the first decode signal in the normal... Agent: Mcginn Intellectual Property Law Group, PLLC
20060291307 - Semiconductor memory and burn-in test method of semiconductor memory: A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure... Agent: Arent Fox PLLC
20060291308 - Test method and test program for semiconductor storage device, and semiconductor storage device: A method and program for testing a semiconductor storage device enabling efficient determination of memory cells that may cause disturbance. The semiconductor storage device includes a memory cell array including an array of memory cells, an X decoder for applying predetermined voltage to the gate terminals of the memory cells,... Agent: Freescale Semiconductor, Inc. Law Department
20060291310 - Block word line precharge circuit of flash memory device: A block word line precharge circuit that precharges a block word line connected to the gates of transistors, for transferring bias of global word lines to local word lines, respectively. During a precharge period of the block word line, a program voltage, a read voltage and a pass voltage are... Agent: Mayer, Brown, Rowe & Maw LLP
20060291309 - Driver circuit, electro-optical device, electronic instrument, and drive method: A driver circuit includes a first output buffer BUF1 which drives a data line of an electro-optical device based on grayscale data, and a first precharge circuit PC1 which precharges an output line of the first output buffer BUF1. The first precharge circuit PC1 supplies a first precharge voltage to... Agent: Oliff & Berridge, PLC
20060291312 - Cmos amplifiers with frequency compensating capacitors: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20060291311 - Memory device for retaining data during power-down mode and method of operating the same: A memory device includes a bit line sense amplifier, a command decoder configured to generate an internal control signal indicating an operating mode of the memory device, and a bit line sense amplifier controller configured to selectively apply an external voltage as a supply voltage to the bit line sense... Agent: Marger Johnson & Mccollom, P.C.
20060291313 - Local sense amplifier and semiconductor memory device having the same: A sense amplifier including a pair of differential transistors configured to amplify a differential signal applied to a pair of I/O lines, each transistor having a terminal, a current supplying circuit configured to supply a current to the differential transistors in response to an enable signal, and a coupling element... Agent: Marger Johnson & Mccollom, P.C.
20060291314 - Memory: A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external access operation, an access control portion performing an internal access operation on the basis... Agent: Mcdermott Will & Emery LLP
20060291315 - Antifuse circuit: An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions... Agent: Freescale Semiconductor, Inc. Law Department
20060291316 - Antifuse circuit with dynamic current limiter: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor.... Agent: Okamoto & Benedicto, LLP
20060291318 - Internal voltage supply circuit: Disclosed herein is an internal voltage supply circuit for a semiconductor device. The internal voltage supply circuit includes a first voltage driver for supplying a first voltage in response to a first enable signal, a second voltage driver for supplying a second voltage in response to a second enable signal,... Agent: Marshall, Gerstein & Borun LLP
20060291319 - Reduced area high voltage switch for nvm: In a high voltage switch circuit for programming memory cells, preset devices for precharging the core circuit are eliminated by statically presetting nodes of the switch core circuit through a pair of drive circuits arranged to pull up or down a pair of cascoded transistors in the core circuit.... Agent: Merchant & Gould PC
20060291317 - Voltage supply circuit and semiconductor memory: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the... Agent: Arent Fox PLLC
20060291320 - Storage units and register file using the same: A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a third inverter, in which the first and second inverters have different threshold voltages. The first inverter... Agent: Birch Stewart Kolasch & Birch
20060291322 - Circuit and method for retrieving data stored in semiconductor memory cells: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one... Agent: Graybeal, Jackson, Haley LLP
20060291321 - Word line driver for dram embedded in a logic process: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep... Agent: Bever Hoffman & Harms, LLP Tri-valley Office
20060291323 - Parallel data path architecture: A memory device includes: a memory array for storing data; data pads for supplying as an output of the memory device data retrieved from the memory array in a read operation; parallel read data paths each coupled between the memory array and the data pads, where the parallel read data... Agent: Edell, Shapiro & Finnan, LLC12/21/2006 > 52 patent applications in 29 patent subcategories. patent applications/inventions, industry category
20060285374 - Content addressable memory cell: A content addressable memory cell may include a non-volatile memory storage transistor coupled to an enhancement transistor. In some embodiments, the enhancement transistor may be a select cell. In some embodiments, the storage transistor may use substrate hot electron injection. Through the use of the enhancement transistor, overerasing and read... Agent: Trop Pruner & Hu, PC
20060285375 - Semiconductor memory and method for manufacturing the semiconductor memory: A semiconductor memory includes a semiconductor region, floating gate electrodes arranged in a matrix on the semiconductor region through a tunnel insulating layer, inter-gate insulating layers disposed only on the plurality of floating gate electrodes, respectively, control gate electrodes disposed on the plurality of inter-gate insulating layers, respectively, and isolation... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060285376 - Semiconductor memory device layout including increased length connection lines: An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a first isolation device electrically coupled to an end of the first bit line, and a second isolation device electrically coupled to an end of the... Agent: Myers Bigel Sibley & Sajovec
20060285377 - Sliced crossbar architecture with no inter-slice communication: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first... Agent: Townsend And Townsend And Crew, LLP
20060285379 - Memory device with programmable parameter contoller: The present invention relates to a memory device having the capability of controlling a characteristic parameter including a register controller including a nonvolatile memory unit for storing data and a parameter controller for outputting a signal corresponding to a predetermined input signal. The parameter controller controls one or more characteristic... Agent: Heller Ehrman White & Mcauliffe LLP
20060285378 - Semiconductor memory device: In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.... Agent: Mcdermott Will & Emery LLP
20060285380 - Phase change random access memory (pram) device: A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are... Agent: Volentine Francos, & Whitt PLLC
20060285381 - Sensing of resistance variable memory devices: A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed... Agent: Dickstein Shapiro LLP
20060285382 - Hard disk device having normal and low density memory regions: A hard disk device includes a magnetic disk for storing data, a temperature sensor for detecting an ambient temperature and a controller for controlling operation of the hard disk device. The magnetic disk has a first memory region where data are memorized with a high density when the ambient temperature... Agent: Posz Law Group, PLC
20060285383 - Non-volatile magnetic memory device: A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second... Agent: Morgan Lewis & Bockius LLP
20060285384 - Non-volatile memory array with simultaneous write and erase feature: A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has... Agent: Schneck & Schneck
20060285385 - Mtp storage medium and access algorithm method with traditional otp: A method for performing multi-programmable function with one-time programmable (OTP) memories includes: generating a newest word in a OTP memory array; receive a word-to-be-record; comparing the newest word and the word-to-be-record; and according to a result, recording bit information between the newest word and the word-to-be-record into the OTP memory... Agent: North America Intellectual Property Corporation
20060285386 - Accessing an nrom array: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local... Agent: Tiajoloff & Kelly
20060285387 - Flash memory device with nand architecture with reduced capacitive coupling effect: A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes... Agent: Seed Intellectual Property Law Group PLLC
20060285388 - Circuit and method of generating high voltage for programming operation of flash memory device: Provided is a high voltage generator for a flash memory device including a voltage pumping unit configured to generate a high voltage in response to a pumping clock signal, a transistor having a gate coupled to the high voltage and a source coupled to a program voltage, a voltage distributor... Agent: Marger Johnson & Mccollom, P.C.
20060285389 - Eeprom cell and eeprom block: The EEPROM cell includes a writing unit having a flash cell Metal Oxide Semiconductor (MOS) for receiving from outside a gate selection signal via a gate and a drain selection signal via a drain, and writing one bit data, and a high-voltage MOS whose source is connected to a source... Agent: Morgan Lewis & Bockius LLP
20060285390 - Bitline exclusion in verification operation: Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze
20060285391 - Compensation currents in non-volatile memory read operations: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and... Agent: Vierra Magen/sandisk Corporation
20060285392 - Selective slow programming convergence in a flash memory device: A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to... Agent: Leffert Jay & Polglaze, P.A. Attn: Kenneth W. Bolvin
20060285393 - Apparatus and method for programming a memory array: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that... Agent: Schwegman Lundberg Woessner & Kluth, P.A.
20060285394 - Method of programming a non-volatile memory cell by controlling the channel current during the rise period: A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming... Agent: Dla Piper Rudnick Gray Cary Us, LLP
20060285395 - Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts: Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command,... Agent: Lexmark International, Inc. Intellectual Property Law Department
20060285396 - Program method with optimized voltage level for flash memory: A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20060285398 - Semiconductor device: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation... Agent: Buchanan, Ingersoll & Rooney PC
20060285397 - Storage device: A storage device, enabling elimination of redundant write operations of non-selected data and enabling optimization of arrangement of pages to a state efficient for rewriting, having two flash memories which can be accessed in parallel, a page register for acquiring data in parallel from the flash memories and temporarily storing... Agent: Rader Fishman & Grauer PLLC
20060285399 - Drive circuit and display apparatus: Disclosed is a drive circuit that is capable of increasing the efficiency of power recovery by improving the drive capability of a switching element of an output circuit for driving a capacitive load, particularly the drive capability in a low voltage range. The drive circuit includes a totem-pole circuit having... Agent: Sughrue Mion, PLLC
20060285400 - Static semiconductor memory device allowing simultaneous writing of data into a plurality of memory cells: A supply instruction signal attains the H-level before data is written into a plurality of memory cells. A P-channel MOS transistor is arranged between a power supply node and an input node. The P-channel MOS transistor is turned off to open the input node according to the supply instruction signal.... Agent: Mcdermott Will & Emery LLP
20060285402 - Apparatus and methods for multi-level sensing in a memory array: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage... Agent: Tiajoloff & Kelly
20060285401 - Low power dissipation voltage generator: A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a source transistor to couple a substrate voltage, Vbb, to an output voltage node. The transistor is selectively activated by a current mirror circuit and... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20060285403 - Output circuit that turns off one of a first circuit and a second circuit: An output circuit including a first circuit configured to provide a first output signal, a second circuit configured to provide a second output signal, and a third circuit. The third circuit is configured to receive a third output signal that is based on the first output signal and the second... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060285404 - Multi-use strobe and illumination module: A system for illuminating and signaling in a hands free manner includes an illumination module comprising at least one independent light source and strobe emitter, and a material holder for supporting the illumination module for hands free use.... Agent: Central Coast Patent Agency, Inc
20060285405 - Semiconductor memory and operation method for same: A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh... Agent: Arent Fox PLLC
20060285406 - Input buffer for low voltage operation: Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The input buffer operates in a relatively low supply voltage and a relatively wide range of signal levels of the input signals while improving the symmetry between rising... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20060285407 - Memory device: A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a... Agent: Harness, Dickey & Pierce, P.L.C
20060285408 - Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells: The present invention consists of a method and system for compensating, over time and over an operating temperature range, for margin loss in a non-volatile memory (“NVM”) cell, which method comprises selection of a reference level based on temperature readings obtained from a temperature sensing element that is thermally coupled,... Agent: Tiajoloff & Kelly
20060285410 - Memory having parity error correction: A memory includes a sense amplifier segment and a plurality of word lines including a spare word line, a first transfer word line, and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060285412 - Memory having parity error correction: A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060285409 - Memory having parity generation circuit: A memory includes a column segment including memory cells along word lines, and a parity generation circuit configured to receive a first serial data stream of data bit values stored in memory cells along a word line and determine a first parity value of the first serial data stream upon... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060285413 - Semiconductor memory: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier... Agent: Arent Fox PLLC
20060285411 - Single cycle refresh of multi-port dynamic random access memory (dram): A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in... Agent: International Business Machines Corporation Dept. 18g
20060285415 - Circuit and method for reading an antifuse: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to... Agent: Kimton N. Eng. Esq. Dorsey & Whitney LLP
20060285416 - Circuit and method for reading an antifuse: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to... Agent: Kimton N. Eng. Esq. Dorsey & Whitney LLP
20060285414 - Fuse circuit and electronic circuit: A fuse circuit and an electronic circuit for outputting a signal in accordance with the breakage of fuses even when the resistances of the broken fuses differ, reducing leak currents, and lowering power consumption. The fuse circuit includes a plurality of fuse lines, each including a fuse connected to a... Agent: Freescale Semiconductor, Inc. Law Department
20060285418 - Semiconductor integrated circuit device, electronic component mounting board and layout designing method for the semiconductor integrated circuit device: A circuit configuration is adopted which supplies an internal power supply voltage from outside and inside of a semiconductor chip 1. The internal power supply voltage from the outside is supplied through an internal power supply pad 20, whereas the internal power supply voltage from the inside is supplied through... Agent: Mcdermott Will & Emery LLP
20060285417 - Transformer coupled clock interface circuit for memory modules: The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.... Agent: Brown Raysman Millstein Felder & Steiner, LLP
20060285419 - Flexible capacity memory ic: More than one memory areas are connected in parallel to increase the memory capacity when activated. The different memory area in a single unit die is activated by a selector pad which controls a single-pole, double throw switch to enable or disable the different memory areas. The corresponding pads of... Agent: Hungchang Lin
20060285420 - Three dimensional twisted bitline architecture for multi-port memory: A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode... Agent: International Business Machines Corporation Dept. 18g
20060285421 - Architecture for virtual ground memory arrays: The drain programming window in virtual ground memory arrays may be enlarged by reducing the number of voltage drops in the cell access path. This reduction may be accomplished by reducing the number of transistors in the access path or by otherwise reducing the resistance in the access path.... Agent: Trop Pruner & Hu, PC
20060285422 - Floating body memory cell system and method of manufacture: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby... Agent: Zilka-kotab, PC
20060285423 - Volatile memory cell two-pass writing method: A method is set forth for writing volatile memory cells embodied on an integrated circuit and taking the form of an array of volatile memory cells including a plurality of word lines and a plurality of bit lines. In use, a first write operation is performed on at least one... Agent: Zilka-kotab, PC
20060285425 - Data output circuit of synchronous memory device: A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data... Agent: Ladas & Parry LLP
20060285424 - High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which... Agent: Edell, Shapiro & Finnan, LLC12/14/2006 > 49 patent applications in 28 patent subcategories. patent applications/inventions, industry category
20060279977 - Ferroelectric memory device having ferroelectric capacitor: A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060279978 - Method and structure for high performance phase change memory: A method (and structure) for a memory cell having a phase change material (PCM) element and a heating element external to the PCM element. The heating element causes one of a presence of and an absence of a phase boundary within the PCM element for storing information in the PCM... Agent: Mcginn Intellectual Property Law Group, PLLC
20060279979 - Method of reading phase-change memory elements: A method of reading a phase-change memory element. The memory element is read by establishing a read voltage across the memory element. The read voltage is preferably greater than the holding voltage of the memory element.... Agent: Energy Conversion Devices, Inc.
20060279981 - Fast magnetic memory devices utilizing spin transfer and magnetic elements used therein: A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of magnetic storage cells includes a plurality of magnetic elements and at... Agent: Sawyer Law Group LLP
20060279982 - Magnetic random access memory: A magnetic random access memory includes memory cells which store information using an internal magnetization direction. A first write line includes a first extending portion, a second extending portion and a first connection portion. The first extends portion extends along a first direction and has a first end and a... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060279980 - Magnetic storage cell and magnetic memory device: To provide a magnetic memory cell that is capable of efficiently changing the magnetization directions of magneto-sensitive layers. A magnetic memory cell comprises an annular magnetic layer 4a through which extends a write bit line 5a that generates a magnetic field, and a TMR film S20a configured so as to... Agent: Greenblum & Bernstein, P.L.C
20060279983 - Storage device and semiconductor apparatus: A storage device includes a storage element having first and second terminals that cause a first electrical characteristic change when an electric signal of a first threshold level or higher is applied and that cause a second electrical characteristic change, which is asymmetrical to the first electrical characteristic change, when... Agent: Sonnenschein Nath & Rosenthal LLP
20060279984 - Semiconductor integrated circuit device: A programmable logic device unit, a non-volatile memory unit which stores data for programming the programmable logic device unit in a part of data storage area thereof and a control circuit which controls the non-volatile memory unit to allow the data stored in a part of the data storage area... Agent: Foley And Lardner LLP Suite 500
20060279985 - Purge-based floating body memory: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of... Agent: RyderIPLaw C/o Intellevate
20060279987 - Leaf plot analysis technique for multiple-side operated devices: A method for analyzing the interaction between threshold states of a multiple-bit memory cell on a coordinate system is provided. The coordinate system is formed using a plurality of axes with one axis being a threshold state of a first side of a memory cell and the second axis being... Agent: Akin Gump Strauss Hauer & Feld L.L.P.
20060279989 - Method of controlling copy-back operation of flash memory device including multi-level cells: A method of controlling a copy-back operation of a flash memory device including multi-level cells. In the method, the copy-back operation can be executed even without an additional storage space. Accordingly, a program time can be shortened and operational performance of a flash memory device can be improved.... Agent: Mayer, Brown, Rowe & Maw LLP
20060279988 - System and method for matching resistance in a non-volatile memory: A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and... Agent: Sawyer Law Group LLP
20060279992 - Nand flash memory devices having shielding lines between wordlines and selection lines: A NAND flash memory having a cell string structure includes a wordline configured to transfer a wordline voltage to a memory cell. A selection line is configured to transfer a selection voltage to a selection transistor connected to the memory cell and at least one shielding line is interposed between... Agent: Myers Bigel Sibley & Sajovec
20060279991 - Nand type flash memory array and method for operating the same: A NAND type flash memory array which is composed of a plurality of memory cells with a shallow junction on an SOI substrate to make the body region depleted fully when each channel of the memory cells is turned on is provided. The invention improves the efficiency of a reading... Agent: Marger Johnson & Mccollom, P.C.
20060279990 - Selective application of program inhibit schemes in non-volatile memory: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered... Agent: Vierra Magen/sandisk Corporation
20060279993 - Semiconductor memory device which generates voltages correspoding to a plurality of threshold voltages: A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060279994 - Flash memory device capable of reduced programming time: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored... Agent: Volentine Francos, & Whitt PLLC
20060279995 - Nonvolatile memory: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage... Agent: Miles & Stockbridge PC
20060279986 - Semiconductor device and programming method therefor: There is provided a semiconductor device including regular cells (16) disposed in a regular sector (10) and connected to a word line (14), and a plurality of reference cells (26) used in reading data from the regular cells (10), wherein one of the reference cells is selected based on a... Agent: Ingrassia Fisher & Lorenz, P.C.
20060279996 - Read source line compensation in a non-volatile memory: Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple... Agent: Macronix C/o Haynes Beffell & Wolfeld LLP
20060279997 - Method of refreshing a charge-trapping nonvolatile memory using band-to-band tunneling hot hole (btbthh) injection: A method of using a non-volatile memory that utilizes a charge-trapping layer for data storage is described. A refresh step is performed, after the non-volatile memory is subject to multiple write/erase cycles causing hard-to-erase electrons in the charge-trapping layer, to eliminate the hard-to-erase electrons. After the refresh step, the non-volatile... Agent: J C Patents, Inc.
20060279998 - Low power nrom memory devices: A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a charge trapping dielectric layer... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20060280000 - Cact-tg (catt) low voltage nvm cells: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type... Agent: Mammen Thomas
20060279999 - Methods of erasing flash memory devices by applying wordline bias voltages having multiple levels and related flash memory devices: Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while... Agent: Myers Bigel Sibley & Sajovec
20060280001 - Semiconductor memory device: A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch within a read amplifier are provided individually and the column selection switch within the read amplifier is... Agent: Stanley P. Fisher Reed Smith LLP
20060280002 - Memory system having fast and slow data reading mechanisms: A memory for storing data comprising: a fast data reading mechanism operable to sense one or more signal values dependent upon a data value stored in said memory so as to generate a first signal transition indicative of said data value and used to generate a fast read result that... Agent: Nixon & Vanderhye, PC
20060280003 - Methods and apparatus for reading a full-swing memory array: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of... Agent: Qualcomm Incorporated
20060280004 - Control signal interface circuit for computer memory modules: The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and... Agent: Brown Raysman Millstein Felder & Steiner, LLP
20060280005 - Memory voltage generating circuit: A memory voltage generating circuit includes a first control module, a core circuit, and a second control module. The core circuit includes a regulation amplifier, a first MOSFET, a second MOSFET, and a switch. An output terminal and an inverting input terminal of the regulation amplifier are both connected to... Agent: Morris Manning Martin LLP
20060280006 - Storage device and control method therefor: The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D1), to a memory cell array (11) for providing BIAS VOLTAGE VPP stepped... Agent: Ingrassia Fisher & Lorenz, P.C.
20060280007 - Memory product controller, memory product control method, and memory product: To provide a memory product controller, a memory product control method, and a memory product storing a computer program, capable of realizing a multi-function memory product, without increasing the cost, by grouping a plurality of memory products. In a memory product controller, information identifying a memory product and an operating... Agent: Arent Fox PLLC
20060280008 - Device to be used for reading out a memory cell, and method for reading out a memory cell: A method for reading out a memory cell, and a device to be used for reading out a memory cell is disclosed. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060280009 - Semiconductor memory: A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cells maintaining or discharging one of... Agent: Mcdermott Will & Emery LLP
20060280010 - Storage device: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line... Agent: Reed Smith LLP
20060280011 - Bias sensing in dram sense amplifiers: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time... Agent: Fish & NeaveIPGroup Ropes & Gray LLP
20060280012 - Electronic memory apparatus and method for operating an electronic memory apparatus: An electronic memory apparatus has a plurality of memory devices, a plurality of temperature sensors and a control unit. The memory devices each have a multiplicity of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus. The control unit passes a same periodic clock signal to... Agent: Slater & Matsil LLP
20060280013 - Expanding devices and structures and methods therefore: A method including: forming a housing having at least one expandable portion, the forming including: expanding a covering to define a cavity; and expanding foam in the cavity in an expansion direction to expand the covering into a predetermined shape; and disposing one or more electronic components in the housing... Agent: Thomas Spinelli
20060280014 - Expanding devices and structures and methods therefore: A method for forming an expandable member is provided. The method including: expanding a covering to define a cavity; and expanding foam in the cavity in an expansion direction to expand the covering into a predetermined shape.... Agent: Thomas Spinelli
20060280015 - Semiconductor memory: An oscillator generates a refresh request signal periodically. A storing circuit changes a stored value by a predetermined value in response to the refresh request signal and returns the stored value by one in response to a refresh operation. A store control circuit, when a state detecting circuit detects a... Agent: Arent Fox PLLC
20060280017 - Circuit and method for reading an antifuse: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP
20060280016 - Method for trimming programmable resistor to predetermined resistance: A programmable resistor is an e-fuse connecting to a source/drain of a MOS transistor. According to the method, a voltage is provided to the gate of the MOS transistor to partially blow the programmable resistor. Following that, a resistance comparator is used to compare the resistance of the programmable resistor... Agent: North America Intellectual Property Corporation
20060280018 - Apparatus, system, and method for modifying memory voltage and performance: An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies... Agent: Kunzler & Associates
20060280019 - Error based supply regulation: In some embodiments, an error based supply regulation scheme is provided where error information from a cache is monitored, and the supply level supplying a CPU associated with the cache is controlled based on the error information. Other embodiments are disclosed herein.... Agent: Blakely Sokoloff Taylor & Zafman
20060280021 - Memory and driving method therefor: A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th bank select MOS transistor. Gate(i, j) of memory cell M(i, j) is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20060280020 - Memory data access scheme: A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a... Agent: Schneck & Schneck
20060280022 - Nonvolatile semiconductor memory device having assist gate: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line... Agent: Mcdermott Will & Emery LLP
20060280023 - Semiconductor memory device using a ferroelectric capacitor: A semiconductor memory device includes a row of memory cells connected in series, each of the memory cells including a ferroelectric capacitor and a cell transistor having a gate terminal and source/drain terminals, the source/drain terminals being connected in parallel with two electrodes of the ferroelectric capacitor, a word line... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060280024 - Memory system with registered memory module and control method: A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address... Agent: Volentine Francos, & Whitt PLLC
20060280025 - Semiconductor memory device: A semiconductor memory device is provided. The semiconductor memory device includes: a first input/output control unit for changing a sensing node into a first level in response to an activation of a first enabling signal for enabling an output of a data synchronized with a rising edge of a clock... Agent: Blakely Sokoloff Taylor & Zafman12/07/2006 > 38 patent applications in 24 patent subcategories. patent applications/inventions, industry category
20060274562 - Planar array contact memory cards: A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of... Agent: Harrington & Smith, LLP
20060274563 - Self-test circuit for high-definition multimedia interface integrated circuits: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer... Agent: Gauthier & Connors, LLP
20060274564 - Wordline voltage generation circuit and nonvolatile memory device with the same: A wordline voltage generation circuit generates an incremental step pulse voltage and includes a first circuit unit connected to a program voltage, a second circuit unit connected between the first circuit unit and a divided voltage and controlled by a program step code, and a third circuit unit connected between... Agent: F. Chau & Associates, LLC
20060274566 - Memory system combining flash eeprom and feram: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274565 - Memory system having improved random write performance: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274567 - Method of programming a memory device: The present invention is a method of programming a memory device, wherein different levels or magnitudes of current may be applied to and imposed on the memory device so that any one of a plurality of memory states may be realized. A read step indicates the so determined state of... Agent: Paul J. Winters
20060274568 - Magnetic random access memory: A magnetic random access memory described in embodiments of the present invention comprises a conductive line, a soft magnetic material which surrounds the conductive line, a gap disposed in a part of the soft magnetic material, and a magneto-resistive element in which a part of a vertical magnetization film as... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274570 - Liquid crystal display device: A liquid crystal display device includes a display unit having matrix type pixels defined by gate and data lines crossing with each other, a data driver to supply a data voltage to be supplied to the data lines via output lines, the output lines being less in number than the... Agent: Morgan Lewis & Bockius LLP
20060274569 - Semiconductor device including back-gated transistors and method of fabricating the device: A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.... Agent: Mcginn Intellectual Property Law Group, PLLC
20060274571 - Semiconductor integrated circuit device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit... Agent: Stanley P. Fisher Reed Smith LLP
20060274572 - Semiconductor integrated circuit device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit... Agent: Stanley P. Fisher Reed Smith LLP
20060274573 - Magnetic random access memory: A magnetic random access memory includes a first magnetoresistive element which is used as a memory element, and a second magnetoresistive element which is used as a current load of a read bias circuit.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274575 - Electrically programmable memory element with reduced area of contact: A programmable resistance memory element having a conductive layer as an electrode. The conductive layer and memory material may have a small area of contact. In one embodiment, the memory element may include a chalcogenide material.... Agent: Philip H. Schlazer Energy Conversion Devices, Inc.
20060274574 - Phase-change memory device and method of writing a phase-change memory device: A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of... Agent: Volentine Francos, & Whitt PLLC
20060274578 - Nand flash memory device having page buffer adapted to discharge bit line voltage during erase operation: A NAND flash memory device comprises a memory cell array comprising a plurality of memory cells, a plurality of page buffers, and an isolation circuit connected between the memory cell array and the plurality of page buffers. The isolation circuit comprises a high voltage transistor adapted to disconnect a first... Agent: Volentine Francos, & Whitt PLLC
20060274577 - Non-volatile memory electronic device with nand structure being monolithically integrated on semiconductor: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.
20060274580 - Dram cells with repressed floating gate memory, low tunnel barrier interpoly insulators: Methods for operating structures and systems having memory cells with a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20060274579 - Multi-voltage generator generating program voltage, read voltage and high voltage in response to operating mode of flash memory device: Provided is a multi-voltage generator for a flash memory device including a high voltage pumping unit configured to generate a high voltage in response to an enable signal, voltage regulators, each regulator coupled to the high voltage and a control voltage and configured to generate a pumping signal, and a... Agent: Marger Johnson & Mccollom, P.C.
20060274576 - Sensing scheme for a non-volatile semiconductor memory cell: A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared with a predefined reference current while the gate voltages of the cells are varied. Sense amplifiers detect... Agent: Slater & Matsil LLP
20060274581 - Reference scheme for a non-volatile semiconductor memory device: A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory... Agent: Slater & Matsil LLP
20060274582 - Flash memory device having reduced program time and related programming method: Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a... Agent: Volentine Francos, & Whitt PLLC
20060274583 - Starting program voltage shift with cycling of non-volatile memory: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period... Agent: Vierra Magen Marcus & Deniro LLP
20060274584 - Storage array with enhanced rvi: A carrier and associated methodology for removably supporting a plurality of data storage devices as a multiple disc array in a distributed storage system. The carrier defines attachment features for fixing each of the data storage devices to the carrier preventing movement of the data storage devices in relation to... Agent: Fellers, Snider, Blankenship, Bailey & Tippens, P.C.
20060274585 - Memory device with row shifting for defective row repair: A memory device includes N regular rows of memory cells, L redundant rows of memory cells, a shift circuit, and N word lines, where N>1 and L>1. Each word line is associated with a designated row and an alternate row that is L rows away from the designated row. The... Agent: Qualcomm Incorporated
20060274586 - Semiconductor memory device with redundancy function: A fuse and fuse latch includes first and second fuse and fuse latches each serving as a redundancy information storage circuit. Fuse elements and a fuse latch are provided in each of the first and second fuse and fuse latches. The first and second fuse and fuse latches each output... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274588 - Flash memory device and read method thereof: A flash memory device and a read method thereof are provided. At a read operation, a sense node of a page buffer is developed while a bitline is developed and data of a selected memory cell is sensed based on the develop result of the sense node. For a develop... Agent: Mills & Onello LLP
20060274587 - Static random-access memory having reduced bit line precharge voltage and method of operating the same: A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word line driver coupled to word lines of the SRAM array and configured to operate at a... Agent: Texas Instruments Incorporated
20060274590 - Semiconductor memory device: A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20060274589 - Sensing current recycling method during self-refresh: A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line sensing of a selected wordline and deactivation of the selected wordline, a capacitor is connected to a source node associated with a bit line sensing amplifier... Agent: Edell, Shapiro & Finnan, LLC
20060274592 - Circuit and method for controlling a clock synchronizing circuit for low power refresh operation: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP
20060274591 - Semiconductor memory device and information processing system: A refresh operation at a memory cell array for keeping data stored in memory cells is enabled to be switched whether to be executed based on an external refresh request inputted from external or an internal refresh request generated internally by a refresh control unit, and therefore, when the refresh... Agent: Arent Fox PLLC
20060274593 - Semiconductor integrated circuit device: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate... Agent: Miles & Stockbridge PC
20060274595 - Apparatus for supplying internal voltage: An apparatus for supplying an internal voltage is provided the apparatus for supplying an internal voltage comprises: a comparison unit for comparing a reference voltage with an internal reference voltage to output a driving signal based on the comparison result; an internal voltage providing unit for providing the internal voltage... Agent: Blakely Sokoloff Taylor & Zafman
20060274594 - Implementation of a fusing scheme to allow internal voltage trimming: Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies
20060274596 - Memory devices having reduced coupling noise between wordlines: Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By... Agent: Michael G. Fletcher Fletcher Yoder
20060274599 - Clock stop detector: A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a... Agent: Dicke, Billig & Czaja, P.l.l.c.
20060274597 - Delay-lock loop and method adapting itself to operate over a wide frequency range: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20060274598 - Method for controlling the access times to a system bus and communication module: A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module, which is connected to the communication module via the system bus for transmitting measurement and/or control signals... Agent: Whitham, Curtis & Christofferson & Cook, P.C.Previous industry: Electric power conversion systems
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