Static information storage and retrieval inventions 10/06

20060239054 - Content addressable memory architecture: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The...

20060239053 - Self-aanalyzing memory word: Disclosed herein is a memory system in which sought after keywords will identify their own location by setting a flag bit. The important thing is, keywords may be unstructured, hidden in a sea of words; finding one is equivalent to finding a needle in a haystack. To do so, keywords...

20060239055 - Dram stacked package, dimm, and semiconductor manufacturing method: The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals...

20060239056 - Generation of mram programming currents using external capacitors: An apparatus comprising a magnetoresistive random access memory (MRAM) and a method of forming the same. The apparatus includes a memory circuit comprising an MRAM cell, and a charge pump circuit electrically coupled to the memory circuit wherein the memory circuit and at least a first portion of the charge...

20060239057 - Alignment insensitive d-cache cell: A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on...

20060239059 - Memory array circuit with two-bit memory cells: A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through switching elements controlled in a cyclic sequence by 2m signal lines, where m is an integer greater than one....

20060239058 - Method and apparatus for accessing a memory array: A memory device including first and second memory elements is provided. The first and second memory elements each have first and second electrodes. The first electrode of the first and second memory elements is a common first electrode and is located below the second electrodes. A first line is connected...

20060239061 - Memory system and semiconductor integrated circuit: A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that...

20060239060 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes: a multilayer film including a first ferroelectric film and a second ferroelectric film; means for creating an electric field which goes vertically across the multilayer film; and means for passing current along an interface between the first ferroelectric film and the second ferroelectric film and...

20060239063 - Sensor adjusting circuit: A sensor adjusting circuit for adjusting a digital sensor, whose circuit scale is small and which can maintain high accuracy in a wide adjustment range is provided. A sensor adjusting circuit for adjusting an analog input signal inputted from a sensor and outputting it as another analog output signal in...

20060239062 - Static ram memory cell with dnr chalcogenide devices and method of forming: An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting differential negative resistance characteristics. One of the two devices serves as the load of the other. A switch is provided to bias a middle input node and...

20060239065 - Magnetic memory device: A magnetic memory device which can be formed with a further reduced size. The magnetic memory device includes: a plurality of memory cells each including at least one magnetoresistive effect revealing body and arranged along a pair of lines; a plurality of auxiliary write lines arranged so that each memory...

20060239064 - Magnetic random access memory device: A memory device includes a memory cell having a read margin that exceeds the MR ratio of the memory cell's MR element. The memory cell includes a MR element, a reference transistor, and an amplifying transistor. In some embodiments, the MR element can include a magnetic tunneling junction sandwiched between...

20060239066 - Magnetic random access memory device: A memory device includes a memory cell, a reference structure, and a sensing device. The memory cell includes an MR element and a pass transistor. The pass transistor, reference structure, and sensing device are connected to an input node. The logic state of the memory cell can be detected by...

20060239067 - Thin film magnetic memory device for writing data of a plurality of bits in parallel: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path....

20060239070 - High density memory array system: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a...

20060239069 - Semiconductor integrated circuit device having nonvolatile semiconductor memory and programming method thereof: A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path...

20060239068 - Static random access memory cell: A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node...

20060239072 - Nonvolatile memory device and semiconductor device: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line,...

20060239071 - Semiconductor memory device and electronic equipment: A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a write voltage control circuit for controlling...

20060239073 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M>2) physical quantity levels is...

20060239074 - Using redundant memory for extra features: Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory array and is coupled to receive a command signal. The redundancy circuit is adapted to be selectively programmed for selecting a redundant portion of the...

20060239077 - Nand flash memory device having dummy memory cells and methods of operating same: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality...

20060239075 - Nand flash memory management: A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks...

20060239076 - Non-volatile memory electronic device with nand structure being monolithically integrated on semiconductor: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory...

20060239078 - Nor flash memory device using bit scan method and related programming method: A NOR flash memory device configured to perform a program operation using an ISPP scheme, and comprising a plurality of memory cells, a word line voltage generator, and a scan controller is provided. A method of programming the NOR flash memory device comprising a bit scan method is also provided....

20060239079 - Noise reduction technique for transistors and small devices utilizing an episodic agitation: The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend...

20060239080 - Method for non-volatile memory with managed execution of cached data: Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the...

20060239081 - Nand flash memory with read and verification threshold uniformity: A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to...

20060239082 - Driver circuit: A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a...

20060239083 - Nand flash memory device and methods of its formation and operation: A NAND flash memory device, and methods of forming and operating the same are provided. The NAND flash memory device includes first and second selection gate lines sequentially disposed at one side of a plurality of cell gate lines. A first selection transistor including the first selection gate line serves...

20060239084 - Output buffer circuit for semiconductor memory device: There is provided an output buffer circuit for a semiconductor memory device. The output buffer circuit includes: a main buffer and parallel connected auxiliary buffer receiving an input signal. A selection circuit controls the auxiliary buffer by selectively defining a selected input signal in relation to the input signal and...

20060239085 - Dynamic shift register: A dynamic shift register includes a first stage (21) and a second stage (22). The first stage includes a logical inputting port (201), a first retaining circuit (231), and a first transmitting gate (211). The first transmitting gate includes an input connected to the logical inputting port, and an output...

20060239086 - Nonvolatile memory system: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an...

20060239087 - Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same: In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array...

20060239088 - Method and apparatus for increasing fuse programming yield through preferred use of duplicate data: Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon...

20060239089 - Non-volatile semiconductor device for use in memory card and memory system: A semiconductor memory device includes a block and a reading portion. In the block, a plurality of memory cells are arranged in rows and in columns, and the block includes blocks including a plurality of pages. Each page is configured by a plurality of memory cells which are arranged in...

20060239090 - Semiconductor memory device: To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30. It comprises a built-in self-test circuit 10 for testing defects of the...

20060239091 - Using redundant memory for extra features: An access request for a first memory location of a memory device is received at the memory device. A second memory location is selected in response to the request without regard to an address signal....

20060239092 - Memory circuit and related method for integrating pre-decoding and selective pre-charging: In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit lines selectively during data accessing according to...

20060239093 - Semiconductor memory device: To set a threshold of a reference cell in short time in a semiconductor memory device using a variable threshold type nonvolatile memory cell as a reference current/voltage generating unit, a memory cell which keeps an initial state during an inspection process without performing write/erase operations is provided in an...

20060239094 - Semiconductor memory including self-timing circuit: A semiconductor memory including a sense amplifier circuit for reading the data stored in memory cells and particularly to a semiconductor memory including a self-timing circuit for improving margin for reading data by controlling activation timing of the sense amplifier drive signal in accordance with characteristics of internal memory cells....

20060239098 - Dram architecture enabling refresh and access operations in the same bank: To provide a DRAM that reduces loss time of accesses at the time of refresh and performs refresh for any other bank in parallel with normal accesses and is able to be used just like SRAM. [Constitution]DRAM comprises: refresh directing means for directing execution of refresh; bank specifying means for...

20060239095 - Memory device communication using system memory bus: Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the...

20060239096 - Memory structure and memory refreshing method: The present invention relates to a memory-refreshing method applied to a computer system. The computer system includes a central processing unit (CPU), a north bridge chip in communication with the CPU and a system memory in communication with the north bridge chip. The system memory includes at least a first...

20060239097 - Semiconductor storage apparatus: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or...

20060239099 - No-precharge famos cell and latch circuit in a memory device: The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission...

20060239101 - Fuse detection method and semiconductor memory device including fuse detection circuit: A fuse detection method according to the present invention includes reading out a program state of each fuse and generating a killer signal indicating the program state of the fuse; counting the program state indicated by the killer signal to obtain a count value; inputting an expected value for the...

20060239100 - Logic circuit setting optimization condition of semiconductor integrated circuit regardless of fuse cut: Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of...

20060239102 - Semiconductor integrated circuit device and its power supply wiring method: The present invention discloses a power supply wiring method for stabilizing operation of a semiconductor integrated circuit device. A power supply mesh 24, which is arranged on an upper layer of a basic power supply wires 18 for supplying power to a logic circuit portion 13, includes vertical reinforcing power...

20060239103 - Semiconductor memory circuit: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of...

20060239104 - Slave and master of serial peripheral interface, system thereof, and method thereof: A slave and a master of serial peripheral interface, system thereof and method thereof are provided. The invention saves the read address during the process of data-read in the serial peripheral interface (SPI) and adds a new data-read command so that when the former data address is followed by the...

20060239106 - Semiconductor memory: Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to...

20060239105 - Semiconductor memory device: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each...

20060239107 - Memory system and memory device having a serial interface: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The...

20060239108 - Semiconductor device and control method therefor: A non-volatile semiconductor device provides a pull-up transistor (M1) for a word line drive which can be downsized. The semiconductor device includes a first decoder (109) including a pull-up transistor (M1) selecting and driving a word line (P2WL) connected to memory cells, a first voltage generating circuit (102) generating a...

20060239109 - Semiconductor memory device: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a...

20060239110 - Word line driver circuitry and methods for using the same: Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time...

20060239111 - Non-volatile semiconductor device and method for automatically recovering erase failure in the device: A spare sector is in a blank state beforehand. Each time the erasing is carried out in practical use, the number of erase pulses is counted or the presence/absence of overcurrent flowing when the erase pulse is being applied is monitored. A regular sector having long-erase failure thus detected is...

20060233004 - Car power source apparatus: The car power source apparatus is provided with a battery having a plurality of battery modules connected in series on positive and negative sides of a reference node, and a voltage detection circuit to detect battery module voltage with respect to the battery reference node. The battery reference node of...

20060233005 - Device in a memory circuit for definition of waiting times: The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on...

20060233007 - Display: A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for...

20060233009 - Interleaving and de-interleaving methods, wireless apparatus and semiconductor apparatus of same: The purpose of the present invention is to simplify a circuit for carrying out an interleaving and a de-interleaving processing. A RAM address control outputs an address by an addition of an address output from an address ROM and a predetermined offset, based on state information. The address ROM stores...

20060233003 - Matrix display device: A matrix display device includes an array substrate which controls switching elements connected to pixel electrodes surrounded by gate and source lines by a select signal, and supplies a video signal to the pixel electrodes, a unit that switches between a first and a second scan modes according to an...

20060233002 - Memory cell structure: A memory cell structure. A first conductive line is cladded by at least two first ferromagnetic layers respectively having a first easy axis and a second easy axis, a nano oxide layer located between the first ferromagnetic layers, and a first pinned ferromagnetic layer. The first and second easy axes...

20060233006 - Programmable pipeline array: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell...

20060233008 - Solid-state image-sensing device: In a solid-state image-sensing device of the invention, for acquisition of sensed-image data, a photoelectric converter disconnecting switch is turned on to make a forcible reset switch perform resetting, then the voltage at the end of a logarithmic conversion MOS transistor that is not connected to the photoelectric converter disconnecting...

20060233010 - Non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060233011 - Cam device and remedial method for cam device: A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search...

20060233012 - Semiconductor storage device having a plurality of stacked memory chips: A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which...

20060233013 - Memory device with pre-fetch circuit and pre-fetch method: A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write...

20060233014 - Redundancy circuits for semiconductor memory: A semiconductor random access memory device has an array of normal memory and an array of dummy memory cells. The array of the dummy memory cells are controlled in order to form a redundant twin-cell structure that includes at least one of the dummy memory cells....

20060233016 - Sram cell structure and circuits: An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines,...

20060233015 - Sram memory device with flash clear and corresponding flash clear method: A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The...

20060233017 - Data read method of magnetic random access memory: A data read method of a magnetic random access memory including a first wiring which runs in a first direction, a plurality of second wirings which run in a second direction different from the first direction, and a plurality of magnetoresistive elements which are arranged at intersections of the first...

20060233018 - Non-volatile memory device having toggle cell: A tunneling magneto-resistance element is arranged on an upper layer side of a digit line. The tunneling magneto-resistance element is electrically coupled to a source/drain region of an access transistor through a strap and a contact hole. A bit line is electrically coupled to the tunneling magneto-resistance element, and arranged...

20060233019 - Reading phase change memories without triggering reset cell threshold devices: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current...

20060233021 - Non-volatile memory with background data latch caching during erase operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060233022 - Non-volatile memory with background data latch caching during program operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060233020 - Monitoring the threshold voltage of frequently read cells: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with...

20060233023 - Method for non-volatile memory with background data latch caching during erase operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060233024 - Dram hierarchical data path: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global...

20060233025 - Techniques for implementing accurate operating current values stored in a database: Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory...

20060233026 - Method for non-volatile memory with background data latch caching during program operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060233027 - System and method for a high-speed access architecture for semiconductor memory: A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is...

20060233028 - Method and apparatus for reference cell adjusting in a storage device: When adjusting the reference cells (11), the first reference unit (15) and the second reference unit (17) are used for a verify operation of the reference cells (11). The first reference unit (15) provides the lower limit current of the allowable current range, which is caused to flow by a...

20060233029 - Random access memory having voltage provided out of boosted supply voltage: A random access memory including an array of single transistor memory cells and a voltage source. The voltage source is configured to receive a boosted supply voltage and a reference voltage. The voltage source is configured to provide an output voltage out of the boosted supply voltage and based on...

20060233030 - System and method for enhanced mode register definitions: Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with data selecting one option of a set of options for the operating mode. A second register is programmed with...

20060233031 - Synchronous ram memory circuit: One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception...

20060233032 - Non-volatile semiconductor memory device: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be...

20060233033 - Semiconductor memory device: A semiconductor memory device comprises a central control circuit for receiving an operation command from an external chipset, generating an active signal for executing the operation command, and generating a precharge signal after a predetermined time, a row path control circuit for controlling a bank according to the active signal...

20060233034 - Circuit and method for high speed sensing: A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to the first and...

20060233035 - Semiconductor memory device and testing method thereof: A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays,...

20060233036 - Power savings mode for memory systems: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow...

20060233037 - Method and apparatus for operating electronic semiconductor chips via signal lines: The invention relates to a method for operating electronic semiconductor chips via signal lines, particularly memory chips, where the semiconductor chips are arranged in groups on modules, and where the modules are connected to the signal lines, having the following method steps: a signal quality on the signal lines of...

20060233038 - Semiconductor memory device: A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of...

20060227585 - Computer system, disk apparatus and data update control method: A computer system includes a disk apparatus and a host computer including a journal file system. The disk apparatus includes a memory unit which is capable of permanently storing a journal, a storing control unit which stores a journal, which is sent from the host computer, in the memory unit,...

20060227586 - Medium provided with magnetic element, and method and apparatus for reading information from such medium: An information reading apparatus has an excitation unit that applies a magnetic field to a medium provided with at least one magnetic element that generates a signal when the magnetic field is applied thereto and a pseudo element that generates no signal when the magnetic field is applied thereto; a...

20060227587 - Multichip package or system-in package: Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control...

20060227588 - Semiconductor storage device: In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A...

20060227589 - System and method for writing data using an electron beam: A system for writing data using an electron beam to change the structure of a small section of a storage medium and includes at least one focused electron beam source. The duration of a write cycle of the focused electron beam source is controlled at least in part on an...

20060227590 - Reading a phase change memory: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some...

20060227592 - Reading phase change memories: A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to...

20060227591 - Using higher current to read a triggered phase change memory: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some...

20060227593 - Low voltage operation dram control circuits: Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drain transistors coupled to the sense or restore signals and driven by gate...

20060227595 - Back-gate controlled read sram cell: Disclosed is an eight transistor static random access memory (SRAM) device, comprising first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of...

20060227594 - Memory unit using dynamic threshold voltage wordline transistors: The invention relates to an integrated circuit memory unit comprising: a memory cell, a switched bulk DC voltage source and a plurality of wordline-controlled transistors. Each of wordline-controlled transistors has a bulk connected to the switched bulk DC voltage source. When the data bit is read from the memory cell...

20060227596 - Storage element for mitigating soft errors in logic: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock...

20060227597 - World line segment select transistor on word line current source side: The word line segment select transistor of a segmented word line array is placed on the word line current source side. This eliminates many undesirable effects currently associated with segmented word line MRAM arrays....

20060227599 - Magnetic memory device and method of fabricating the same: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer...

20060227598 - Magnetic random access memory using improved data read out method: An MRAM has a plurality of bit lines, a reference bit line, a plurality of memory cells and reference cells and a read section. The memory cells are provided along the bit lines and the reference cells along the reference bit line. The memory cell and reference cell have a...

20060227600 - Non-volatile memory device: A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions...

20060227601 - Memory cell with trenched gated thyristor: One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward biasing a thyristor to switch the thyristor into a high conductance low impedance state, and storing a first charge...

20060227602 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from the memory cell array and externally supplied expectance...

20060227604 - Program rewriting system and program rewriting method: Program data stored in the recording medium of a general control apparatus coupled to a network is stored in the recording medium of a control apparatus as a rewritten subject of program data in the following manner. First, program data 21 stored in a recording medium 12b contained within the...

20060227603 - Recording method using link recording information: A recording method using link recording information is provided to record the link program information on different kinds of recording media and read and regenerate the link information during the regenerating process so that a user may automatically link and watch the recorded information....

20060227605 - Memory architectures including non-volatile memory devices: Architectures are described that can include integrated non-volatile memory modules. Integrated non-volatile memory modules are a form of memory that is integrated on a single chip and includes at least one volatile memory cell and at least one non-volatile memory device. Information can be loaded between the at least one...

20060227606 - Electronic control apparatus having first microcomputer which forwards externally supplied updating data to a second microcomputer having a lower data receiving performance than the first microcomputer: An electronic control apparatus such as an ECU of a motor vehicle contains first and second microcomputers, with the first microcomputer having a substantially higher data receiving performance than the second microcomputer. Data for updating a ROM of the second microcomputer, transmitted to the first microcomputer from an external apparatus...

20060227607 - Non-volatile memory device including multi-page copyback system and method: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to...

20060227608 - Threshold voltage shift in nrom cells: An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide layer, a charge trapping layer; and a top oxide layer. The bottom oxide layer is no thicker than that...

20060227612 - Common wordline flash array architecture: The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantially the same potential as the...

20060227610 - Integrated electronic non volatile memory device having nand structure: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory...

20060227609 - Non-volatile memory electronic device with nand structure being monolithically integrated on semiconductor: A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different...

20060227611 - Recovery method of nand flash memory device: A NAND flash memory device is recovered by applying a predetermined bias to a drain or a source. A negative bias is applied to a cell gate so that electrons are injected into a floating gate of a cell. This narrows the distribution of an erase threshold voltage and minimizes...

20060227614 - Non-volatile memory and method with bit line to bit line coupled compensation: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a...

20060227613 - Non-volatile memory device and method of preventing hot electron program disturb phenomenon: A method for preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device. A channel boosting disturb-prevention voltage lower than a program-prohibit voltage applied to other word lines is applied to edge word lines coupled to memory cells that are nearest to select transistors. As...

20060227615 - Reference current generating circuit of nonvolatile semiconductor memory device: A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to...

20060227620 - Non-volatile memory cells utilizing substrate trenches: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling...

20060227619 - Nonvolatile semiconductor memory device which stores multivalue data: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating...

20060227618 - Program-verify method of non-volatile memory device: A method for programming a non-volatile memory device includes applying a first program-verify voltage to a first word line to determine whether or not memory cells associated with the first word line have been programmed successfully. A second program-verify voltage is applied to a second word line to determine whether...

20060227616 - Reducing sneak currents in virtual ground memory arrays: Sneak currents may be reduced between adjacent input/output groups in addressed memory arrays, even in the case when I/O breaks are ineffective, such as during erase verify. By providing a plurality of intervening, appropriately biased, non-addressed memory cells, a high resistance to sneak currents may be presented....

20060227617 - Semiconductor device and semiconductor integrated circuit: A semiconductor device includes a first nonvolatile memory element group which includes a plurality of first nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics, a verify circuit which detects a defective first nonvolatile memory element in the first nonvolatile memory element group, and a second...

20060227621 - Nonvolatile semiconductor memory including redundant cell for replacing defective cell: A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell...

20060227622 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be...

20060227623 - Address latch signal generation circuit and address decoding circuit: An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a...

20060227625 - Method and apparatus for capturing full-screen frames: An apparatus for capturing full-screen frames, which are displayed by a display unit having a first display buffer and a second display buffer, in real time. The display unit selects one of the first and second display buffers as a front buffer for displaying the full-screen frames. The apparatus includes...

20060227624 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write...

20060227627 - Buffer component for a memory module, and a memory module and a memory system having such buffer component: The invention relates to a buffer component for a memory module having a plurality of memory components, comprising a first data interface for receiving an item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second...

20060227626 - Input buffer circuit of semiconductor memory device: An input buffer circuit of a semiconductor memory device, wherein a corresponding memory chip is not always selected regardless of a chip select signal in a power-down operating mode or a self-refresh operating mode. Accordingly, the problem of semiconductor memory device malfunctions in the power-down operating mode or the self-refresh...

20060227628 - Display driver and display driving method: In a display driver, a period D following a period P in one scanning period is divided into periods R, G, and B in which data voltages are applied to data lines R, G, and B, and two output orders of the data voltage such as the period R→the period...

20060227629 - Memory device and control method therefor: An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells...

20060227630 - Method and apparatus for applying bias to a storage device: In Step 1, a bias is applied (ON) to all of vertical rows Z1(0) to Z1(2). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z2(0) where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z2(1)...

20060227631 - Semiconductor memory device with delay section: In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the...

20060227632 - Information processing system, information generating apparatus and method, information processing apparatus and method, and program: Embodiments of the present invention are intended to allow a user to integrally manage content regardless whether the content is owned or not owned by the user. In a reproduction terminal, one piece of sort-out information is generated from one play list. Sort-out information is obtained by classifying the metadata...

20060227633 - Internal voltage generator: An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to...

20060227634 - Method for determining and classifying sram bit fail modes suitable for production test implementation and real time feedback: A method (200) is disclosed for determining various bit failure modes in a static random access memory device such as may be used in a production test environment to a resolution detailed enough to distinguish between write, read, and disturb failure modes. One method 200 of determining various bit failure...

20060227635 - Methods and systems for providing paper based outcomes: In various embodiments, gaming devices may generate outcomes to be sold in printed form. Representations of the outcomes, corresponding payouts, and other information are printed on sheets of paper. Multiple printed outcomes are assembled into books, wrapped, and sold to consumers. Consumers may purchase the books and browse through the...

20060227636 - Methods and systems for providing paper based outcomes: In various embodiments, gaming devices may generate outcomes to be sold in printed form. Representations of the outcomes, corresponding payouts, and other information are printed on sheets of paper. Multiple printed outcomes are assembled into books, wrapped, and sold to consumers. Consumers may purchase the books and browse through the...

20060227638 - Display driver and display driving method: In a display driver, one scanning period is divided into a period P and a subsequent period D. In the period P, a pre-charge voltage equal to an original data voltage is applied in a time-sharing manner to data lines in one block, and in the period D after the...

20060227637 - Equalizer and method thereof and memory device: An equalizer and a method thereof and a memory device are provided. The equalizer is used for the memory device having sense amplifier, first bit line and second bit line. The equalizer includes a first switch and a second switch. The first switch is coupled between a reference voltage and...

20060227639 - Current sensing circuit and method of operation: A method for sensing current conducted through a memory cell in which a memory cell current is supplied to, or drawn from, a first sensing node. The first sensing node is defined by a common connection point between the first terminal of a sensor element and an input of an...

20060227641 - Noise resistant small signal sensing circuit for a memory device: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the...

20060227640 - Sensing device with activation and sensing alert functions: A sensing apparatus having a sensing functionality controller and a method of detecting the sensing apparatus is disclosed. A signal generation unit embedded in the sensing apparatus operates in conjunction with the sensing functionality controller to support the sensing functionality of the sensing unit. The signal generation unit generates one...

20060227642 - Semiconductor memory device: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory...

20060227643 - Semiconductor memory device and semiconductor memory device test method: During writing of fail addresses to address registers, when writing of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, or when a storage process of a number of fail addresses that is greater than...

20060227644 - Image processing apparatus, backup processing method, storage medium storing program readable by computer, and program: An image processing apparatus for eliminating the necessity of providing a first control board with a power supply unit beforehand for backing up data stored in an image memory, and reducing the cost of the apparatus as a whole. To accomplish this, in an image processing apparatus including a system...

20060227645 - Nonvolatile semiconductor memory device which stores multivalue data: A voltage generating circuit supplies first gate voltage to the control gate of a memory cell for a first control time period and supplies write voltage to the drain for a first write time period which is shorter than the first control time period when an operation of writing data...

20060227646 - Integrated circuit memory device, system and method having interleaved row and column control: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to...

20060227649 - Dual port memory cell with reduced coupling capacitance and small cell size: A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray...

20060227647 - Multi-port memory device: A multi-port memory device that prevents degradation of efficiency of a global data drive by turning off the switches, which do not discharge a global data bus. The multi-port memory device includes a global data bus, a banks, each bank including a transmitter and a receiver; ports, each port including...

20060227648 - Semiconductor memory device: In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and...

20060227650 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an...

20060227651 - Column path circuit: A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal...

20060221658 - Apparatus and method for memory efficient, programmable, pattern matching finite state machine hardware: A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored...

20060221659 - Access circuit and method for allowing external test voltage to be applied to isolated wells: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one...

20060221660 - Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells: A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells....

20060221661 - Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells: A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a...

20060221662 - Display device and driving method thereof: A display device includes a plurality of pixels, wherein each pixel includes: a light emitting element; a first capacitor connected between a first node and a second node; a driving transistor having an input terminal, an output terminal, and a control terminal connected to the second node where the driving...

20060221663 - Electronic device with a memory cell: The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a second storage state with a second conductivity....

20060221670 - In-service reconfigurable dram and flash memory device: A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of...

20060221671 - Individual i/o modulation in memory devices: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The out/output lines that are shorter, or less capacitive, than the threshold are sensed sooner...

20060221668 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including: a first capacitor, one end of the first capacitor being connected to a floating node; a detection transistor, a gate electrode of the detection transistor being connected to the floating node; a second capacitor, one end of the second capacitor being connected to the...

20060221669 - Semiconductor device: A semiconductor device includes: a first sense amplifier; a first bit line coupled to the first sense amplifier; a second bit line disposed next to the first bit line and electrically coupled to a constant-voltage source; and a first reference cell, including: a first transistor having a source and a...

20060221664 - Semiconductor memory device for a low voltage operation: A semiconductor memory device maintains a same operation speed, without a use of high voltage, even when a driving voltage is low (e.g., below 1.0V). In particular, the inventive semiconductor memory device can reduce a leakage current in a bit line sense amp unit at a low voltage. For this,...

20060221665 - Semiconductor memory device for low voltage: A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/output...

20060221666 - Semiconductor memory device for low voltage: A semiconductor memory device includes a first cell block having a plurality of unit cells for providing a data signal included in a unit cell through a corresponding bit line pair; a plurality of bit line sense amplifying blocks for sensing and amplifying the data signal delivered to the corresponding...

20060221667 - Solid state image pickup device and camera: An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P well by layering the...

20060221672 - Nanocrystal quantum dot memory devices: Memory devices and recordable media are disclosed that take advantage of memory effects in the electronic transport in CdSe nanocrystal (NC) quantum dot arrays. Conduction through a NC array can be reduced with a negative voltage and then restored with a positive voltage. Light can also be used to restore...

20060221676 - Circuitry for use in current switching a magnetic cell: A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells, providing a bit line, providing a plurality of word lines, providing bit line read/write logic, and providing a plurality of switches for the bit line. Each of...

20060221673 - Highly efficient segmented word line mram array: In an MRAM array based on MTJs, the size of segmented word line select transistors and their associated connections become a significant overhead, especially when the operating point is chosen deep along the hard axis of the asteroid curve. This problem has been overcome by placing the big segmented word...

20060221674 - Mram cell with domain wall switching and field select: An MRAM cell includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship and separated by a non-magnetic tunneling barrier layer. The first magnetic region includes a reference layer having a fixed magnetization adjacent the tunneling barrier layer. The second magnetic region includes...

20060221677 - Switchable element: A memory element, logic element or sensor element is provided, which element comprises a switchable first magnetic component exhibiting a ferromagnetic or ferrimagnetic behaviour and comprising at least two magnetic domains with different magnetisation directions and a domain wall between the magnetic domains. The element has electrodes operable to induce...

20060221675 - System and method for hardening mram bits: A system and method for protecting MRAM bits during a dose rate event is described. A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include...

20060221678 - Circuit for reading memory cells: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of...

20060221679 - Method of programming memory cell array: A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state...

20060221680 - Magnetic random access memory, magnetic random access memory manufacturing method, and magnetic random access memory write method: A magnetic random access memory includes first and second write wirings, the second write wiring having first and second crossing angles formed by crossing the first write wiring, a first magnetoresistive element having a first axis of easy magnetization directed to a side of the first crossing angle and having...

20060221681 - Non-volatile memory device with threshold voltage control function: Even when the number of rewrite operations varies among erase unit areas, the number of rewrite operations is improved for all of the erase unit areas. A flash EEPROM 100 comprises a trimming value storing area 130 of storing a trimming value corresponding to each erase unit area 120 included...

20060221683 - Compensating for coupling in non-volatile storage: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly...

20060221687 - Electrically alterable non-volatile memory with n-bits per cell: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of...

20060221686 - Integrated circuit that uses a dynamic characteristic of the circuit: An integrated circuit has a first component that has a dynamic characteristic that varies among like integrated circuits, for example, among integrated circuits fabricated using the same lithography mask. Operating the first component produces an output that is dependent on the dynamic characteristic of the first component. A digital value...

20060221685 - Non-volatile multi-level semiconductor flash memory device and method of driving same: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely,...

20060221684 - Printing apparatus and control program updating method: A printing apparatus which obtains, through a network, updating data for an updating process to update a control program for executing a printing process on the basis of print data has: a confirming unit which confirms its own operating state when the updating data is obtained; and an updating processing...

20060221688 - Semiconductor integrated circuit and nonvolatile memory element: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The...

20060221690 - Test mode for detecting a floating word line: Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage...

20060221689 - Write once type recording medium, recording device and recording method for write once type recording medium, and reproduction device and reproduction method for write once type recording medium: On a write-once-type recording medium 10, there are provided: a definite defect management area 13 to definitely record therein defect management information; and a plurality of temporary defect management areas 14A, 14B, and 14C to temporarily record therein the defect management information. If the recording medium 10 is not yet...

20060221682 - Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same: Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and...

20060221692 - Compensating for coupling during read operations on non-volatile memory: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly...

20060221691 - Layout for nand flash memory array having reduced word line impedance: A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plurality of word lines. A...

20060221696 - Method for non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of...

20060221693 - Non-volatile memory and method with compensation for source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This...

20060221694 - Non-volatile memory and method with control gate compensation for source line bias errors: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This...

20060221695 - Page buffer circuit of flash memory device: A page buffer circuit of a flash memory device includes a plurality of page buffers connected to a predetermined number of bit lines, respectively, and also connected to a Y-gate circuit, the page buffers perform a read operation or a program operation at the same time in response to bit...

20060221700 - Charge packet metering for coarse/fine programming of non-volatile memory: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory...

20060221699 - Nonvolatile semiconductor memory: The nonvolatile semiconductor memory includes a plurality of memory devices for storing data, a write circuit for supplying a high voltage for data writing, a plurality of selectors connected between the write circuit and the plurality of memory devices, for selecting one from the plurality of memory devices; and a...

20060221698 - Nonvolatile semiconductor memory device and manufacturing method of the same: The invention realizes a smaller-sized OTP memory cell and large reduction of its manufacturing process and cost. An embedded layer (BN+) to be a lower electrode of a capacitor is formed in a drain region of a cell transistor of an OTP memory, a capacitor insulation film having a small...

20060221697 - Use of data latches in multi-phase programming of non-volatile memories: A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach...

20060221701 - Time division driven display and method for driving same: A time division driven display and a method for driving the same. The display includes a panel having data lines, a source driver having output pins, a precharge controller and a demultiplexer. The precharge controller electrically connected to these data lines selects one from these data lines to precharge. The...

20060221702 - Decoding circuit for non-binary groups of memory line drivers: A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In...

20060221703 - Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells: Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages...

20060221705 - Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells: A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a...