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Static information storage and retrieval September class, title,number 09/06

20060209583 - Method and apparatus for address allotting and verification in a semiconductor device: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of...

20060209584 - Securely field configurable device: A field configurable device, such as an FPGA, supports secure field configuration without using non-volatile storage for cryptographic keys on the device and without requiring a continuous or ongoing power source to maintain a volatile storage on the device. The approach can be used to secure the configuration data such...

20060209585 - Nonvolatile semiconductor memory device: A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array,...

20060209586 - Semiconductor component and method for fabricating it: A semiconductor component has a semiconductor body in which a trench structure is provided. An electrode structure embedded in the trench structure is at least partly insulated from its surroundings by an insulation structure, and is contact-connected in a contact-connecting region via a contact hole that penetrates through an upper...

20060209587 - High density memory device: This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory density (e.g., 1015 bits/cm3), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices are intrinsically latchable,...

20060209589 - Foreign object detector: A foreign object detector for a note validator, the detector includes means defining a note path and gate means in the note path operable between an open position for allowing a note to pass the gate means and a fully closed position for preventing a note from passing the gate...

20060209588 - Proton and heavy ion seu resistant sram: A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a second passive...

20060209590 - Amorphous layers in a magnetic tunnel junction device: An improved TMR device is disclosed. The ferromagnetic layers of the device, particularly those that contact the dielectric tunneling layer have an amorphous structure as well as a minimum thickness (of about 15 Å). A preferred material for contacting the dielectric layer is CoFeB. Ways of overcoming problems relating to...

20060209591 - Mram cell structure and method of fabrication: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key...

20060209594 - Memory device with time-shifting based emulation of reference cells: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to...

20060209592 - Non-volatile memory and method with power-saving read and program-verify operations: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation...

20060209593 - Semiconductor memory device: A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit, wherein each memory cell is set to have...

20060209595 - Systems and methods for write protection of non-volatile memory devices: A write protection mechanism may be implemented that is external to a non-volatile memory device and/or that is external to controller/s that interface with the non-volatile memory device, thus providing increased security over unauthorized and/or undesirable write cycles to the memory device. Write protection security may be further enhanced by...

20060209596 - Multiple level programming in a non-volatile memory device: The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory block. The upper page of the memory block is then programmed....

20060209597 - Compact non-volatile memory cell and array system: NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are...

20060209598 - Inverter non-volatile memory cell and array system: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used...

20060209599 - Nonvolatile semiconductor memory: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile...

20060209600 - Simultaneous reading from and writing to different memory cells: A nonvolatile memory array includes a grid of word lines WL1, . . . ,WL6 and bit lines BL1, . . . ,BL8. Of a plurality of memory cells 210, each memory cell is located at an intersection region of one of the word lines and one of the bit...

20060209601 - Page buffer for preventing program fail in check board program of non-volatile memory device: A page buffer in which the value of data that have been latched in a register of a page buffer is not changed by slowly transmitting data to the register in a check board program operation of a NAND flash memory device. The page buffer includes a first register having...

20060209602 - Column selection signal generator of semiconductor memory device: A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal generated by an external clock signal. The column...

20060209603 - Method and apparatus for supporting verification, and computer product: An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation...

20060209604 - Negative voltage driving for the digit line isolation gates: A system and method to reduce standby leakage current in the event of row-to-column shorts in a memory chip or in an electronic device having memory or data storage elements is disclosed. In case of memory rows or wordlines precharged to a negative wordline voltage (VNWL), the standby leakage current...

20060209605 - Non-volatile memory device having buffer memory with improve read speed: Non-volatile memory devices may include a buffer memory corresponding to one block of a memory cell array, thus improving a read operation. The non-volatile memory device may include a memory cell array including a plurality of memory blocks, each having memory cells disposed at the intersections of bit lines and...

20060209606 - Low power delay controlled zero sensitive sense amplifier: In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive...

20060209607 - Receiver circuit: A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises a first amplifier stage and a second...

20060209608 - Sense amplifier systems and methods: Systems and methods provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier for a memory array is disclosed having an associated precharge circuit and a read completion detection circuit....

20060209609 - Method for operating a flash memory device: An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion of the error correction code is not exceeded....

20060209610 - Semiconductor memory and method for analyzing failure of semiconductor memory: A counter controller stops a counter operation of a refresh counter to keep a counter output signal at a constant value when the counter output signal takes a predetermined value relating to a specific address. A state where the specific address is refreshed is maintained, and the failure analysis is...

20060209611 - Semiconductor memory device having complete hidden refresh function: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated....

20060209612 - Semiconductor storage device: A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side...

20060209613 - Memory modules and methods: Embodiments of memory modules and corresponding methods are disclosed. One memory module embodiment includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second...

20060209614 - Method of designing layout of semiconductor integrated circuit and apparatus for doing the same: A method of designing a layout of a functional block and an on-chip capacitor in a semiconductor integrated circuit, includes the steps of (a) designing a layout of a capacitor/block including a functional block, and an on-chip capacitor having a predetermined capacity and disposed adjacent to the functional block, (b)...

20060209615 - Data reproduction device and method, and program: Memory resources can be optimized by dynamically determining a threshold value of a storage device used for buffering in accordance with a compression rate of data for streaming reproduction. A data reproduction device for temporarily storing compressed data that is downloaded from a server 5 and sequentially performing the streaming...

20060209616 - Phase change memory device and associated wordline driving circuit: A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a...

20060209617 - Simulating a floating wordline condition in a memory device, and related techniques: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines...

20060209619 - Data input circuit of synchronous semiconductor memory device using data sampling method for changing dqs domain to clock domain: Provided is a data input circuit of a semiconductor memory device. The data input circuit includes: an input buffer that samples an external data signal in response to a data strobe signal and outputs a first-sampled signal; a first domain converter that samples the first-sampled signal in response to a...

20060209618 - Efficient register for additive latency in ddr2 mode of operation: An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive...

20060209620 - Synchronous clock generator including duty cycle correction: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal...

20060209621 - Optical disk recording/reproducing apparatus: An optical disc recording/reproducing apparatus is provided which can obtain the best recording quality. Data is recorded while tracking is displaced by gradually supplying an offset voltage (deviation value) to a tracking error signal, and then reproduction is performed on a recording area. The jitter value (reading state of address...

20060203530 - Compact ternary and binary cam bitcell architecture with no enclosed diffusion areas: Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert...

20060203529 - Cutting cam peak power by clock regioning: A CAM device architecture where CAM cells are divided into at least two arrays and each array is operated in a different clock domain so that at no time are the arrays simultaneously drawing maximum power. By dividing the CAM array into a plurality of arrays and staggering the search...

20060203532 - Early read after write operation memory device, system and method: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory...

20060203531 - Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit: A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer...

20060203533 - Semiconductor device and operating method thereof: To provide a memory element that positively utilizes a phenomenon such as a dielectric breakdown, differently from a conventional memory element, and to provide a memory device having an increased memory capacity. The invention provides a memory device having a pair of electrodes and multiple memory material layers stacked between...

20060203534 - Polarization switching digital to analog converter and method: A polarization switching digital to analog converter has a ferroelectric capacitor. A number of switches are coupled to the ferroelectric capacitor. A summing circuit is coupled to the one of the switches....

20060203535 - Semiconductor, functional device, electrochromic device, optical device, and image-taking unit: A semiconductor comprises a compound (A) adsorbed on a surface of the semiconductor, the compound (A) having at least one lone electron pair and substantially not undergoing in oxidation-reduction reactions, wherein the presence of the compound (A) negatively changes a flat band potential of the semiconductor with reference to that...

20060203536 - Memory device with reduced leakage current: A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal...

20060203539 - Magnetization reversal methods for magnetic film, magnetoresistive films, and magnetic memories using them: A magnetization reversal method is a method of applying an external magnetic field to a magnetoresistive film, in which the magnetoresistive film has a structure wherein a nonmagnetic film is placed between magnetic films with an easy axis of magnetization along a perpendicular direction to a film plane and in...

20060203538 - Magnetoresistive effect element and magnetic memory: A TMR element has a free first magnetic layer, a second magnetic layer with a fixed magnetization direction provided above one surface of the first magnetic layer, a nonmagnetic insulating layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer with a fixed magnetization...

20060203537 - Methods and devices for determining writing current for memory cells: Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to...

20060203540 - Semiconductor memory device with magnetoresistance elements and method of writing data into the same: A semiconductor memory device includes memory cells, first wirings, a first current driver circuit, and a second current driver circuit. The memory cell includes a magneto-resistive element having a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating...

20060203541 - Phase change memory device: A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to...

20060203542 - Semiconductor integrated device: A semiconductor non volatile memory device capable of multiple write operations with high reliability is implemented. The memory device includes memory cells, each comprising a first electrode, a second electrode, and an information storage section put between the two electrodes, wherein an operation to feed a first pulse current from...

20060203543 - Non-volatile memory device and method for fabricating the same: A non-volatile memory device having a split gate type cell structure, a method for fabricating the same, and a method for fabricating a semiconductor device by using the same are provided. A non-volatile memory device includes a substrate, a plurality of patterned tunnel insulation layers formed on the substrate, a...

20060203544 - Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first...

20060203545 - Memory sensing circuit and method for low voltage operation: A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop...

20060203546 - Method of achieving wear leveling in flash memory using relative grades: For each block of a memory, a number is calculated that is a function of how many times the block has been erased and of how many times at least one other block has been erased. The numbers are stored in the memory device that includes the memory. The numbers...

20060203547 - Semiconductor memory device: A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile semiconductor memory cells arranged therein, the first and second cell arrays being disposed in the direction of each bit line for transferring cell data and physically independent of each other; a sense amplifier disposed...

20060203548 - Multi-plane type flash memory and methods of controlling program and read operations thereof: A multi-plain type flash memory device comprises a plurality of plains each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plain or latching an output data bit to be received from the corresponding plain, cache buffers each...

20060203549 - Page buffer circuit of flash memory device with reduced consumption power: A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to reduce consumption power in the standby mode....

20060203550 - Flash memory device with improved erase function and method for controlling erase operation of the same: The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device includes memory cell blocks, each having a plurality of memory cells sharing local word lines and bit lines, an...

20060203551 - Method for reading flash memory cell, nand-type flash memory apparatus, and nor-type flash memory apparatus: A method of reading a flash memory cell, a NAND-type flash memory apparatus, and/or a NOR-type flash memory apparatus improves the resolution capability and reduces the determination time by using different voltages applied at the read operation of the flash device. As a result, it is possible to reduce sizes...

20060203554 - Multi-state memory cell with asymmetric charge trapping: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the...

20060203555 - Multi-state memory cell with asymmetric charge trapping: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the...

20060203553 - Nand string wordline delay reduction: An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it...

20060203552 - Process of fabricating flash memory with enhanced program and erase coupling: Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends...

20060203556 - Flash memory controller utilizing multiple voltages and a method of use: A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high...

20060203557 - Semiconductor storage device and semiconductor storage device driving method: A semiconductor storage device comprises a semiconductor layer; a plurality of memory cells formed on the semiconductor layer, data writing, erasing or reading with respect to each of the memory cells being possible based on a voltage applied to a control electrode and a voltage applied to the semiconductor layer;...

20060203558 - Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory...

20060203559 - Memory device with customizable configuration: One embodiment of the present invention relates to a memory device in a package comprising a plurality of data output ports, a plurality of internal data lines for providing data to and from a memory unit, a switching unit which is operable, depending on an operational mode, either to connect...

20060203563 - Charge packet metering for coarse/fine programming of non-volatile memory: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory...

20060203560 - Driving method of nonvolatile memory and nonvolatile memory used in the same method: To increase a cell current ratio of a program state to an erase state of two bit storage nonvolatile memory cells and reduce power consumption, a program state of MONOS-typed memory cells is a state where electrons are injected into two local regions near drain and source junction edges, an...

20060203561 - Non-volatile memory and control with improved partial page program capability: In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold...

20060203562 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be...

20060203565 - Flash memory device with improved pre-program function and method for controlling pre-program operation therein: A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an erase controller generating a pre-program control signal in response to an erase command; and a voltage selection circuit selecting one of...

20060203564 - Memory device having off-chip driver enable circuit and method for reducing delays during read operations: A memory device capable of performing a read operation includes: a memory array that stores data; and off-chip drivers that supply as an output of the memory device data retrieved from the memory array. At least one of the off-chip drivers includes: an enable circuit that generates an enable signal...

20060203566 - Nonvolatile memory device for storing data and method for erasing or programming the same: A method for erasing or programming a nonvolatile memory device comprising a memory cell, a sense amplifier, and a page memory, the method comprising the steps of: performing an erasure or programming operation in a manner dependent on the data stored in the page memory, reading out the content of...

20060203567 - Integrated memory circuit and method for repairing a single bit error: The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an...

20060203568 - Overdrive period control device and overdrive period determining method: An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit supplying a power source...

20060203569 - Current mode output driver: A current mode output driver and output current control method of controlling an output current using a gate voltage are provided. The current mode output driver, which outputs data read from a memory core to a transmission line, includes a gate voltage control circuit, a bias circuit, and a driver...

20060203571 - Input and output buffers having symmetrical operating characteristics and immunity from voltage variations: A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical topology. Each of the combined differential amplifiers includes a pair of transistors coupled to each other as a current mirror. The current mirror transistors are coupled in series with...

20060203570 - System and method for storing a sequential data stream: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow...

20060203572 - Low supply voltage temperature compensated reference voltage generator and method: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with...

20060203574 - Pre-emphasis for strobe signals in memory device: Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory...

20060203573 - Semiconductor device, semiconductor memory device and data strobe method: Semiconductor devices having an interface of an open drain or a pseudo-open drain type are provided, and the semiconductor devices include a data strobe (DQS) control signal generating circuit, a DQS control circuit and an output unit. The generating circuit generates a first DQS control signal and a second DQS...

20060203577 - Data output controller in semiconductor memory device and control method thereof: A data output controller of a high-speed memory device and a method therefor. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a second section...

20060203575 - Memory with data latching circuit including a selector: A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is configured to delay the data signal to provide a delayed data signal. The selector is configured to receive the delayed data...

20060203576 - Semiconductor memory and system apparatus: A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a...

20060203578 - Apparatus and method for self-correcting cache using line delete, data logging, and fuse repair correction: An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs...

20060203579 - Device and method for compensating defect in semiconductor memory: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit...

20060203580 - Programmable element latch circuit: An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to...

20060203581 - Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and...

20060203582 - Memory compiler redundancy: An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on...

20060203584 - Modified persistent auto precharge command protocol system and method for memory devices: A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disable command. Memory devices operating according this method...

20060203583 - Semiconductor memory and data read method of the same: According to the present invention, there is provided a semiconductor memory having: a memory cell array in which a plurality of memory cells each holding data made up of first data and second data are arranged at least along a column direction; a plurality of word lines running along a...

20060203585 - Differential read-out circuit for fuse memory cells: A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells (F2, F3). The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells (F2, F3). The...

20060203586 - Semiconductor memory device: A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a...

20060203587 - Partition of non-volatile memory array to reduce bit line capacitance: The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors...

20060203588 - Semiconductor memory: When it is judged that real bit lines connected to real memory cells are liable to be connected to adjacent circuit elements to be electrically short-circuited, dummy bit lines are connected to voltage lines which supply voltages to the circuit elements. For example, the dummy bit lines are directly connected...

20060203590 - Dynamic random access memories and method for testing performance of the same: The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of...

20060203589 - Self refresh period signal generation device: A self refresh period signal generating device includes an internal temperature sensor; an extended mode register set for storing a first temperature code which corresponds to temperature measured by an external temperature sensor; a selection means for selecting one of the first temperature code included in the extended mode register...

20060203591 - One time programmable read-only memory comprised of fuse and two selection transistors: A one time programmable read-only memory (OTPROM) device includes a plurality of memory cells, where a memory cell of the OTPROM device comprises a fuse indicating a first memory state of the memory cell if the fuse is destroyed and a second memory state of the memory cell if the...

20060203592 - Reduced area, reduced programming voltage cmos efuse-based scannable non-volatile memory bitcell: An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal of the fuse. A programming voltage can be supplied...

20060203593 - Reduced area, reduced programming voltage cmos efuse-based scannable non-volatile memory bitcell: An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal of the fuse. A programming voltage can be supplied...

20060203594 - Large voltage generation in semiconductor memory device: A semiconductor memory device is disclosed. The device is provided with at least one purpose-specific voltage generator such as a VPP generator. The device is further provided with a circuit for generating a voltage for programming an anti-fuse element by the use of at least one of purpose-specific voltages such...

20060203595 - Multiple memory device management: Multiple memory devices can be managed as though they were one memory device. A memory device that has a logical memory address map can be replaced with multiple memory devices that each has an address range that is a subset of the logical memory address map. When one of the...

20060203596 - Semiconductor integrated circuit device: A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the block. The block decoder includes a logical address register holding logical block address corresponding to the several blocks and a...

20060203597 - Multiport memory device: A multiport memory device according to an embodiment of the invention includes first and second input ports, first and second output ports, and a memory cell array. The device further includes: an input data selector for selecting one of the first and second input ports to send input data to...

20060203598 - Decoder for memory device: A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls...

20060203599 - Detection of row-to-row shorts and other row decode defects in memory devices: A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current...

20060203600 - Low power word line control circuits with boosted voltage output for semiconductor memory: A word line control device has a word line driver for deactivating and activating a word line to control access to a memory cell, and a voltage coupling device for coupling voltages to the word line driver....

20060203601 - Memory device and method having programmable address configurations: A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied...

20060203604 - Display device: A display device is provided, which includes, a substrate, a plurality of gate lines formed on the substrate, a gate driver disposed on the substrate and transmitting gate signals to the gate lines, a repair gate driver disposed on the substrate and having a structure substantially the same as that...

20060203603 - Memory arrangement and method for processing data: A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access to the memory. An...

20060203605 - Multi-phase clock signal generator and method having inherently unlimited frequency capability: A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The...

20060203602 - Self-timed interface for strobe-based systems: Self-timed interfaces and methods are provided for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed interface couples the strobe signal to a receiver that samples data of data line under control...

20060203606 - System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series...

20060203607 - Fully-hidden refresh dynamic random access memory: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the...

20060198174 - Contents providing system, output control device, and output control program: A contents providing system is provided with an information obtaining unit that obtains at least one of input information input to a user interface of a client device and output information output from the user interface, a content searching unit that searches for contents in accordance with the information obtained...

20060198176 - Low noise amplifier: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting...

20060198175 - Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems: A technique is discussed for a different memory sub system topology to allow for separating impedance discontinuity The trace lengths from the MCH and the trace lengths to each memory device is calculated based at least in part on a frequency domain and time domain analysis. The new topology improves...

20060198177 - Memory device: A memory device comprising a main body, a first connect head, a transmission wire and a second connect head is provided. A memory is disposed inside the main body for storing digital data. The first connect head is disposed at one end of the main body and electrically connected to...

20060198178 - Memory stacking system and method: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the...

20060198179 - Multi-resistive integrated circuit memory: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum...

20060198180 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line...

20060198181 - Static random access memory utilizing gated diode technology: A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have...

20060198182 - Memory device with external magnetic field generator and method of operating and manufacturing the same: A memory device with a magnetic field generator and method of operating and manufacturing the same. In the device and method, a magnetic memory may includes a magnetic tunneling junction (MTJ) cell, a transistor, and a bit line, and a magnetic field generator external to the magnetic memory to generate...

20060198183 - Semiconductor device: With a semiconductor device using a phase change material, in particular, an increase in the number of circuit elements associated with a testing function is checked to the minimum, and an easier test on the semiconductor device is implemented. When a retention test and so forth are conducted on a...

20060198185 - Magnetic device and method of making the same: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic...

20060198184 - Magnetic memory device and write method of magnetic memory device: A magnetic memory device includes a first write wiring which runs in a first direction, a second write wiring which runs in a second direction different from the first direction, and a magnetoresistive element which is arranged at an intersection between the first and second write wirings, has a fixed...

20060198186 - Error reduction circuit for chalcogenide devices: An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance....

20060198188 - Method for operating page buffer of nonvolatile memory device: A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is carried out using one among several latch circuits included in the page buffer. The method activates a first latch circuit while...

20060198189 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060198190 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060198191 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a global-bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which...

20060198192 - Boosting to control programming of non-volatile memory: A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings...

20060198194 - Noise suppression in memory device sensing: NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or...

20060198193 - Reduction of adjacent floating gate data pattern sensitivity: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a...

20060198196 - Nonvolatile semiconductor memory having a plurality of interconnect layers: A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged...

20060198195 - Self-boosting method for flash memory cells: A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as...

20060198187 - Memory device with a ramp-like voltage biasing structure based on a current generator: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting...

20060198197 - Ultra-low power limiter: An over-voltage protection circuit (i.e., a limiter), includes: a first switching block having a plurality of semiconductor elements, serially connected to each other and turned on in sequence according to the magnitude of an input voltage; and a plurality of second switching blocks, in which each of the second switching...

20060198198 - Semiconductor integrated circuit: According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change...

20060198201 - Multi-bits storage memory: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs...

20060198199 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed...

20060198200 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be...

20060198202 - Flash memory backup system and method: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash...

20060198203 - Method of erasing a flash memory cell: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the...

20060198204 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations....

20060198206 - Semiconductor device and inspection method of the same and electromagnetic detection equipment: A heat detection equipment as electromagnetic detection equipment is combined with a semiconductor integrated circuit including, without setting an extra external test terminal, a control circuit for outputting chip information and resistors driven for generating thermal energy that is a kind of electromagnetic waves to obtain manufacturing information and inspection...

20060198207 - Semiconductor memory device: Disclosed is an apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide...

20060198205 - User-configurable pre-recorded memory and system: In a user-configurable pre-recorded memory (UC-PM), a user may configure his accessibility and only pays the associated access fee. A UC-PM preferably comprises a pre-recorded memory and an access-control circuit. To protect copyright, pre-recorded contents are preferably encrypted. A UC-PM system offers excellent access control and impenetrable copyright protection. The...

20060198209 - Nano memory, light, energy, antenna and strand-based systems and methods: An apparatus includes a plurality of wash durable clothing strands; an array of nano electronic elements fabricated in the strands; and an array of memory elements coupled to the nano electronic elements. The nano electronic elements can include solar cells, display elements, or antennas, among others....

20060198208 - Publicasting systems and methods: An add-on module provides publicasting functionality to legacy and other devices. Contemplated modules include: (a) a transformation agent that transforms device data to a desired publishable data format for insertion into a remote application, and (b) a consumer interface that publicasts the device data as publishable data to a remote...

20060198210 - Semiconductor device: A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array...

20060198211 - Test system for testing integrated circuits and a method for configuring a test system: The invention relates to a test system for testing connectable integrated circuits. A particular test system may have switching devices via which a respective assigned one of the integrated circuits can be connected to the supply unit, a control unit for controlling the switching devices, and a determination unit in...

20060198212 - Decoder for memory data bus: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page...

20060198214 - Circuits and methods for controlling timing skew in semiconductor memory devices: A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed....

20060198216 - Memory array architecture for a memory device and method of operating the memory array architecture: A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the...

20060198215 - Memory device and method for testing memory devices with repairable redundancy: A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory...

20060198213 - Non-volatile memory element: A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the memory cell exhibiting a first characteristic which is electrically irreversibly modifiable according to the first partial data item, at least...

20060198217 - Multiple level cell memory device with single bit per cell, re-mappable memory block: A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode....

20060198218 - Method and apparatus for optimal write restore for memory: According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the...

20060198219 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is disclosed, which incorporates a mask ROM of a contact program scheme in which a drain contact of each of transistors which constitute a memory cell array is connected to a bit line through an interconnecting pattern and a via plug, wherein a plurality of...

20060198220 - Open digit line array architecture for a memory array: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first...

20060198221 - Minimizing adjacent wordline disturb in a memory device: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined...

20060198222 - Minimizing adjacent wordline disturb in a memory device: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined...

20060198223 - Integrated semiconductor memory having activatable sense amplifiers: An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense coupling” effects upon activation of the sense...

20060198224 - Magnetic memory device: A magnetic memory device includes a plurality of variable resistance elements arranged in parallel between a first and second nodes and having resistance values which vary depending on data stored in the elements, a selection transistor connected to the first node to perform selection on the plurality of variable resistance...

20060198225 - Reducing power consumption in a data storage system: An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjusted in relation to which of the operational and state...

20060198226 - Semiconductor storage device and operating method therefor: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory...

20060198227 - Mixed-voltage interface and semiconductor integrated circuit: A mixed-voltage interface transfers signals serially between a pair of circuit blocks operating at different voltage levels in a semiconductor integrated circuit. Control, address, and data signals are multiplexed onto a common signal line. The number of necessary signal lines is thereby greatly reduced, as compared with parallel signal transfer,...

20060198228 - Various methods and apparatuses to preserve a logic state for a volatile latch circuit: An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power...

20060198229 - Memory device having terminals for transferring multiple types of data: Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information...

20060198230 - Memory device having terminals for transferring multiple types of data: Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information...

20060198232 - Apparatus for memory device wordline: A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower...

20060198231 - Pulse controlled word line driver: The invention relates to a driver circuit for driving a word line of a memory. The driver circuit comprises a driver unit for deactivating the word line after an access to a memory cell, a discharging means for discharging the word line, and a signal generator that generates two control...

20060198235 - Distributed delay-locked-based clock and data recovery systems: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of...

20060198234 - Double data rate scheme for data output: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring...

20060198237 - Method and apparatus for initialization of read latency tracking circuit in high-speed dram: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of...

20060198233 - System and method to change data window: One disclosed embodiment may comprise a system to change a data window. The system may comprise a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated...

20060198236 - Write address synchronization useful for a ddr prefetch sdram: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the...

20060198238 - Modified core for circuit module system and method: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on...

20060198239 - Modular numberical control: A modular, numerical control includes at least two modules, each including a microprocessor unit and being connected to each other via serial data-transmission channels for the transmission of information in the form of data packets. In at least one module, a data-packet generating unit is provided for generating data packets...

20060198174 - Contents providing system, output control device, and output control program: A contents providing system is provided with an information obtaining unit that obtains at least one of input information input to a user interface of a client device and output information output from the user interface, a content searching unit that searches for contents in accordance with the information obtained...

20060198176 - Low noise amplifier: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting...

20060198175 - Method, system, and apparatus high speed interconnect to improve data rates of memory subsystems: A technique is discussed for a different memory sub system topology to allow for separating impedance discontinuity The trace lengths from the MCH and the trace lengths to each memory device is calculated based at least in part on a frequency domain and time domain analysis. The new topology improves...

20060198177 - Memory device: A memory device comprising a main body, a first connect head, a transmission wire and a second connect head is provided. A memory is disposed inside the main body for storing digital data. The first connect head is disposed at one end of the main body and electrically connected to...

20060198178 - Memory stacking system and method: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the...

20060198179 - Multi-resistive integrated circuit memory: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum...

20060198180 - Distributed write data drivers for burst access memories: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line...

20060198181 - Static random access memory utilizing gated diode technology: A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have...

20060198182 - Memory device with external magnetic field generator and method of operating and manufacturing the same: A memory device with a magnetic field generator and method of operating and manufacturing the same. In the device and method, a magnetic memory may includes a magnetic tunneling junction (MTJ) cell, a transistor, and a bit line, and a magnetic field generator external to the magnetic memory to generate...

20060198183 - Semiconductor device: With a semiconductor device using a phase change material, in particular, an increase in the number of circuit elements associated with a testing function is checked to the minimum, and an easier test on the semiconductor device is implemented. When a retention test and so forth are conducted on a...

20060198185 - Magnetic device and method of making the same: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic...

20060198184 - Magnetic memory device and write method of magnetic memory device: A magnetic memory device includes a first write wiring which runs in a first direction, a second write wiring which runs in a second direction different from the first direction, and a magnetoresistive element which is arranged at an intersection between the first and second write wirings, has a fixed...

20060198186 - Error reduction circuit for chalcogenide devices: An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance....

20060198188 - Method for operating page buffer of nonvolatile memory device: A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is carried out using one among several latch circuits included in the page buffer. The method activates a first latch circuit while...

20060198189 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060198190 - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height;...

20060198191 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a global-bit line, first and second section bit lines, a first transistor which connects the global bit line with the first section bit line, a second transistor which connects the global bit line with the second section bit line, a section selection circuit which...

20060198192 - Boosting to control programming of non-volatile memory: A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings...

20060198194 - Noise suppression in memory device sensing: NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or...

20060198193 - Reduction of adjacent floating gate data pattern sensitivity: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a...

20060198196 - Nonvolatile semiconductor memory having a plurality of interconnect layers: A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged...

20060198195 - Self-boosting method for flash memory cells: A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as...

20060198187 - Memory device with a ramp-like voltage biasing structure based on a current generator: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting...

20060198197 - Ultra-low power limiter: An over-voltage protection circuit (i.e., a limiter), includes: a first switching block having a plurality of semiconductor elements, serially connected to each other and turned on in sequence according to the magnitude of an input voltage; and a plurality of second switching blocks, in which each of the second switching...

20060198198 - Semiconductor integrated circuit: According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change...

20060198201 - Multi-bits storage memory: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs...

20060198199 - Non-volatile memory and manufacturing method and operating method thereof: A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed...

20060198200 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be...

20060198202 - Flash memory backup system and method: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash...

20060198203 - Method of erasing a flash memory cell: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the...

20060198204 - Fast read port for register file: Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations....

20060198206 - Semiconductor device and inspection method of the same and electromagnetic detection equipment: A heat detection equipment as electromagnetic detection equipment is combined with a semiconductor integrated circuit including, without setting an extra external test terminal, a control circuit for outputting chip information and resistors driven for generating thermal energy that is a kind of electromagnetic waves to obtain manufacturing information and inspection...

20060198207 - Semiconductor memory device: Disclosed is an apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide...

20060198205 - User-configurable pre-recorded memory and system: In a user-configurable pre-recorded memory (UC-PM), a user may configure his accessibility and only pays the associated access fee. A UC-PM preferably comprises a pre-recorded memory and an access-control circuit. To protect copyright, pre-recorded contents are preferably encrypted. A UC-PM system offers excellent access control and impenetrable copyright protection. The...

20060198209 - Nano memory, light, energy, antenna and strand-based systems and methods: An apparatus includes a plurality of wash durable clothing strands; an array of nano electronic elements fabricated in the strands; and an array of memory elements coupled to the nano electronic elements. The nano electronic elements can include solar cells, display elements, or antennas, among others....

20060198208 - Publicasting systems and methods: An add-on module provides publicasting functionality to legacy and other devices. Contemplated modules include: (a) a transformation agent that transforms device data to a desired publishable data format for insertion into a remote application, and (b) a consumer interface that publicasts the device data as publishable data to a remote...

20060198210 - Semiconductor device: A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array...

20060198211 - Test system for testing integrated circuits and a method for configuring a test system: The invention relates to a test system for testing connectable integrated circuits. A particular test system may have switching devices via which a respective assigned one of the integrated circuits can be connected to the supply unit, a control unit for controlling the switching devices, and a determination unit in...

20060198212 - Decoder for memory data bus: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page...

20060198214 - Circuits and methods for controlling timing skew in semiconductor memory devices: A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed....

20060198216 - Memory array architecture for a memory device and method of operating the memory array architecture: A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the...

20060198215 - Memory device and method for testing memory devices with repairable redundancy: A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory...

20060198213 - Non-volatile memory element: A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the memory cell exhibiting a first characteristic which is electrically irreversibly modifiable according to the first partial data item, at least...

20060198217 - Multiple level cell memory device with single bit per cell, re-mappable memory block: A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode....

20060198218 - Method and apparatus for optimal write restore for memory: According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the...

20060198219 - Semiconductor integrated circuit device: A semiconductor integrated circuit device is disclosed, which incorporates a mask ROM of a contact program scheme in which a drain contact of each of transistors which constitute a memory cell array is connected to a bit line through an interconnecting pattern and a via plug, wherein a plurality of...

20060198220 - Open digit line array architecture for a memory array: A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first...

20060198221 - Minimizing adjacent wordline disturb in a memory device: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined...

20060198222 - Minimizing adjacent wordline disturb in a memory device: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined...

20060198223 - Integrated semiconductor memory having activatable sense amplifiers: An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to “post-sense coupling” effects upon activation of the sense...

20060198224 - Magnetic memory device: A magnetic memory device includes a plurality of variable resistance elements arranged in parallel between a first and second nodes and having resistance values which vary depending on data stored in the elements, a selection transistor connected to the first node to perform selection on the plurality of variable resistance...

20060198225 - Reducing power consumption in a data storage system: An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjusted in relation to which of the operational and state...

20060198226 - Semiconductor storage device and operating method therefor: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory...

20060198227 - Mixed-voltage interface and semiconductor integrated circuit: A mixed-voltage interface transfers signals serially between a pair of circuit blocks operating at different voltage levels in a semiconductor integrated circuit. Control, address, and data signals are multiplexed onto a common signal line. The number of necessary signal lines is thereby greatly reduced, as compared with parallel signal transfer,...

20060198228 - Various methods and apparatuses to preserve a logic state for a volatile latch circuit: An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power...

20060198229 - Memory device having terminals for transferring multiple types of data: Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information...

20060198230 - Memory device having terminals for transferring multiple types of data: Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information...

20060198232 - Apparatus for memory device wordline: A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower...

20060198231 - Pulse controlled word line driver: The invention relates to a driver circuit for driving a word line of a memory. The driver circuit comprises a driver unit for deactivating the word line after an access to a memory cell, a discharging means for discharging the word line, and a signal generator that generates two control...

20060198235 - Distributed delay-locked-based clock and data recovery systems: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of...

20060198234 - Double data rate scheme for data output: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring...

20060198237 - Method and apparatus for initialization of read latency tracking circuit in high-speed dram: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of...

20060198233 - System and method to change data window: One disclosed embodiment may comprise a system to change a data window. The system may comprise a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated...

20060198236 - Write address synchronization useful for a ddr prefetch sdram: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the...

20060198238 - Modified core for circuit module system and method: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on...

20060198239 - Modular numberical control: A modular, numerical control includes at least two modules, each including a microprocessor unit and being connected to each other via serial data-transmission channels for the transmission of information in the form of data packets. In at least one module, a data-packet generating unit is provided for generating data packets...