Static information storage and retrieval inventions 08/06

20060193159 - Fast pattern matching using large compressed databases: A pattern matching system includes, in part, a multitude of databases each configured to store and supply compressed data for matching to the received data. The system divides each data stream into a multitude of segments and optionally computes a data pattern from the data stream prior to the division...

20060193160 - Semiconductor device: Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and...

20060193161 - Processes for turning a sram cell off and processess for writing a sram cell: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second...

20060193162 - Ferroelectric memory and semiconductor memory: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a...

20060193163 - Program circuit of semiconductor: A semiconductor integrated circuit device includes a storage element, program circuit, and sensing circuit. The storage element stores information by electrically irreversibly changing the element characteristics. The program circuit programs the storage element by electrically irreversibly changing its element characteristics. The sensing circuit senses the irreversibly changed element characteristics of...

20060193164 - Semiconductor memory device: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of...

20060193165 - Magnetoresistive element and magnetic memory device: A magnetoresistive effect element according to the present invention is comprised of a TMR element that is disposed at an intersection where a bit line and a write word line intersect with each other, in a manner sandwiched between the bit line and the write word line, and is configured...

20060193167 - Compact non-volatile memory array with reduced disturb: A non-volatile memory (NVM) array is made of NVM cells that have a floating gate transistor and a select transistor in which the floating gate transistor requires only a single layer of polysilicon. Adjacent cells are arranged so that the floating gates are staggered rather than being in the same...

20060193168 - Integrated semiconductor memory and method for operating a semiconductor memory: An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a...

20060193166 - Semiconductor device and method of operating a semiconductor device: The invention considers a non-volatile semiconductor memory device comprising a first and second floating gate transistor, which are coupled in series. Each floating gate transistor comprises a floating gate. Programming means coupled to the first and second floating gate transistor are operable to place a selected electrical charge in one...

20060193170 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus: An electro-optical device includes first and second substrates that are bonded to each other, the first substrate having an extended portion extended from the second substrate on a first side thereof in plan view, a plurality of pixel units that are disposed in a pixel region on the first substrate...

20060193172 - High bandwidth datapath load and test of multi-level memory cells: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The...

20060193169 - Multiple level programming in a non-volatile memory device: The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels....

20060193171 - Semiconductor memory devices having signal delay controller and methods performed therein: A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell....

20060193173 - Non-volatile semiconductor memory device and data programming method: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the electron emission from the floating gates of...

20060193174 - Non-volatile and static random access memory cells sharing the same bitlines: A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile...

20060193175 - Nonvolatile memory device and method of manufacturing the same: The nonvolatile memory device includes a semiconductor substrate on which a source, a drain, and a channel region are formed, a tunneling oxide film formed on the channel region, a floating gate formed of a transition metal oxide (TMO) on the tunneling oxide, a blocking oxide film formed on the...

20060193176 - Multiple level programming in a non-volatile memory device: The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory block. The upper page of the memory block is then programmed....

20060193177 - Position based erase verification levels in a flash memory device: The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to the cell's location with respect to array ground. A cell in the middle of a row of cells between array grounds is verified...

20060193178 - Non-volatile memory device with erase address register: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory...

20060193179 - Method and apparatus for determining the geometric correspondence between multiple 3d rangefinder data sets: A method, computer program product, and apparatus for obtaining the geometric correspondence between at least two 3D range data sets obtained using a 3D rangefinder device. First and second 3D range data sets are provided. The first 3D range data set is displayed as a 2D displayed image. The second...

20060193180 - Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can...

20060193181 - Sram bus architecture and interconnect to an fpga: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled...

20060193182 - Information processing apparatus and method, memory control device and method, recording medium, and program: A memory control device for writing to a memory data input via a port section and for reading from the memory data output via the port section includes setting means for setting, in accordance with a transfer speed of first input data input via the port section, a write-enable time...

20060193183 - Reducing dq pin capacitance in a memory device: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT...

20060193184 - Hub module for connecting one or more memory chips: The invention relates to a hub module for connecting one or more memory chips, said module having an address input for connection to an address bus in order to receive an address of the memory area to be addressed and having an address output for connection to a further address...

20060193186 - Method of designing semiconductor chip and program for use in designing semiconductor chip: Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to improve yield. A priority order list...

20060193185 - Semiconductor device with a plurality of fuse elements and method for programming the device: A device and method for programming the semiconductor device that includes a plurality of first fuse-sets which store first information, wherein each of the first fuse-sets includes at least one first fuse element and the first information has been compressed, a second fuse-set including at least one second fuse element...

20060193187 - Disk drive unit having reduced electrical power consumption: A disk drive unit for a disk, e.g. for use in a mobile device, comprises a spindle (1) positioned within the disk drive unit and adapted to support the disk rotatably in an operating position. An electric motor (2) is operatively coupled to the spindle (1) to rotate it. An...

20060193188 - Memory interface methods and apparatus: Memory interface methods and apparatus for processing source synchronous data from a memory device (DRAM). The methods and apparatus synchronously transfer data from the memory device to a memory controller even though the time variability of read return strobe signals is greater than one clock cycle....

20060193189 - Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices: A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. Furthermore, the second memory device...

20060193191 - Contactless bidirectional nonvolatile memory: A contactless memory architecture has a column of bidirectional multi-bit memory cells between each adjacent pair of diffused lines in a bank. The architecture includes about half as many metal lines as diffused lines, and bank select cells at both ends of the bank. Most bank select cells connect respective...

20060193190 - Multi-bank memory: A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed....

20060193192 - Method for identifying memory bit cells and connections: A method for identifying memory bit cells and connections. The method includes defining a bit pattern for each bit cell node in a bit cell; defining a node pattern for each node in a circuit block; and matching the node patterns with the bit patterns, wherein bit cells and corresponding...

20060193193 - High speed data bus: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and...

20060193195 - Apparatus and method for controlling clock signal in semiconductor memory device: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially...

20060193194 - Data strobe synchronization for dram devices: Methods and apparatus that determine, at a device (e.g., a DRAM device), a phase difference between two externally supplied timing signals such as a clock signal (CLK) and a data strobe signal (DQS) are provided. Adjustments may be made to timing of one of the signals itself or other internal...

20060193196 - Semiconductor memory device having a precharge control circuit and an associated precharge method: We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the...

20060187697 - Rom with a partitioned source line architecture: A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a...

20060187698 - System and method for dynamic checking: Systems and methods for utilizing dynamic checks is provided. A user provides user identification information via a POS terminal. The identification information is used to obtain account information such that a representation of the dynamic check may be generated based on the account information. The dynamic check is populated with...

20060187699 - Semiconductor devcie with isolation layer: The invention relates to a semiconductor device, which is arranged in a semiconductor body (1), and which comprises at least one source region (4) and at least one drain region (5), each being of the first conductivity type, and at least one body region (8) of the second conductivity type,...

20060187700 - Single event effect (see) tolerant circuit design strategy for soi type technology: A method of designing an integrated circuit to be Single Event Upset (SEU) immune by converting one or more Single Event Transient (SET) sensitive transistors into at least two serially connected transistors, and spacing the transistors sufficiently far apart so that the probability of a specified high-energy particle striking both...

20060187701 - Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method: In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G1, G2) for the writing voltage and the erasure voltage differ...

20060187702 - Memory integrated circuit, in particular an sram memory integrated circuit, and corresponding fabrication process: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a...

20060187703 - Magnetoresistive effect element, magentic memory device and manufacturing method of magnetoresistive effect element and magnetic memory device: A magnetoresistive effect element (1) has an arrangement in which a pair of ferromagnetic material layers (magnetization fixed layer (5) and magnetization free layer (7)) is opposed to each other through an intermediate layer (6) to obtain a magnetoresistive change by causing a current to flow in the direction perpendicular...

20060187704 - Spin based sensor device: A spin based electronic device can be used as a magnetic field sensor. The device uses ferromagnetic materials for implementing a variable spin resistance. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus...

20060187705 - Magnetic cell and magnetic memory: A magnetic cell includes a first ferromagnetic layer whose magnetization is substantially fixed in a first direction; a second ferromagnetic layer whose magnetization is substantially fixed in a second direction opposite to the first direction; a third ferromagnetic layer provided between the first and the second ferromagnetic layers, a direction...

20060187706 - 2-transistor floating-body dram: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation...

20060187707 - Non-volatile memory array with simultaneous write and erase feature: A non-volatile transistor memory array, having individual cells, each individual cell having a current injector transistor and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line,...

20060187709 - Twin insulator charge storage device operation and its fabrication method: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be...

20060187710 - Method for operating page buffer of nonvolatile memory device: A method for operating a page buffer of a nonvolatile memory device includes activating a first latch circuit of the page buffer in a programming operation and inactivating the first latch circuit in a copy-back programming operation. A second latch circuit is activated in both the copy-back programming operation and...

20060187711 - Gate structure of a non-volatile memory device and method of manufacturing same: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating...

20060187712 - Reduction of adjacent floating gate data pattern sensitivity: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a...

20060187708 - Device state control method and information processing apparatus: A device state control method for use in an information processing apparatus that has a body, a device connectable to the body, a storage portion which stores information of a state of power supply to the device, the device state control method including: determining whether the information of state of...

20060187714 - Flash memory cell arrays having dual control gates per memory cell charge storage element: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory...

20060187713 - Processing information management in a plasma processing tool: A computer-implemented method for managing substrate processing data. Substrate process data is acquired while a substrate is processed in a plasma-processing chamber of a cluster tool. The method includes receiving meta-data that identifies at least one of an identification of the substrate and a process. The method further includes receiving...

20060187715 - System and method for performing concatentation of diversely routed channels: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in...

20060187716 - Reduction of adjacent floating gate data pattern sensitivity: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a...

20060187717 - Robust face detection algorithm for real-time video sequence mobile drive with expansion capacity, stackable, mobile storage device and control circiut thereof: A stackable mobile storage device is provided, including a first mobile drive, at least a second mobile drive and a detachable module plugged between the first mobile drive and the second mobile drive to stack each other. The detachable module is composed of a male connector and a female connector....

20060187718 - Shift register, method of controlling the same, electro-optical device, and electronic apparatus: It is provided a method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series. The storage unit has a hold gate and stores a logical level of a pulse when the hold gate...

20060187719 - Semiconductor package, id generating system thereof, id recognizing system thereof, id recognition method thereof, semiconductor integrated circuit chip, id generating system thereof, id recognizing system thereof, and id recognition method thereof: In ID generation for a semiconductor package or a semiconductor integrated circuit chip, a topographic characteristic to be utilized as specific information is selected from at least one topographic characteristic that the semiconductor package or the semiconductor integrated circuit has. Then, the selected topographic characteristic is measured as the specific...

20060187720 - Semiconductor device: A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1”...

20060187721 - Random access memory including selective activation of select line: A random access memory that includes an array of memory cells, a first circuit configured to receive an address to address memory cells in the array of memory cells, and a second circuit. The second circuit is configured to obtain control signals including an address strobe signal and gate the...

20060187723 - Nonvolatile semiconductor memory device having improved redundancy relieving rate: In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the...

20060187722 - Panel assembly for display device, display device including the same, and repairing method for display device: A panel assembly for a display device and a display device having the panel assembly are provided. The panel assembly for a display device includes a display region including a plurality of pixels and most of display signal lines connected to the pixels, a plurality of repair lines disposed in...

20060187726 - Memory bus checking procedure: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . ....

20060187725 - Semiconductor memory device: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line and reduces current consumption in the non-select bit line. The semiconductor memory device includes...

20060187724 - Test for weak sram cells: A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102)....

20060187728 - Integrated semiconductor memory: An integrated semiconductor memory (100) comprises a controllable voltage generator (30) for precharging bit lines (BL) of a memory cell array (10) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first...

20060187727 - Self-addressed subarray precharge: Power consumption in an integrated circuit memory is reduced by lowering the power supply demand from an on-chip pumped VCCP power source. Only the row decoders for subarrays in a memory bank that were previously activated are precharged in response to a bank precharge command. Additional circuitry is provided to...

20060187729 - Source synchronous communication channel interface receive logic: A network device for determining an optimal sampling phase for source synchronous data received on a data communications channel. The network device includes a transmitter clock domain for providing a data pattern along with a synchronous free-running clock. The network device also includes a plurality of phases of a core...

20060187732 - Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function: According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed...

20060187730 - Semiconductor device and display device utilizing the same: A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the...

20060187731 - Semiconductor memory device: A semiconductor memory device is provided for minutely changing a refresh interval according to a detected temperature and thereby lowering its power consumption. A temperature detector detects a temperature of a chip and outputs the corresponding temperature signal. A reference temperature signal output unit outputs the corresponding reference temperature signal...

20060187733 - Semiconductor device: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective...

20060187734 - Semiconductor integrated circuit and ic card: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the...

20060187735 - Indexation by transposition of matrix of large dimension: A data processing system comprises a first memory and a second memory including a sparse direct matrix comprising full boxes storing a data item and a column index and addressable consecutively. A module dimensions a transposed matrix, by reading row by row column indices of the direct matrix so as...

20060187738 - Memory management device and memory device: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an...

20060187736 - Non-volatile memory device conducting comparison operation: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a...

20060187737 - Pattern layout of word line transfer transistors in nand flash memory which executes subblock erase: A semiconductor device includes a memory cell array, first and second selection circuits, and transfer transistors. The first selection circuit selects a block in the memory cell array. The second selection circuit selects several memory cells in the block to erase the memory cells corresponding to word lines in the...

20060187739 - Methods and apparatus for using memory: In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total...

20060187741 - Method and apparatus for avoiding bi-directional signal fighting of serial interface: A method and apparatus for avoiding bi-directional signal fighting of a serial interface is disclosed. The serial peripheral interface includes a clock signal line and a data line. In this method, during normal operation, a first clock signal is received and transformed to output a second clock signal in the...

20060187740 - System and method for mode register control of data bus operating mode and impedance: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data...

20060187742 - Nonvolatile ferroelectric memory and control device using the same: A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged...

20060181910 - Content addressable memory including a dual mode cycle boundary latch: A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data...

20060181908 - Method and apparatus for controlling the timing of precharge in a content addressable memory system: A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated...

20060181909 - Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask: A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The...

20060181911 - Static content addressable memory cell: A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a...

20060181912 - Low-power solid state storage controller for cell phones and other portable appliances: A storage controller comprising a first interface to exchange data with an appliance, such as a cell phone; a second interface to exchange data with a host system and receive power from the host system to provide power to the appliance; and a solid state memory to provide the appliance...

20060181913 - Semiconductor memory device with strengthened power and method of strengthening power of the same: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers;...

20060181914 - Alignment mode selection mechanism for elastic interface: Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if...

20060181916 - Non-volatile memory cell for storage of a data item in an integrated circuit: The present invention relates to a non-volatile memory cell for storage of a data item in an integrated circuit, comprising a resistive memory element which may have different conductance states depending on the stored data item, a memory unit for passing the stored data item to an integrated circuit, a...

20060181915 - Phase change memory device providing compensation for leakage current: A semiconductor memory device includes a plurality of phase change memory cells connected to the same bitline and different respective word lines. A read operation is performed on one of the memory cells by selecting the bitline and a corresponding wordline. While the read operation is performed, leakage current produced...

20060181919 - Embedded dram gain memory cell: A high density horizontal merged MOS-bipolar gain memory cell is realized for DRAM operation. The gain cell includes a horizontal MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a horizontal bi-polar transistor having an emitter region, a base region...

20060181917 - Semiconductor memory device for low voltage: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device...

20060181918 - Semiconductor memory device with dual storage node and fabricating and operating methods thererof: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor,...

20060181920 - Resistive memory element with shortened erase time: A resistive memory element for reversibly switching between a high-resistance OFF state and a low-resistance ON state includes a reactive electrode, an inert electrode and a solid electrolyte arranged between the two electrodes. The resistive memory element further includes a nanomask structure arranged in the solid electrolyte, in particular at...

20060181921 - Method for writing data into memory and the control device: A method for writing data into the memory, especially a method of preventing the data from overwriting for the write operation, is disclosed. The invention provides a control device for a memory system, which utilizes at least two layers of latches to hold the inputted data from a data bus...

20060181922 - Resetting phase change memory bits: A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse...

20060181923 - Nonvolatile semiconductor memory device: A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which...

20060181924 - Non-volatile memory device and method for operation page buffer thereof: A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit...

20060181925 - Nonvolatile memory cell arrangement: Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent...

20060181926 - Semiconductor memory device and method for writing to semiconductor memory device: The semiconductor memory device comprising: an n-channel memory cell transistor including: a first diffused region and a second diffused region formed in a semiconductor substrate; a charge storage layer formed over the semiconductor substrate between the first diffused region and the second diffused region; and a gate electrode formed over...

20060181927 - Mtp nvm elements by-passed for programming: Non-Volatile Memory (NVM) cells include a selection circuit for providing an output based on selecting between an input data signal and an output of a Multiple Time Programmable (MTP) NVM element. The input data signal may be latched by a latch circuit such as a flip-flop first. The selector circuit's...

20060181929 - Semiconductor memory device: To implement a high reliability and large number of rewrite operations by optimizing reliability margins of both data “0” and data “1” or a reliability margin of one of the data “0” or data “1” with a circuit for monitoring a rewrite status and a circuit for changing a read...

20060181928 - Wired-or typed page buffer having cache function in a nonvolatile memory device and related method of programming: Disclosed is a page buffer having a wired-OR type structure and a cache function which is adapted for use in a nonvolatile semiconductor memory device and a method of programming same. The page buffer embeds the cache latch block in relation to the cache function. Moreover, the nonvolatile semiconductor memory...

20060181932 - Device and method for pulse width control in a phase change memory device: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and...

20060181930 - Erase verify for non-volatile memory: A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is...

20060181931 - Method and driver for programming phase change memory cell: In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature....

20060181933 - Method and driver for programming phase change memory cell: In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature....

20060181934 - Methods for preventing fixed pattern programming: A method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array....

20060181935 - Semiconductor memory devices and methods of operating the same: A semiconductor memory device may include a plurality of independently operated memory banks each including a plurality of wordlines. At least one of the plurality of wordlines may be activated in response to a slave command and at least one of the wordlines may be activated in response to a...

20060181936 - Apparatus and methods for regulated voltage: An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a...

20060181938 - Charge pump circuit for semiconductor memory device: A charge pump circuit may include a cross-coupled load unit and a bias determination unit. The cross-coupled load unit may receive first and second input signals applied with mutually opposite phases to obtain a charge pumping. The cross-coupled load unit may have first and second output terminals that may be...

20060181937 - Circuits that generate an internal supply voltage and semiconductor memory devices that include those circuits: An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and...

20060181939 - Integrated semiconductor memory with adjustable internal voltage: An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock generator circuit. The supply voltage is provided...

20060181940 - Memory address generating circuit and memory controller using the same: Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a...

20060181941 - Efficient method of test and soft repair of sram with redundancy: Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief....

20060181943 - Memory device having open bit line architecture for improving repairability and method of repairing the same: In a memory device having an open bit line architecture for improving repairability and a method of repairing the memory device, redundant memory cells used to repair defective cells are included even in first and second edge sub-arrays that are arranged at the edges of a memory array. Further, memory...

20060181942 - Switching a defective signal line with a spare signal line without shutting down the computer system: A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an...

20060181944 - Daisy chained multi-device system and operating method: A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to...

20060181945 - Memory: A memory capable of suppressing reduction of data determination accuracy is provided. This memory comprises a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current,...

20060181946 - Full-stress testable memory device having an open bit line architecture and method of testing the same: A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and...

20060181947 - Method and system for low power refresh of dynamic random access memories: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored...

20060181948 - System and method for detecting and reducing data corruption in a storage device: A data storage system using flash storage maintains a status indicator corresponding to data written into the flash storage. The status indictor of the data indicates whether a disruption, such as a power disruption or a device disconnection, occurred when the data was being written into the flash storage. The...

20060181950 - Apparatus and method for sram decoding with single signal synchronization: A memory decoding apparatus includes a plurality of local subarray support circuits associated with a memory subarray, and a common bus locally configured with respect to said plurality of local subarray support circuits, the common bus configured for synchronous activation of one or more of the plurality of local subarray...

20060181949 - Operating system-independent memory power management: Embodiments of the present invention can reduce the power consumption of memory systems by powering down unused portions of memory, independent of operating system activity....

20060181951 - Method and apparatus for address generation: A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the...

20060181954 - Circuit and method for writing a binary value to a memory cell: A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled...

20060181952 - Programmable analog control of a bitline evaluation circuit: The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global...

20060181955 - Semiconductor integrated circuit device: A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with...

20060181953 - Systems, methods and devices for providing variable-latency write operations in memory devices: A memory system includes storage cells, a respective one of which is configured to store a fixed charge therein when a write voltage applied thereto is above a predetermined threshold voltage and to discharge the fixed charge therefrom when the write voltage applied thereto is below the threshold voltage. The...

20060181956 - Memory device having components for transmitting and receiving signals synchronously: One embodiment of the present invention provides a memory device comprising an array of memory cells, a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface, an input/output section for exchanging data, address and control signals with...

20060181957 - Register read for volatile memory: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read...

20060176721 - Method and apparatus for managing ternary content addressable memory: A method for managing a ternary content addressable memory (CAM) comprises the steps of: dividing the ternary CAM into parts corresponding to a number of sequence IDs determined by a packet classification rule set by a system manager; storing a packet having a priority set according to the packet classification...

20060176722 - Method of operating a content addressable memory with reduced instantaneous current and power consumption during a search: The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at...

20060176723 - Memory module and memory system having the same: A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to...

20060176724 - Phase change memory device: A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a...

20060176725 - Pmc memory circuit and method for storing a datum in a pmc memory circuit: The invention relates to a PMC memory circuit comprising a PMC memory cell having a PMC component, the PMC component having a solid electrolyte with permanently introduced defects, so that the PMC component has a hysteresis with regard to its I-V characteristic curve with an upper and a lower current...

20060176726 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060176730 - Global bit line restore timing scheme and circuit: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset...

20060176728 - Local bit select circuit with slow read recovery scheme: Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is...

20060176729 - Local bit select with suppression of fast read before write: A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors....

20060176731 - Multifunctional latch circuit for use with both sram array and self test device: An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from...

20060176727 - Radiation-hardened sram cell with write error protection: A method and system is disclosed for preventing write errors in a Single Event Upset (SEU) hardened static random access memory (SRAM) cell. A compensating element has been connected to a feedback path of the SRAM cell. The compensating element operates to cancel out capacitive coupling generated in an active...

20060176732 - Sram and dual single ended bit sense for an sram: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended...

20060176733 - Method of switching an mram cell comprising bidirectional current generation: The present invention relates to a method of switching a magnetoresistive memory (MRAM) cell comprising the following steps: providing an MRAM cell having a magnetic tunnel junction including first and second magnetic regions; said first magnetic region exhibiting a fixed magnetization, said second magnetic region exhibiting a free magnetization which...

20060176734 - Double-decker mram cells with scissor-state angled reference layer magnetic anisotropy and method for fabricating: A double-decker MRAM cell is provided, including a stacked structure of first and second magnetic tunnel junctions. Each magnetic tunnel junction includes free and fixed magnetic regions made of magnetic material separated by a tunneling barrier layer made of non-magnetic material. The fixed magnetic regions are pinned by at least...

20060176735 - Magnetic tunnel junction device and method of manufacturing the same: The MR ratio of an MTJ device is increased. A single-crystalline MgO (001) substrate 11 is prepared, and then an epitaxial Fe (001) lower electrode (first electrode) 17 with a thickness of 50 nm is grown on a MgO (001) seed layer 15 at room temperature. Annealing is then performed...

20060176736 - Flash memory cell arrays having dual control gates per memory cell charge storage element: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory...

20060176737 - Method for reading flash memory cell, nand-type flash memory apparatus, and nor-type flash memory apparatus: A method of reading a flash memory cell, a NAND-type flash memory apparatus, and/or a NOR-type flash memory apparatus improves the resolution capability and reduces the determination time by using different voltages applied at the read operation of the flash device. As a result, it is possible to reduce sizes...

20060176738 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a...

20060176739 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a...

20060176740 - Flash memory devices with flash fuse cell arrays: A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse sense amplifying circuits. The first, second and third flash fuse cell fusing circuits all share...

20060176741 - Method and apparatus for driving flash memory: A method for driving a flash memory and flash memory apparatus thereof are provided. The flash memory apparatus comprises a flash memory controller and a flash memory. At first, a voltage level of the parameter definition pin is detected by the flash memory controller to obtain the basic configuration of...

20060176742 - Semiconductor device and writing method: A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted...

20060176743 - Write driver circuit for memory array: Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global...

20060176744 - Low power chip select (cs) latency option: A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents...

20060176745 - Compilable memory structure and test methodology for both asic and foundry test environments: A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for...

20060176747 - Circuit for interfacing local bitlines with global bitline: A circuit for interfacing local bitlines to a global bitline. The circuit includes a first device having an input coupled to a first local bitline in a first memory sub-array. A second device has an input coupled to a second local bitline in a second memory sub-array. An interface line...

20060176746 - Method and apparatus for driver circuit: An embodiment includes a first semiconductor element coupled between a precharge signal and a node, the first semiconductor element to allow current to flow from the precharge signal to the node when a positive voltage is present on the precharge signal, and a switching device coupled between the node and...

20060176748 - Dynamic memory for a cellular terminal: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize...

20060176749 - Semiconductor memory device that requires refresh operations: A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the...

20060176750 - Circuit and method for reading an antifuse: An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and compare a sense current at the sense node relative to...

20060176752 - Integrated semiconductor memory: An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interconnects, but preferably at the end of each interconnect. The comparator circuits...

20060176751 - Methods and apparatus for implementing a power down in a memory device: A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device,...

20060176754 - Flat cell read only memory using common contacts for bit lines and virtual ground lines: In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of the memory. Moreover,...

20060176753 - Global bit select circuit with dual read and write bit line pairs: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit....

20060176755 - Semiconductor memory device: Disclosed is a semiconductor memory device which includes a sense amplifier, arranged between a first mat and a second mat, switches for controlling the connection between first and second bit lines of each of the first and second mats on one hand and the sense amplifier on the other, and...

20060176757 - High performance cmos nor predecode circuit: A CMOS decoder with an FET stack coupled to the input node so that when all the inputs are selected, the FET stack is conducting and initially holds the value on the input node, and prevents dipping of the input node voltage....

20060176758 - Semiconductor memory devices having negatively biased sub word line scheme and methods of driving the same: Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative voltage are adjusted to a negative voltage. The...

20060176756 - Write control circuitry and method for a memory array configured with multiple memory subarrays: Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively...

20060176761 - Clock generating circuit with multiple modes of operation: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying...

20060176760 - Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays: A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal...

20060176759 - Variable clocking read capture for double data rate memory devices: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first...

20060171183 - Content addressable memory circuit with improved memory cell stability: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells...

20060171184 - Low power content addressable memory system and method: A low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized cam cell groups, each cam cell group having one or more cam cells; a valid entry tag bit associated with each said content addressable memory cell; a match...

20060171185 - Module for reading data carriers: A module for reading data carriers, with a processor arrangement and a reading unit,—wherein the module is designed for incorporation in a data processing device,—wherein addressable coded data are stored on the data carrier, and—wherein the processor arrangement comprises a decoding function and is for this purpose designed for—receiving a...

20060171186 - Ferro-electric memory device: The present invention provides a ferro-electric memory device which suppresses the deterioration of the retention characteristics at the time when an ambient temperature has decreased, without requiring much longer cycle time. The ferro-electric memory device includes a first ferro-electric capacitor intended for use in a first normal cell and a...

20060171187 - Rectifying charge storage memory circuit: A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as a read only memory (ROM)....

20060171191 - Memory architecture of display device and memory writing method for the same: A memory architecture of display device comprises a memory cell array having a plurality of memory cells arranged as a plurality of cell rows and a plurality of cell columns, and a data latch circuit having a plurality of latch units for storing a plurality of bits; wherein the number...

20060171188 - Memory cell with stability switch for stable read operation and improved write operation: A memory cell and method of destabilizing a memory cell for facilitating a write operation are provided. A stability switch is coupled between one of a voltage supply or a ground terminal and the memory cell, and is turned off during the write operation to reduce the drive voltage required...

20060171194 - Programmable matrix array with chalcogenide material: A chalcongenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a...

20060171195 - Semiconductor memory device: In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in...

20060171192 - Semiconductor storage device: The SRAM cell 1 includes inverters 10, 20, N-type FETs (Field Effect Transistors) 32, 34, 36, 38, word lines 42, 44, and bit lines 46, 48. A gate width W2 and gate length L2 of the FETs 32, 34, 36, 38 are equal to a gate width W3 and gate...

20060171193 - Semiconductor storage device: An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read...

20060171189 - Sram cell using tunnel current loading devices: An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel...

20060171190 - Systems and methods for accessing memory cells: Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a...

20060171197 - Magnetoresistive memory element having a stacked structure: A magnetoresistive memory element has a stacked structure including: a tunneling barrier made of non-magnetic material, a first magnetic system with a ferromagnetic tunneling junction reference layer barrier having a fixed magnetic moment vector on one side of the tunneling adjacent to the non-magnetic material, and a second magnetic system...

20060171196 - Method for writing to magnetoresistive memory cells and magnetoresistive memory which can be written to by the method: A method for writing to the magnetoresistive memory cells of a MRAM memory, includes applying write currents respectively onto a word line and a bit line. A superposition of the magnetic fields generated by the write currents in each memory cell selected by the corresponding word lines and bits lines...

20060171198 - Spin-injection magnetic random access memory: A spin-injection magnetic random access memory according to an embodiment of the invention includes a magnetoresistive element having a magnetic fixed layer whose magnetization direction is fixed, a magnetic recording layer whose magnetization direction can be changed by injecting spin-polarized electrons, and a tunnel barrier layer provided between the magnetic...

20060171199 - Magnetic random access memory with memory cell stacks having more than two magnetic states: A magnetic random access memory (MRAM) has memory units or stacks of multiple memory cells arranged in the X-Y plane on the MRAM substrate with each memory unit having four possible magnetic states. Each memory unit is located at an intersection region between two orthogonal write lines and has two...

20060171201 - Nonvolatile latch: A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the...

20060171200 - Memory using mixed valence conductive oxides: A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion....

20060171202 - Memory system and data writing method: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which...

20060171203 - Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a...

20060171204 - Memory device and method for operating the same with high rejection of the noise on the high-voltage supply line: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between...

20060171205 - Flash cell fuse circuit and method of fusing a flash cell: A flash cell fuse circuit includes a fuse cell array, a plurality of switch circuits and a plurality of fuse sense amplifiers. The fuse cell array outputs first signals in response to word line enable signals after a program or erase operation. The switch circuits pass one of the first...

20060171206 - Non-volatile memory and fabricating method and operating method thereof: A non-volatile memory is provided. A well is disposed in a substrate and a shallow well is disposed inside the well. At least two stack gate structures are disposed on the substrate. Drain regions are disposed in the shallow well outside the stack gate structures. An auxiliary gate layer is...

20060171207 - Nonvolatile semiconductor memory device: The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, first of...

20060171208 - Apparatus and method for speeding up access time of a large register file with wrap capability: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses,...

20060171209 - Charge trap memory cell with multi-doped layers, flash memory array using the memory cell and operating method of the same: The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the...

20060171210 - Nonvolatile semiconductor memory device which uses some memory blocks in multilevel memory as binary memory blocks: A nonvolatile semiconductor memory device includes a memory cell array, interface, and write circuit. The write circuit can selectively write data in the memory cell array by first write procedures or second write procedures in accordance with a data write command input to the interface. When a data write command...

20060171211 - Semiconductor memory device and method for multiplexing write data thereof: A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device further includes a memory core region including an array of memory cells, a data input path that receives data to...

20060171212 - Nonvolatile memory device with load-supplying wired-or structure and an associated driving method: We describe a nonvolatile memory device with a wired-OR structure and method of driving the same that reduces peak current during the wired-OR operation. The nonvolatile semiconductor memory device includes a memory cell array including a plurality of bitlines and a plurality of memory cells to store data. A plurality...

20060171213 - Control of voltages during erase and re-program operations of memory cells: A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate...

20060171214 - Internal voltage generation control circuit and internal voltage generation circuit using the same: An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command...

20060171216 - Apparatus for controlling activation period of word line of volatile memory device and method thereof: An apparatus for controlling an activation period of a word line of a volatile memory device is disclosed. The apparatus adjusts the activation period of the word line using a member for adjusting a pulse width of a pulse signal that activates the word line according to an operation mode...

20060171215 - High density bitline selection apparatus for semiconductor memory devices: A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines...

20060171217 - Apparatus and method for low cost, multi-port protocol analysis and monitoring: A multiport concentrator concentrates network data from different links in a network and carried on a plurality of lower speed lines into a stream of data carried on a higher speed line. A measurement system determines network statistics from the stream of data carried by the higher speed line....

20060171219 - Memory array decoder: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein...

20060171218 - Semiconductor memory device having n-bit prefetch type and method of transferring data thereof: A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch type, from an array of memory cells are precharged with a ½ power supply...

20060171221 - Method for analyzing critical defects in analog integrated circuits: The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further...

20060171220 - Test data topology write to memory using latched sense amplifier data and row address scrambling: For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality of sense amplifier latches. The initial row of memory cells is deactivated while the latched...

20060171223 - Integrated circuit devices having precharge and equalization circuits therein and methods of operating same: An integrated circuit device may include an equalization transistor having first and second current carrying terminals electrically coupled to first and second signal lines, respectively, and a gate terminal responsive to an enable signal. A first body voltage control circuit may also be provided. This control circuit includes a first...

20060171222 - Memory device: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines....

20060171224 - 1t-nmemory cell structure and its method of formation and operation: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the...

20060171225 - Memory devices and methods of operation thereof using interdependent sense amplifier control: A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of data from a memory cell to the local input/output line...

20060171226 - Semiconductor memory device with column to be selected by bit line selection signal: A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the...

20060171227 - Low-voltage reading device in particular for mram memory: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first...

20060171228 - Semiconductor device: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The logic gate 70 is connected to the input end...

20060171229 - Semiconductor device: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having...

20060171232 - High speed low voltage driver: A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage....

20060171231 - Memory device: A memory device capable of reducing power consumption when the operation mode is a deep power down mode, includes an external power source voltage line through which an external power source voltage is supplied; an internal voltage line through which an internal voltage generated in an internal voltage generator is...

20060171230 - Method and apparatus for providing the proper voltage to a memory: A method includes querying a memory to determine what type of voltage the memory requires and applying the proper operating voltage to the memory based on the query. An apparatus that supports different memory types is also disclosed....

20060171234 - Ddr ii dram data path: Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a...

20060171233 - Near pad ordering logic: Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a...

20060171235 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device comprises a semiconductor substrate; a cell well formed in the semiconductor substrate; a first sub cell array including part of a cell array of NAND cells arranged in array in the cell well; a second sub cell array including the remainder of the cell array...

20060171236 - Semiconductor device: A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided...

20060171237 - Semiconductor memory device: In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side...

20060171238 - Semiconductor memory device: A semiconductor memory device includes an interface unit connected to an external circuit, a data memory unit including a write data line, a read-out data line, a data control unit, and a memory block connected to the data control unit, and a read-out latch block connected between a read-out data...

20060171239 - Dual port memory unit using a single port memory core: A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory...

20060171240 - Bitline selection circuitry for nonvolatile memories: Bit lines of a memory device are arranged by an interleaving of even and odd bit lines and segregated into an even and odd bank. A discharge network discharges the banks alternately. A bit line selection network alternately connects the banks to a sense amplifier. The bank of odd bit...

20060171242 - Semiconductor memory device and method of controlling sub word line driver thereof: A semiconductor memory device includes a sub word line driver for selectively connecting one of sub word lines with a main word line and applying a boosted voltage having a level higher than a power source voltage to a selected sub word line. The device includes a sub word line...

20060171241 - Semiconductor memory device capable of selectively refreshing word lines: A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether data has been written to any of...

20060171244 - Chip layout for multiple cpu core microprocessor: A microprocessor chip on a semiconducting substrate has at least two CPU cores that have hot spots on one side, a private cache memory for each CPU core that is located on the same side of said CPU core as the hot spot, a common cache memory that can be...

20060171243 - Memory array circuit with word line timing control for read operations and write operations: A timing controller for a memory cell circuit provides separate sense amplifier timing signals and write circuit timing signals during respective read and write cycles of the memory cell circuit. Timing of word line read enable signals is different than timing of word line write enable signals, and is correlated...

20060171245 - Read and/or write detection system for an asynchronous memory array: This invention provides an asynchronous electronic circuit that has an asynchronous memory circuit where the memory cells are arranged in columns and rows. The asynchronous circuit includes a read completion detection circuit and a write completion detection circuit that determines an end of the read cycle or the write cycle...

20060171246 - Semiconductor memory device: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an...

20060171247 - Semiconductor memory module with bus architecture: A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R×4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside...