Static information storage and retrieval inventions 07/06

20060164876 - Multi-transistor memory cells: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor....

20060164878 - Data reading method, data writing method, and semiconductor memory device: In a data reading method according to the present invention, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell. Next, reference signal generating data corresponding to a high level side is written to the memory cell....

20060164877 - Memory: A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal...

20060164879 - Non-volatile ferromagnetic memory having sensor circuitry shared with its state change circuitry: Several methods may be employed to make this cell including, but not limited to, electroplating, sputtering, E-beam deposition, chemical vapor deposition and molecular beam epitaxy. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of the present invention...

20060164880 - Switching element method of driving switching element rewritable logic integrated circuit and memory: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact...

20060164881 - Static semiconductor memory device: A static semiconductor memory device includes a memory cell formed in a memory cell region; and a dummy memory cell formed in a dummy memory cell region. The memory cell includes a power supply wiring and a ground wiring which are provided to extend in a direction of a word...

20060164882 - Storage controller using vertical memory: Storage development using vertical memory is described. A memory system includes a controller and a non-volatile memory array. The non-volatile memory array is vertically stacked relative to the controller. The controller communicates with external devices through an interface and processes requests from the external devices to store and retrieve data....

20060164884 - Method of dynamically controlling program verify levels in multilevel memory cells: Pre-program verify levels for a multilevel read-only memory cell are generated dynamically. A determination takes into account a program verify level, an over-program budget, and a second-bit effect budget to generate pre-program verify levels. The generated pre-program verify levels mitigate issues of over-programming, hard-to-program, and second-bit effect....

20060164883 - Multi-valued scrambling and descrambling of digital data on optical disks and other storage media: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a...

20060164885 - [method for reducing data error when falsh memory storage device using copy back command]: A method of a flash memory storage device using a copy back command is provided. An error correction rule is adopted to determine whether or not data errors occurred in the un-amended data stored in the page, wherein when it is determined that data errors has occurred in the un-amended...

20060164886 - Nonvolatile semiconductor memory device having protection function for each memory block: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When...

20060164887 - Method and apparatus for changing operating conditions of nonvolatile memory: A nonvolatile memory array is associated with counting memory that stores data on a number of times a particular threshold state is reached in the associated nonvolatile memory. The aging physical characteristics of the nonvolatile memory can be compensated by adjusting the operating conditions of the nonvolatile memory. The operating...

20060164889 - Microcomputer and microprocessor having flash memory operable from single external power supply: A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory...

20060164888 - Voltage down-converter with reduced ripple: A voltage-down converter for providing an output voltage lower than a power supply voltage of the converter is proposed. The converter includes voltage regulation means for obtaining an intermediate voltage corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element with a control signal resulting...

20060164890 - Method of driving a program operation in a nonvolatile semiconductor memory device: In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between a program period and a verifying period. This remarkably improves programming speed and reduces current consumption....

20060164891 - Removable modules with external i/o flexibility via an integral second-level removable slot: The functionality provided to electronic devices by application specific removable modules is enhanced by viewing the removable modules as first-level removable modules and providing them with at least one second-level removable slot for selectively nesting second-level removable modules having particular external I/O capabilities. The functionality provided to the electronic devices...

20060164892 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values...

20060164893 - Defect address storing circuit for semiconductor memory device: A defect address storing circuit for a semiconductor memory device comprises a plurality of fuse pairs formed in a fuse region and a plurality of transistors formed in a transistor region outside the fuse region. The plurality of fuse pairs and the plurality of transistor pairs are arranged to form...

20060164894 - Enabling test modes of individual integrated circuit devices out of a plurality of integrated circuit devices: Methods and apparatus are provided. A common test-mode enable signal is received at two or more integrated circuit devices of an electronic system. A test mode of only an integrated circuit device of the two or more integrated circuit devices that was last to receive a valid command is enabled...

20060164896 - Memory cell array biasing method and a semiconductor memory device: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first...

20060164895 - Semiconductor storage device: A semiconductor storage device includes: a plurality of memory array cells (hereinafter, referred to as cells); a circuit arranged in each of the cells for precharge of each bit line of the cells to a predetermined voltage; and a circuit for comparing, for each bit line, an output voltage of...

20060164897 - Semiconductor storage device having page copying function: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to...

20060164898 - Exploiting a statistical distribution of the values of an electrical characteristic in a population of auxiliary memory cells for obtaining reference cells: In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of...

20060164901 - Power control device and method of multi base powers for optical disk drive: A power control device of single base power is provided for an optical read/write module of an optical disk drive. The optical read/write module generates a power feedback signal and a temperature signal. The power control device includes a current compensating module, a current computing module and a current integrating...

20060164899 - Power control device and method of single base power for optical disk drive: A power control device of single base power is provided for an optical read/write module of an optical disk drive. The optical read/write module generates a power feedback signal and a temperature signal. The power control device includes a current compensating module, a current computing module and a current integrating...

20060164900 - Power control method of optical disk drive: A power control method is provided for an optical disk drive. The optical disk drive has an optical read/write module for accessing an optical storage media. The power control method includes the following steps: measuring the temperature of the optical read/write module; predicting a threshold current of the optical read/write...

20060164902 - Pseudo-synchronization of the transportation of data across asynchronous clock domains: A pseudo-synchronous temporary storage element transports data between two system blocks with different clock systems by pseudo-synchronizing the clock edges of the two clock signals. The pseudo-synchronization circuit may be an integral part of a storage element, a separate pseudo-synchronization device, or a discrete add-on circuit to an off the...

20060164903 - Semiconductor memory device having self refresh mode and related method of operation: A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit...

20060164904 - Dynamic pre-charge level control in semiconductor devices: Dynamic control of a pre-charge level particularly for memory cells is described. In one example, a circuit block has pre-charge node and a power supply is coupled to the pre-charge node to provide either a first power level or a second power level when the circuit block is not active....

20060164905 - Integrated circuit apparatus: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of...

20060164906 - Semiconductor integrated circuit and ic card: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the...

20060164907 - Multiple flash memory device management: Multiple memory devices can be managed as though they were one memory device. A memory device that has a logical memory address map can be replaced with multiple memory devices that each has an address range that is a subset of the logical memory address map. When one of the...

20060164908 - Semiconductor memory device and a method of redressing a memory cell: A semiconductor memory device has a non-auxiliary memory cell, an auxiliary memory cell, a first driver, and a second driver. The non-auxiliary memory cell is connected to a predetermined bit line and a first word line. The auxiliary memory cell is connected to the predetermined bit line and a second...

20060164909 - System, method and storage medium for providing programmable delay chains for a memory system: A memory system including a plurality of delay lines and a processor in communication with the delay lines. The delay lines are in communication with a bus attached to a memory device. The bus includes a plurality of wires and each of the delay lines corresponds to on of the...

20060164910 - Semiconductor memory device capable of performing page mode operation: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit...

20060158916 - Programable identification circuitry: An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer information. The integrated circuit can be a memory device...

20060158917 - Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces: Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any...

20060158918 - Semiconductor memory device: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above...

20060158919 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells using a current flowing through a wiring. A plurality of first write lines are electrically or magnetically or electrically and magnetically connected to the memory cells and provided along a first direction. A first connection line electrically connects at least...

20060158920 - Electrical fuse circuit: An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to...

20060158922 - Semiconductor device: In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation....

20060158921 - Semiconductor integrated circuit device: When the operation frequency is high, in order to cause the rate of change of outputs from an output terminal (OUT) to be abrupt, a selection control signal is caused to be in a low state, thereby causing MOS transistors (T5b, T6b) to be in ON states, thereby causing the...

20060158923 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element, a control switch which controls the application of electrical stress to the storage element, and a control circuit which controls conduction/nonconduction of...

20060158924 - Semiconductor memory device: A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a...

20060158926 - Memory cell and semiconductor integrated circuit device: A memory cell includes a memory cell section and a switching section. The memory cell section includes first and second inverters which are connected to form a flip-flop, and each of the first and second inverters comprises a load transistor and a drive transistor. The switching section is connected with...

20060158925 - Non-volatile static memory cell: A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with...

20060158927 - Spin based electronic device: A thin film sensing device operates based on a spin polarized current. The spin device includes ferromagnetic layers characterized by different coercivities and/or magnetization states, and one or more low transmission barriers in between. The device is further configured so that the spin polarized current flows at least in part...

20060158928 - Phase change memory cell with junction selector and manufacturing method thereof: A memory cell includes a memory element and a selection element coupled to said memory element. The selection element includes a first junction portion, having a first type of conductivity, and a second junction portion, having a second type of conductivity and forming a rectifying junction with the first junction...

20060158929 - Thin film magnetic memory device for conducting data write operation by application of a magnetic field: A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground voltage, respectively....

20060158930 - Cact-tg (catt) low voltage nvm cells: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type...

20060158931 - Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell: An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at...

20060158934 - Electronic memory device having high integration density non-volatile memory cells and a reduced capacitive coupling: A flash NAND electronic memory device includes non-volatile cells having a high integration density and a relative programming method. The memory device is integrated on a semiconductor substrate and includes a matrix with word lines and bit lines organized in sectors of memory cells. The memory device is between the...

20060158935 - Method for compensated sensing in non-volatile memory: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects...

20060158933 - Nand flash memory device having security redundancy block and method for repairing the same: In one aspect, a NAND flash memory device is provided which includes a plurality of main blocks for storing main data, a security block for storing security data, and a plurality of redundancy blocks each for being substituted in place of a failed main block, wherein at least one of...

20060158936 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A...

20060158937 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate...

20060158938 - Method, circuit and systems for erasing one or more non-volatile memory cells: The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments...

20060158932 - Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array: A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is...

20060158939 - Method of erasing data in non-volatile semiconductor memory device while suppressing variation: According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address...

20060158940 - Partial erase verify: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells...

20060158941 - Serial bus controller using nonvolatile ferroelectric memory: A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention,...

20060158943 - Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor: There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor memory device. A bit line voltage switch applies a first supply voltage to a bit line pair in response to a...

20060158944 - Data path having grounded precharge operation and test compression capability: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and...

20060158942 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are...

20060158945 - Readout circuit for semiconductor storage device: By first readout, the current input from a selected cell 13 is converted by a preamplifier 3 and a VCO 4 into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so...

20060158946 - Current sense amplifier for low voltage applications with direct sensing on the bitline of a memory matrix: A current sense amplifier, in particular for low voltage applications, of the type incorporated in a memory electronic device and including a differential amplifier having inputs respectively associated with a matrix circuit leg, connected to a cell to be sensed, and a reference circuit leg, connected a reference cell. At...

20060158947 - Reference sense amplifier for non-volatile memory: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects...

20060158948 - Memory device: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times...

20060158949 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in...

20060158950 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in...

20060158951 - Nonvolatile semiconductor memory device with wired-or structure blocking data transmission from defective page buffer: A nonvolatile semiconductor memory device includes a fuse, a switching enable circuit to generate a switching enable signal in response to a state of the fuse, and a switching unit to couple an internal output line of a page buffer set to a global output line in response to the...

20060158952 - Sram device capable of performing burst operation: Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control...

20060158953 - Logic circuit and word-driver circuit: Disclosed is a logic circuit which comprises first and second MOS transistors which are connected in series between a first signal-input terminal and GND. The gates of the first and second MOS transistors are connected in common to a second signal-input terminal and a connection node between the drains of...

20060158955 - Semiconductor memory device: Disclosed is a semiconductor memory device which comprises an internal clock generating circuit receiving a clock signal from outside to generate an internal clock signal to be supplied to a random access memory. The internal clock generating circuit includes a circuit for canceling internal clock generation for generating a signal...

20060158954 - Semiconductor memory device, system with semiconductor memory device, and method for operating a semiconductor memory device: The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a...

20060152956 - Method and apparatus for performing variable word width searches in a content addressable memory: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search...

20060152957 - Circuit arrangement and method for setting operating parameters in a ram module: An inventive circuit arrangement for setting selected operating parameters in a RAM module contains, for each element in a set of M different operating parameters, a respective value register which is individually assigned, can be set using an individual control signal and is intended to store an item of value...

20060152959 - Multi-time programmable semiconductor memory device and multi-time programming method therefor: A multi-time programmable semiconductor memory device includes a unit array, a unit decoder and a cell distribution circuit. The unit array includes a plurality of programmable units, each of which has a plurality of one-time programmable cells. The unit decoder generates a unit select signal for selecting a programmable unit...

20060152958 - Rom memory cell having defined bit line voltages: The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven state at a memory cell output in a manner dependent on the programming state of the ROM memory cell....

20060152960 - Method to fabricate a thin film non volatile memory device scalable to small sizes: A thin film non volatile memory scalable to small sizes and its fabrication process are disclosed. The thin film memory comprises a thin film transistor control circuitry fabricated on a flexible substrate, together with an optoelectronic cross bar memory comprising a photoconducting material. The thin film non volatile memory can...

20060152961 - Nor-type hybrid multi-bit non-volatile memory device and method of operating the same: A hybrid multi-bit memory device may include a plurality of unit cells arranged in a matrix of a plurality of rows and columns. Each of the unit cells may include a first memory unit and a second memory unit. The first and second memory unit may share a source and...

20060152962 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060152963 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060152966 - Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage: A power (voltage) switching circuit in a semiconductor memory device, capable of reducing leakage current in a standby mode of operation and shortening the wake-up time when a standby mode is switched to an operation mode. The power (voltage) switching circuit comprises a first power switch, a second power switch,...

20060152965 - Memory with reduced bitline leakage current and method for the same: The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an input terminal of one...

20060152964 - Sram having improved cell stability and method therefor: A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a first primary sink current path to the first storage...

20060152967 - Hardmasks for providing thermally assisted switching of magnetic memory elements: An exemplary magnetic random access memory comprises a plurality of hardmasks, a plurality of magnetic memory elements each having been formed using a corresponding one of the hardmasks, and at least one conductor near the hardmasks. The conductor is capable of carrying a current to generate radio frequency electromagnetic fields...

20060152968 - Spin based device with low transmission barrier: An electron spin-based device includes ferromagnetic layers with different coercivities, such that one of such layers is responsive to a magnetic field and the other is fixed. A value of an impedance in the spin based device for a spin polarized current varies in accordance with a relationship between a...

20060152970 - Method and apparatus for current sense amplifier calibration in mram devices: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel...

20060152969 - Mram device with improved stack structure and offset field for low-power toggle mode writing: A magnetic random access memory (MRAM) device includes a reference magnetic region having a resultant magnetic moment vector generally maintained in a desired orientation without the use of exchange coupling thereto. A storage magnetic region has an anisotropy easy axis and a resultant magnetic moment vector oriented in a position...

20060152972 - Thin film magnetic memory device conducting read operation by a self-reference method: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an...

20060152971 - Thin film magnetic memory device reducing a charging time of a data line in a data read operation: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that...

20060152973 - Multi-sensing level mram structure with different magneto-resistance ratios: A new process and structure for a multi-sensing level magnetic random access memory (MRAM) cell having different magneto-resistance (MR) ratios includes an improved magnetic tunnel junction (MTJ) configuration. The MTJ configuration includes a first free layer proximate to a first tunneling barrier and a second free layer proximate to a...

20060152974 - Multi-level ono flash program algorithm for threshold width control: Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases,...

20060152976 - Nonvolatile memory device with load-free wired-or structure and an associated driving method: A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an...

20060152977 - Nonvolatile memory device and method of programming/reading the same: A nonvolatile memory device includes a first memory block including a plurality of memory cells provided between a first drain selection transistor and a source selection transistor; and a second memory block including a plurality of memory cells provided between a second drain selection transistor and the source selection transistor....

20060152978 - Multi-state nrom device: An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected...

20060152975 - Multiple use memory chip: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits....

20060152979 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal...

20060152982 - Integrated semiconductor memory device with test circuit for sense amplifier: An integrated semiconductor memory device includes sense amplifiers that are connected to in each case one bit line pair via controllable voltage generators. In a test mode state, precharging voltages can be fed to at least one of the bit lines of each one of the bit line pairs via...

20060152980 - Low-power delay buffer circuit: A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of...

20060152983 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a...

20060152981 - Solid state disk controller apparatus: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port...

20060152984 - Memory component and addressing of memory cells: A memory component comprises a plurality of memory cells that are each assigned an address, and an address memory for storing numerical values which are uniquely related to addresses of defective memory cells. An address converter having an input for receiving a first address and an output for outputting a...

20060152985 - Output power testing apparatus for memory: An output power testing apparatus for memory is provided. The apparatus includes a signal control device and an adjusting voltage circuit. The signal control device is coupled to the adjusting voltage circuit, and the adjusting voltage circuit adjusts the output voltage based on a set of testing signals from the...

20060152987 - Dual stage dram memory equalization: A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration...

20060152986 - Integrated semiconductor memory device with adaptation of the evaluation characteristic of sense amplifiers: An integrated semiconductor memory device includes memory cells which are connected to first sense amplifiers or second sense amplifiers via in each case one bit line pair. During a read access of one of the memory cells, the sense amplifier connected to the memory cell to be read out evaluates...

20060152988 - Memory component having a novel arrangement of the bit lines: A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row...

20060152989 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in...

20060152990 - Multiple-time electrical fuse programming circuit: A multiple-time electrical fuse programming circuit is described. The circuit includes a programming counter to record the number of programmings, a blowing reference voltage generator to generate a blowing voltage reference wherein the fuse resistance after programming is determined by the blowing voltage reference, at least one self-controlled programmable fuses...

20060152991 - Non-volatile memory storage of fuse information: A fuse-free circuit may include a NAND flash memory cell, and a switch to turn on or off in response to data stored in the NAND flash memory cell. The fuse-free circuit may be embodied in a semiconductor device that also includes an adjustable circuit coupled to the switch. The...

20060152992 - Semiconductor memory device having wordline enable signal line and method of arranging the same: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline...

20060152993 - Electronic apparatus: An electronic apparatus is provided with an arrangement of discrete circuit elements designed to reduce power consumption. Such an arrangement comprises a memory; a memory controller to generate a control signal which controls the memory according to a predetermined operating clock; and a transmission line disposed between the memory controller...

20060152994 - Timer lockout circuit for synchronous applications: A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a...

20060146585 - Low power low area precharge technique for a content addressable memory: A technique to pre-charge a CAM block array including a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, an associated GMAT line, an associated LMAT line, and a group of CAM cells. The pre-charge technique of...

20060146586 - Semiconductor memory device: A semiconductor memory device includes a memory cell array which includes a first group of rows and a second group of rows, each row of the first group consisting of a plurality of first memory cells whose layout direction is a first direction, and each row of the second group...

20060146587 - Method for eliminating crosstalk in a metal programmable read only memory: The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, and a plurality of clamp transistors. When one of the...

20060146592 - Ferroelectric random access memory device and method for driving the same: A ferroelectric random access memory (FRAM) device and a driving method thereof are provided that reduce data loss in an operation of the FRAM device. A power supply supplies a power source to the memory device. A power detection circuit detects a voltage level of the power supply and generates...

20060146591 - Memory device and semiconductor device: A memory circuit includes a latch circuit having a first inverter and a second inverter, a first ferroelectric capacitor that gives a first capacitance to a power supply terminal of the first inverter, a second ferroelectric capacitor that gives a second capacitance different from the first capacitance to a power...

20060146589 - Method for operating a passive matrix-addressable ferroelectric or electret memory device: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage...

20060146588 - Process monitoring for ferroelectric memory devices with in-line retention test: The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors (802). A short delay polarization value is obtained (804) by writing a data value, performing a short delay, and reading the data value. A long delay polarization value...

20060146590 - Semiconductor memory: A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the cell transistor, a plurality of word lines respectively connected with said cell transistor, a plurality of plate lines connected with the other terminal of said ferroelectric...

20060146594 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060146593 - Method and circuit for reading a dynamic memory circuit: A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which...

20060146596 - Configurable storage device: An inexpensive, re-configurable storage circuit for programmable logic devices and application specific integrated circuits is disclosed. The storage circuit comprises: at least one output; and at least two inputs; and at least a one input and a two input response sequence, wherein the inputs change the output in a well...

20060146595 - Methods for forming dram devices including protective patterns and related devices: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the...

20060146597 - Hardware security device for magnetic memory cells: The present invention provides a special structure of magnetic elements, e.g. MRAM elements (10, 11), as a security device (30) for IC's containing magnetic memory cells. The structure may comprise a combination of two or more associated magnetic elements (10, 11) with pre-set anti-parallel magnetization directions. By determining the polarisation...

20060146598 - Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell: The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first...

20060146599 - Magneto-resistance effect element and magnetic memory: The magnetic memory includes a plurality of memory cells, each memory cell including: at least one writing wire; at least one data storage portion, provided on at least one portion of an outer periphery of the writing wire, which comprises a ferromagnetic material whose magnetization direction can be inverted by...

20060146600 - Reading phase change memories to reduce read disturbs: Read disturbs in phase change memories may be reduced by progressively reducing the read pulse falling edges. This may reduce the possibility of quenching and inadvertent amorphization of at least a portion of the bit. As a result, in some embodiments, read disturbs may be reduced....

20060146601 - Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell: A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment...

20060146602 - Mram cell with reduced write current: A magnetic random access memory (MRAM) cell including an MRAM stack and a conductive line for carrying write current associated with the MRAM cell in a direction that is angularly offset from an easy axis of the MRAM stack by an acute angle, such as about 45 degrees....

20060146603 - Method of forming and operating an assisted charge memory device: A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge...

20060146604 - Recording apparatus, recording method, recording medium and program: A recording apparatus which executes copy control utilizing copy control information which is indicative of plural types of copy control includes an electronic watermark detection device, which detects a predetermined copy control information portion of the copy control information out of a content over which an electronic watermark expressing the...

20060146605 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060146606 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060146607 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write...

20060146608 - Integrated circuit including memory array incorporating multiple types of nand string structures: A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical...

20060146609 - Nand flash memory device and method of programming same: Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of...

20060146610 - Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit...

20060146611 - Flash memory device with improved programming performance: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be...

20060146612 - Flash memory devices configured to output data without waiting for bitline and wordline recovery and methods of operating same: A flash memory device includes a memory cell array and an address decoding circuit configured to select bitlines and wordlines of the memory cell array. The device further includes a data sensing circuit configured to read data from a cell of the memory cell array responsive to a selected bitline...

20060146613 - Programming method for controlling memory threshold voltage distribution: A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the...

20060146615 - Method and apparatus for reducing read disturb in non-volatile memory: A memory cell with a charge-trapping structure stores multiple bits. A biasing arrangement is applied to one part of the charge-trapping structure of the memory cell to store a high threshold state, and a biasing arrangement is applied to another part of the charge-trapping structure tending to raise its threshold...

20060146614 - Method for programming a charge-trapping nonvolatile memory cell by raised-vs channel initialed secondary electron injection (chisel): A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive...

20060146617 - Programming and evaluating through pmos injection: A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The transistor is programmed by applying a gate voltage to the gate and generating a drain-to-source voltage across the transistor that is of sufficient magnitude...

20060146616 - Semiconductor memory device and method of supplying wordline voltage thereof: A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first...

20060146618 - Circuit and method for generating boosted voltage in semiconductor memory device: In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response...

20060146619 - Semiconductor memory device and method for controlling the same: A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of...

20060146620 - Semiconductor memory having a spare memory cell: A semiconductor memory encompasses a memory cell array having a spare memory cell array; a holding circuit having banks of fuses, configured to read and hold fuse information; a decision circuit configured to determine which address of memory cell is to be replaced with which spare memory cell based on...

20060146621 - Difference signal path test and characterization circuit: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a...

20060146622 - Performing memory built-in-self-test (mbist): Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing....

20060146623 - Semiconductor device: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large...

20060146624 - Current folding sense amplifier: A method for sensing logical content stored in a memory cell, the method including inputting an input cell current of a selected array cell of a memory array to an input stage, and folding the input cell current and using it to discharge an input of a latch, the latch...

20060146625 - Semiconductor memory: The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected,...

20060146628 - Control circuit for refresh oscillator: The present invention relates to a circuit for controlling a refresh oscillator, and more specifically, to a circuit for controlling a refresh oscillator, wherein refresh characteristics can be tested in a more efficient manner in such a manner that the refresh characteristics are tested at a refresh cycle, which is...

20060146632 - Flash memory device and method for fabricating the same, and programming and erasing method thereof: A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on...

20060146627 - Memory system having multi-terminated multi-drop bus: Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the...

20060146630 - Non volatile semiconductor memory device having a multi-bit cell array: A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a...

20060146626 - Refresh control circuit of pseudo sram: Disclosed herein is a refresh control circuit of a pseudo SRAM. According to the present invention, a single bank select signal for performing a refresh operation on one bank in a period where a chip select signal is enabled, or until a period before a time for reading or writing...

20060146631 - Self refresh oscillator and oscillation signal generation method of the same: A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant...

20060146629 - Semiconductor memory, semiconductor memory system and method of monitoring dynamic temperature thereof: In example embodiments of the present invention, a memory hub control block may be configured to decode a command packet received from a host and determine whether the command packet has designated the memory hub. If the command packet does not designate the memory hub control block, the memory hub...

20060146633 - Device, system and method for power loss recovery procedure for solid state non-volatile memory: A method, device and system for determining whether a prior shut down of a device having a solid state non-volatile memory unit such as a flash memory unit resulted from a power loss and disorderly shut down and whether a power loss recovery procedure should be run....

20060146634 - Semiconductor device: To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output...

20060146635 - Semiconductor device: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch...

20060146636 - Internal power management scheme for a memory chip in deep power down mode: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to...

20060146637 - I/o data interconnect reuse as repeater: Some embodiments may include a memory with a first memory device and data pins, and a second memory device coupled with some of the data pins of the first memory device, allowing the first memory device to operate as a data repeater for the second memory device. An embodiment may...

20060146638 - Memory cell having improved read stability: A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write...

20060146639 - Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder...

20060146640 - Memory device and method for manufacturing the same: A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The...

20060146641 - High speed dram architecture with uniform access latency: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device...