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Static information storage and retrieval June invention type 06/06

20060139980 - Lithographic apparatus and device manufacturing method: A lithography apparatus including a projection system configured to project a beam of radiation as an array of sub-beams of radiation and an array of individually controllable elements configured to modulate the sub-beams of radiation to form a requested dose pattern on a substrate. The requested dose pattern is built...

20060139981 - Electron device, integrated electron device using same, and operating method using same: An electronic device includes at least a memory core formed of an alloy serving as an electronic- conductor and an electrode provided on each of both ends of the memory core. Data is written on the electronic device by supplying an electric current to allow the alloy composition to be...

20060139982 - Non-volatile and-type content addressable memory: In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a ground line, a match control line, and with every row of cells there...

20060139983 - Memory module routing: In some embodiments a memory module circuit board includes a first surface adapted to couple a first plurality of memory devices, a plurality of signal lines, and a command and address bus coupled to the signal lines. The command and address bus is routed from the signal lines and adapted...

20060139984 - Semiconductor device with reduced power consumption: Disclosed is a semiconductor device capable of detecting levels of an external supply voltage, which includes a plurality of signal receivers for simultaneously receiving external input signals, wherein a driving voltage is applied to only one of the signal receivers according to the levels of the external supply voltage....

20060139985 - Non-volatile semiconductor storage device performing rom read operation upon power-on: A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay...

20060139986 - Nonvolatile ferroelectric memory device: A nonvolatile ferroelectric memory device features a multi-bit serial cell structure where read bit lines and write bit lines are divided to control read/write paths individually, thereby improving a transmission operation of serial data. In the nonvolatile ferroelectric memory device, a serial cell that comprises a plurality of switching devices...

20060139987 - Nonvolatile ferroelectric memory device and control method thereof: A nonvolatile ferroelectric memory device and a control method thereof are provided to control read/write operations of memory cell arrays whose channel resistance is differentiated depending on a polarity state of a ferroelectric material. In the device, data read from a memory cell are sensed and amplified through a sense...

20060139988 - Isolation device over field in a memory device: A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the...

20060139989 - Integration of 1t1r cbram memory cells: A memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells with 1T1R architecture, wherein the solid body electrolyte memory cells each comprise a layer stack that comprises at least a bottom and a top electroconductive, in...

20060139990 - Pre-written volatile memory cell: A memory cell of the SRAM type Is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and...

20060139993 - Biosensor and sensing cell array using the same: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic...

20060139992 - Magnetic memory device and method: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode...

20060139991 - Magnetic memory device, method for writing magnetic memory device and method for reading magnetic memory device: The magnetic memory device comprises: a memory cell including two magnetoresistive effect elements serially connected to each other, and a select transistor connected to a connection node between the two magnetic resistant devices, a bit line connected to the connection node of the magnetoresistive effect elements via the select transistor,...

20060139994 - Method of programming, reading and erasing memory-diode in a memory-diode array: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the...

20060139996 - Dynamic data restore in thyristor-based memory device: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to...

20060139995 - One time programmable memory: A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory....

20060139998 - Substrate electron injection techniques for programming non-volatile charge storage memory cells: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the...

20060139999 - Semiconductor device: A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If...

20060140002 - Flash memory device having multi-level cell and reading and programming method thereof: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and...

20060140001 - Nand flash memory device capable of changing a block size: Disclosed herein is a NAND flash memory device capable of changing a block size. In NAND flash memory devices capable of changing a block size, each memory block is divided into two page groups. Each memory block includes two block switches to select each page group in response to an...

20060140000 - Operation methods for a non-volatile memory cell in an array: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling...

20060140003 - Non volatile semiconductor memory device: In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the object of the present invention is to provide a technology of...

20060140004 - Semiconductor device: A semiconductor integrated circuit includes non-volatile memory elements (PM1, PM2), each of which has a first source electrode, a first drain electrode, a floating gate electrode and a control gate electrode and is capable of having different threshold voltages, and read transistor elements (DM1, DM2), each of which has a...

20060139997 - Flash memory device: A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection...

20060140005 - Method and apparatus for operating a non-volatile memory array: An array of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured...

20060140006 - Method and apparatus for operating a non-volatile memory device: A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current....

20060140007 - Non-volatile memory and method with shared processing for an aggregate of read/write circuits: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant...

20060140008 - Storage apparatus: In a data input/output with other apparatus, a data transfer controller (DTC) of a storage controller multiprocesses a data transfer with the other apparatus by utilizing a saving/recovering operation and suppresses a load therefrom, thereby improving performance thereof. A first storage apparatus includes two DMA units in a data transfer...

20060140010 - Method and system for reducing soft-writing in a multi-level flash memory: A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to...

20060140009 - Programming method for nanocrystal memory device: A programming method for non-volatile electrically erasable and programmable CMOS memory transistor lowers programming power requirements. First, a nanocrystal floating gate is provided in electrical communication to source and drain electrodes of the transistor. Secondly, bipolar programming pulses are applied to the substrate, with a control gate held at a...

20060140011 - Reducing floating gate to floating gate coupling effect: For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the...

20060140013 - Semiconductor memory device: A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit...

20060140012 - Word line compensation in non-volatile memory erase operations: Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one...

20060140015 - Programmable output driver turn-on time for an integrated circuit memory device: An integrated circuit memory device, system and method turns on an output driver in response to a stored value that represents an amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data in various embodiments. An...

20060140014 - Static random access memory device having a memory cell with multiple bit elements: A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e., including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can incorporate a single...

20060140016 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values...

20060140017 - Ferroelectric memory reference generator systems using staging capacitors: Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108)...

20060140018 - Semiconductor memory device: The present invention is related to an internal voltage generator for use in a semiconductor memory device preventing latch-up and chip damage. The internal voltage generator includes a first pumping block for comparing an internal upper voltage with a reference voltage to generate a first compensated upper voltage based on...

20060140019 - Semiconductor memory device: The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage generator for use in the semiconductor memory device includes a cell plate voltage generator, a driving voltage generator, and a bit line precharge voltage generator. The bit line...

20060140020 - Internal voltage generator for a semiconductor memory device: Provided is an internal voltage generator for a semiconductor memory includes: a first internal voltage drive device for driving an internal voltage in response to a first reference voltage corresponding to a target level of an internal voltage; and a second internal voltage drive device for driving the internal voltage...

20060140021 - Circuit for generating data strobe signal of semiconductor memory device: A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency...

20060140022 - Data output circuit, data output method, and semiconductor memory device: In a data output circuit, a data output method, and a semiconductor memory device, the data output circuit includes: an internal clock generation unit that delays an external clock signal by a first delay time to output an internal clock signal in response to the external clock signal and a...

20060140023 - Memory system and method for strobing data, command and address signals: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe...

20060140025 - Method for operating a semiconductor memory apparatus, and semiconductor memory system: The present invention relates to a method for operating a semiconductor memory apparatus, comprising: transmitting a command instruction, particularly a write instruction and/or a read instruction, to the semiconductor memory apparatus; transmitting a data signal to and/or from the semiconductor memory apparatus; and transmitting a data clock signal is transmitted...

20060140024 - Multi-phase clock signal generator and method having inherently unlimited frequency capability: A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The...

20060140026 - Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information: A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method...

20060140028 - Semiconductor device and manufacturing method thereof: A semiconductor device includes a semiconductor substrate including an active area (AA) surrounded by an isolation insulating film, and a nonvolatile memory cell on the AA, the nonvolatile memory cell including a tunnel insulating film on the AA, a FG electrode on the tunnel insulating film, a CG electrode above...

20060140029 - Semiconductor memory device: A redundancy replacement judging circuit includes a redundancy replacement judging circuit chain and a pseudo redundancy replacement judging circuit chain substantially equal in delay time to the redundancy replacement judging circuit chain. In response to an output of the pseudo redundancy replacement judging circuit chain, the redundancy replacement judging circuit...

20060140027 - Semiconductor memory device and method of operating the same: A semiconductor memory device has: a first memory including a data storage area and a redundant data storage area; a second memory as a nonvolatile memory storing a defect address of the first memory; a register; a sequencer; and a decoder. The sequencer reads out the defect address from the...

20060140030 - System for performing fast testing during flash reference cell setting: An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell...

20060140031 - Ferroelectric film and method of manufacturing the same: A method of manufacturing a ferroelectric film including: (a) mixing a polycarboxylate containing niobium, a polycarboxylate containing bismuth, a polycarboxylic acid or a polycarboxylic acid ester, and an organic solvent; and (b) applying the resulting mixed solution to a substrate and heat-treating the applied mixed solution to form a ferroelectric...

20060140033 - Data bus architecture for a semiconductor memory: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output...

20060140032 - Method for controlling precharge timing of memory device and apparatus thereof: A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making...

20060140034 - Transition-encoder sense amplifier: A sense amplifier includes a storage element and logic circuitry to transition encode an output signal....

20060140036 - Memory controller, display controller, and memory control method: A memory controller includes: a splitter which divides input pixel data, in which the number of bits of a first color component is I1 bits, the number of bits of a second color component is I2 bits, and the number of bits of a third color component is I3 bits,...

20060140035 - Memory device: Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator...

20060140037 - Temperature sensing device in an integrated circuit: A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature...

20060140038 - Semiconductor memory device with internal voltage generator: An internal voltage generator for use in a semiconductor memory device, includes: an internal voltage generation unit for generating an internal voltage by performing a charge pumping operation to a power supply voltage based on a result of comparing the internal voltage with a reference voltage; and an initial internal...

20060140039 - Voltage supply circuit, in particular for a dram memory circuit, as well as a method for controlling a supply source: A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage on a supply voltage line and a control circuit which is connected to the supply source for switching on and...

20060140042 - High speed wordline decoder for driving a long wordline: A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additionally, a voltage pump can supply operating voltage to the inverter to assist in overdriving the wordline. A voltage sink can also be...

20060140041 - Leakage current management: A thermal feedback loop controls leakage current during burn-in of a circuit....

20060140040 - Memory with selectable single cell or twin cell configuration: A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line...

20060140043 - Flash memory architecture for optimizing performance of memory having multi-level memory cells: A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable of being selectively programmed to have a threshold voltage corresponding to one of a plurality of multi-bit bit-sets. In one embodiment, the memory device...

20060140047 - Apparatus, system and method for generating self-generated strobe signal for peripheral device: A self-generated strobe signal generator generates a self-generated strobe signal for a peripheral device using a peripheral device selection signal and a clock signal, without using a conventional strobe signal for all of the peripheral devices. Using the self-generated strobe signal synchronized to the clock signal, a delay time of...

20060140044 - Clock signal generation apparatus for use in semiconductor memory device and its method: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and...

20060140045 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system...

20060140046 - Synchronous storage device and control method therefor: In a DDR operation mode, (L−1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N1BD)/S (N1D) in reverse phase to signal S (N1)/S (N1B) is provided and internal clock signal CKI becomes high...

20060133122 - Method and apparatus to read information from a content addressable memory (cam) cell: A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information...

20060133123 - Semiconductor memory device and method of making design change to semiconductor chip: The positions of the main driver 10, the output pad 20 and the first buffer 61 and the second buffer 62 are changed from the central region 111 to the peripheral region 120, and the first control signal line 31 and the second control signal line 32 are elongated. The...

20060133124 - Semiconductor package with a controlled impedance bus and method of forming same: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices...

20060133125 - Apparatus and method for memory operations using address-dependent conditions: An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition...

20060133126 - Semiconductor memory device capable of switching from multiplex method to non-multiplex method: There is provided a semiconductor memory device which adopts a multiplex method in which an address signal and a data signal are input into the same terminal, and which is capable of switching from the multiplex method to a non-multiplex method in which an address signal and a data signal...

20060133127 - Nonvolatile semiconductor memory device to which information can be written only once: A nonvolatile semiconductor memory device having a storage element which is programmed with information by breaking an insulating film of the storage element, includes a cell array including a plurality of storage cells arranged in matrix, each of the storage cells having the storage element and a selection switch connected...

20060133128 - Method and storage device for the permanent storage of data: It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer,...

20060133129 - Methods for enhancing performance of ferroelectric memory with polarization treatment: The present invention facilitates data retention lifetimes for ferroelectric devices by improving switched polarization of ferroelectric memory cells. A ferroelectric memory device comprising ferroelectric memory cells is provided (702). A duration for applying a DC bias to the ferroelectric memory cells is selected (704) according to at least a desired...

20060133131 - Low voltage semiconductor memory device: A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a...

20060133132 - Low voltage semiconductor memory device: A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; a reference cell block including a plurality...

20060133130 - Memory circuit receivers activated by enable circuit: A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level...

20060133133 - Semiconductor device: A semiconductor device capable of improving the accuracy for determining whether a prescribed input potential is higher or lower than a reference potential is obtained. This semiconductor device comprises first capacitance means and second capacitance means having different ON- and OFF-state capacitances. The semiconductor device changes the potential of a...

20060133135 - Reducing power in srams while maintaining cell stability: An SRAM with reduced power consumption comprising N SRAM cells and peripheral circuitry that enables writing and reading any of the N SRAM cells. The number of cells, N, is a whole number. The voltage applied to the N SRAM cells is higher than the voltage applied to the peripheral...

20060133134 - Single-event upset tolerant static random access memory cell: A single-event upset tolerant random access memory cell is disclosed. The single-event upset tolerant memory cell includes a first and second sets of access transistors along with a first and second sets of dual-path inverters. The first set of access transistors is coupled to a first bitline, and the second...

20060133136 - Data write method of magnetic random access memory: A data write method of a magnetic random access memory including a magnetoresistive element which has axis of easy and hard magnetizations, a first write wiring which runs in a direction of the axis of easy magnetization, and a second write wiring which runs in a direction of the axis...

20060133137 - Voltage-controlled magnetization reversal writing type magnetic random access memory device and method of writing and reading information using the same: A voltage-controlled magnetization reversal writing type Magnetic Random Access Memory (MRAM) device. The MRAM device includes electrically conductive base electrodes, a piezoelectric layer, an insulation layer, a free ferromagnetic layer, a nonmagnetic layer, a pinned ferromagnetic layer, an antiferromagnetic layer and two electrically conductive reading lines. The electrically conductive base...

20060133138 - Systems for variable programming of non-volatile memory: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are...

20060133139 - Non-volatile semiconductor memory: A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells via the bit lines; a shield...

20060133140 - Rfid tags storing component configuration data in non-volatile memory and methods: An RFID tag has a Non Volatile Memory (NVM) array that can store data in a way that survives loss of power. The data is configuration data that controls the operation of an operational component of the tag. A performance of the operational component is thus adjusted according to the...

20060133141 - Erased sector detection mechanisms: The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted...

20060133143 - Nonvolatile semiconductor memory device and a method of word lines thereof: A nonvolatile semiconductor memory device comprising a memory cell array having a plurality of blocks each including a plurality of electrically reprogrammable nonvolatile memory cells arranged in matrix, a first circuit for selecting one from the plurality of blocks, the first circuit having a plurality of transistors connected to word...

20060133142 - Semiconductor memory device and memory card: A semiconductor memory device disclosed herein comprises: a memory cell array including memory blocks, each memory block including memory cells arranged in a matrix and the memory cell array including first select gate transistors to select one or more memory cells; a select gate line configured to input a control...

20060133145 - Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats: A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat....

20060133144 - Page buffer for nonvolatile semiconductor memory device and method of operation: Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to...

20060133146 - Semiconductor device and a method of manufacturing the same: A semiconductor device having a well region of a first conduction type formed in a main surface of a semiconductor substrate, and a nonvolatile memory element formed at the well region is provided. The nonvolatile memory element comprises a gate electrode formed over the well region through an insulating film...

20060133148 - Method for configuring a voltage regulator: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell...

20060133152 - Method for programming and erasing an nrom cell: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled...

20060133149 - Methods and circuits for generating a high voltage and related semiconductor memory devices: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage...

20060133147 - Nonvolatile semiconductor memory device and voltage generating circuit for the same: A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a...

20060133150 - Semiconductor memory device capable of setting a negative threshold voltage: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one...

20060133151 - Single poly eprom device: The present invention relates to a single poly EPROM device. The single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a channel between the source (16) and the drain (18). The floating...

20060133153 - Memory device: A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the...

20060133154 - Data write apparatus for nonvolatile memory: A data write apparatus for nonvolatile memory includes a control device for transmitting or receiving data, and a nonvolatile memory connected to the control device through a communication line, for storing the data supplied from the control device. The nonvolatile memory permits write of data if the number of pulses...

20060133155 - Nonvolatile semiconductor memory device and a method of erasing data thereof: A nonvolatile semiconductor memory device comprises memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, before erasing data of all of said memory cells in the selected memory block in a plurality of said memory blocks, preprogram is performed to shift all...

20060133156 - Systems for comprehensive erase verification in non-volatile memory: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements...

20060133157 - Method of handling limitations on the order of writing to a non-volatile memory: Sectors of data are stored in a non-volatile memory by writing all the sectors in a first order and subsequently writing all the sectors in a different, second order that is determined prior to the second writing. Sectors are stored in a non-volatile memory by writing the sectors using a...

20060133160 - Bufferless writing of data to memory: This invention provides a processor 900 for writing data contained in payload data 1006 of a data packet 1000 to memory, especially for use as the central processing unit of a memory tag 1200. The processor 900 does not include a write buffer. The processor 900 comprises a first register...

20060133159 - Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose: Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of first and second signal levels...

20060133158 - Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure: Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for simultaneously latching K-bit input data (K is an integer), which is received by simultaneously pre-fetching from an internal...

20060133161 - Memory with storage cells biased in groups: A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their own biasing circuit...

20060133163 - Circuit arrangement and method for switching high-voltage signals by means of low-voltage signals: The invention relates to a circuit arrangement for switching high-voltage signals with low-voltage signals, particularly for driving a semiconductor memory arrangement, comprising a low-voltage logic device for generating a low-voltage signal with a first predetermined logic level and with a second predetermined logic level, comprising a latch for receiving and...

20060133162 - Self-latched control circuit for memory program operation: A memory programming control circuit is disclosed. The memory programming control circuit is connected to a memory cell via a data line for controlling a programming current in a programming operation of the memory cell. The memory programming control circuit includes a programming enable device connected to a positive power...

20060133164 - Semiconductor memory with wordline timing: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit...

20060133165 - Memory system and method for strobing data, command and address signals: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe...

20060133167 - Nonvolatile semiconductor memory device using irreversible storage elements: A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties...

20060133166 - Semiconductor memory: Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data...

20060133168 - Semiconductor memory device for reducing chip area: Disclosed is a semiconductor memory device capable of reducing chip area by precharging all banks simultaneously. The semiconductor memory device includes: a command decoder for generating an auto refresh signal in response to an external command; an active information signal generator for generating an active information signal in response to...

20060133169 - Address comparator of semiconductor memory device: Disclosed is an address comparator configured to flow a current only for an initial short time, but not at other times, such as when an address is input thereto for a repair operation. The address comparator includes a plurality of unit address comparators comparing addresses received for the repair operation,...

20060133170 - Memory circuit: The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch between internal signal lines of each of the ports; and a control device for controlling capacity of the crosstalk-glitch suppressor circuit....

20060133171 - Readout circuit and nonvolatile semiconductor memory device: A readout circuit has: a sense amplifier circuit configured to sense a data stored in a memory cell transistor based on a current flowing through the memory cell transistor and a reference current flowing through a dummy cell transistor; and a voltage control circuit configured to apply a first voltage...

20060133172 - Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory: The invention proposes an apparatus for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the apparatus has a device which is used to influence a threshold voltage for the selection transistor contrary to the influence of an...

20060133173 - Method, apparatus, and system for active refresh management: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount...

20060133174 - Phase-change ram containing ain thermal dissipation layer and tin electrode: Provided is a phase-change RAM containing a substrate, a lower electrode, a phase-change material, an upper electrode and a thermal dissipation layer, wherein the thermal dissipation layer contains an aluminum-nitride thermal dissipation layer having a high heat conductivity, and the lower electrode contains a titanium-nitride electrode which generates a great...

20060133175 - Rfid tags with electronic fuses for storing component configuration data: An RFID tag has a fuse that is adapted to store configuration data in a way that survives loss of power. The fuse can be one time programmable or many times programmable, and be implemented with a non-volatile memory. The configuration data becomes available to an operational component of the...

20060133176 - Charge pump with ensured pumping capability: An n-stage charge pump contains n primary capacitive elements (CC1-CCn or CD1-CDn), n+1 charge-transfer cells (601-60n+1, 1101-110n+1, 1201-120n+1, or 1301-130n+1) respectively sequentially designated as the first through (n+1)th cells, and sources of first and second clock signals (VCKP and {overscore (V)}CK P or VCKP1 and VCKP2) approximately inverse to each...

20060133179 - Dram power bus control: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited...

20060133177 - Mos semiconductor integrated circuit device: A first P-channel transistor is connected between a gate of an N-channel transistor constituting a last-stage buffer circuit and an output of a prebuffer circuit. A second P-channel transistor is connected between the power supply node and a gate of a P-channel transistor constituting a last-stage buffer circuit. A first...

20060133180 - Semiconductor memory device and semiconductor integrated circuit device: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections...

20060133178 - System and method for destructive purge of memory device: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by...

20060133181 - Power controller, apparatus provided with backup power supply, program for controlling power, and method for controlling power: The present invention constructs a flexible power supply backup system corresponding to electronic devices (apparatuses) at low cost, and realizes reliable operation of the apparatuses. There is provided a power controller 1 that controls power of an apparatus 100 provided with a backup power supply for power supply, which includes...

20060133182 - Semiconductor memory device for reducing peak current during refresh operation: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a...

20060133183 - Multi read port bit line: In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one...

20060133186 - Memory access using multiple activated memory cell rows: For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory...

20060133185 - Memory array leakage reduction circuit and method: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits....

20060133184 - Plasma damage protection circuit: A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based...

20060133187 - Memory having internal column counter for compression test mode: A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating a compression register of expected...

20060133188 - Method of controlling mode register set operation in memory device and circuit thereof: Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addresses are used to intercept...

20060133189 - N-well and n+ buried layer isolation by auto doping to reduce chip size: A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried...

20060126369 - Stacked dram memory chip for a dual inline memory module (dimm): The invention refers to a DRAM Memory Chip for a Dual In Line Memory Module (DIMM) having (a) a predetermined number (M) of stacked DRAM memory dies; (b) wherein each DRAM memory die is selectable by a corresponding memory rank signal (r); (c) wherein each DRAM memory die comprises an...

20060126370 - Memory architecture and method of manufacture and operation thereof: An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a...

20060126372 - Circuits for driving fram: A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM...

20060126371 - Magnetoresistive effect device, magnetic random access memory, and magnetoresistive effect device manufacturing method: A magnetoresistive effect device includes a first ferromagnetic layer having a fixed magnetization direction and having magnetic moment ml per unit area. A nonmagnetic layer contacts with the first ferromagnetic layer and has an amplitude hi of roughness of an interface between the nonmagnetic layer and the first ferromagnetic layer....

20060126373 - Three-state memory cell: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference;...

20060126374 - Sense amplifier circuitry and architecture to write data into and/or read from memory cells: A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is...

20060126376 - Deglitching circuits for a radiation-hardened static random access memory based programmable architecture: The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has...

20060126375 - Integrated circuit with a memory of reduced consumption: An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power...

20060126377 - Semiconductor memory device: The present invention relates to a semiconductor memory device in which information is written into a storage element by flowing current. The invention aims at shortening write speed and reducing power consumption by preventing parasitic capacitors from prolonging the time required for a write current to reach a predetermined value....

20060126378 - Serial transistor-cell array architecture: A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory...

20060126379 - Thin film magnetic memory device writing data with bidirectional: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets...

20060126381 - Method of writing to a phase change memory device: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to...

20060126380 - Semiconductor device: The present invention provides a technology which can suppress a variation in a value after a write operation to minimum so as to facilitate multi-bit operation in a semiconductor device such as a phase change memory. A semiconductor device includes: a memory cell having a storage element (phase change material)...

20060126385 - Flash memory device with burst read mode of operation: A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the...

20060126384 - Flash memory integrated circuit with multi-selected modes: The present invention provides a flash memory integrated circuit with multi-selected modes. The flash memory integrated circuit comprises a base, a plurality of flash memory dies, and a transformation device. The plurality of flash memory dies and the transformation device are disposed on the base. And the multi-selected modes can...

20060126387 - Multi-level cell memory device and associated read method: A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference...

20060126386 - Nonvolatile semiconductor memory device and write/verify method thereof: A nonvolatile semiconductor memory device includes write/verify circuits, a switching elements which divides the bit lines into plural portions, and a control circuit. The control circuit is configured to control the write/verify circuits and switching elements. The control circuit performs a control operation to perform the write and verify operations...

20060126382 - Method for reading non-volatile memory cells: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history...

20060126383 - Method for reading non-volatile memory cells: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with...

20060126388 - Device and procedure for measuring memory cell currents: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during...

20060126389 - Integrator-based current sensing circuit for reading memory cells: Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a corresponding sense voltage. The...

20060126393 - Data recovery methods in multi-state memory after program fail: A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed...

20060126392 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection...

20060126391 - Methods of program verifying non-volatile memory devices: Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More particularly, the multi-bit memory cell transistor may be programmed from a first program state to a second program state, and a reference...

20060126394 - Multi-state memory having data recovery after program fail: A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed...

20060126390 - Pipelined programming of non-volatile memories using early data: The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can...

20060126396 - Method, system, and circuit for operating a non-volatile memory array: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating...

20060126395 - Non-volatile memory cell and operating method thereof: A non-volatile memory cell is provided. The non-volatile memory cell includes of a threshold switch material thin film and a memory switch material thin film, and the phases of the memory switch material layer is capable of changing. In addition, the memory switch material layer serves as a memory unit;...

20060126398 - Nrom memory cell, memory array, related devices and methods: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store...

20060126397 - Semiconductor memory device: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data...

20060126399 - Flash memory device capable of reduced programming time: A flash memory device and related method of operation are provided. The device generally comprises a word line voltage generator circuit configured to generate a word line voltage based on incremental step pulse programming; and a word line voltage controller circuit that controls the word line voltage generator circuit so...

20060126400 - Semiconductor integrated circuit: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small...

20060126404 - Low power multi-chip semiconductor memory device and chip enable method thereof: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals....

20060126402 - Mainboard, electronic component, and controlling method of logic operation: A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control...

20060126401 - Reducing dq pin capacitance in a memory device: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance is disclosed. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT...

20060126403 - Semiconductor driver circuit with signal swing balance and enhanced testing: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling...

20060126405 - Apparatus with equalizing voltage generation circuit and methods of use: A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced...

20060126406 - Memory system and method for strobing data, command and address signals: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe...

20060126408 - Memory buffer: The invention relates to a memory buffer, a method for operating the memory buffer, a memory module with a memory buffer, a testing method for the memory module, and an operating method for the memory module. The memory buffer comprises at least one memory logic unit that is connected with...

20060126407 - Methods for repairing and for operating a memory component: In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner that a write or read access...

20060126411 - Pipelined burst memory access: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation....

20060126409 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values...

20060126410 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values...

20060126412 - Integrated circuit device having a test circuit to measure ac characteristics of internal memory macro: An integrated circuit device of the invention, has a memory macro which during normal operation latches an input address in response to a control pulse and generates data output corresponding to the input address, and a test control circuit 22 which during testing performs memory macro characteristic tests. A ring...

20060126413 - Memory circuit and method for reading out a memory datum from such a memory circuit: The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an item...

20060126414 - Method for activating a plurality of word lines in a refresh cycle, and electronic memory device: An electronic memory device for storing data comprises a memory cell array arranged in at least one memory bank and comprising memory cells in which information is stored. The electronic memory device further comprises word lines and bit lines for addressing and reading the memory cells of the memory cell...

20060126416 - Memory cell array structure adapted to maintain substantially uniform voltage distribution across plate electrode: Disclosed is a wiring structure for supplying a plate electrode voltage to a memory device comprising a plurality of memory cells. The wiring structure includes a first plurality of metal wires arranged in a first direction along peripheral and center portions of a plate electrode and a second plurality of...

20060126415 - Programmable system device having a shared power supply voltage generator for flash and pld modules: A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network...

20060126419 - Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block: A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second...

20060126417 - Semiconductor memory device: A cell array in the semiconductor memory device is divided into two blocks. Each of control signal lines for transmission of control signals are also divided into a first portion and a second portion correspondingly to the blocks. A repeater circuit that relays a control signal is provided between the...

20060126418 - Semiconductor memory device with hierarchical i/o line architecture: A semiconductor memory device is composed of a plurality of banks each including a plurality of sub-arrays arranged in rows and columns; global I/O lines shared by the plurality of banks; local I/O lines disposed for every a number of sub-arrays within each of the plurality of banks; I/O switch...

20060126420 - Semiconductor memory: In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input into a write control circuit,...

20060126421 - Apparatus and methods for generating a column select line signal in semiconductor memory device: An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signal has a first pulse width when the...

20060126422 - Memory device and electronic device using the same: A semiconductor memory card 10 that can be attached to and detached from an electronic device is provided with first memory 50 of non-tamper-resistance having usual areas 52 and 53 that can be accessed from the electronic device and a secure area 51 that cannot directly be accessed from the...

20060126423 - Memory element and memory device: A memory element 10 includes a memory layer 4 and an ion source layer 3 positioned between the first electrode 2 and second electrode 6, in which the ion source layer 3 contains any of elements selected from Cu, Ag and Zn, and any of elements selected from Te, S...

20060126424 - Phase-change memory device using chalcogenide compound as the material of memory cells: A phase-change memory device includes memory cells, a memory cell array, a first electrode layer, a word line, and a bit line. The memory cell includes a phase-change layer formed on a semiconductor substrate. The memory cell array has the memory cells arranged in a matrix. The phase change layer...

20060126425 - Delay-locked loop having a pre-shift phase detector: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is...

20060114706 - Content addressable memory with reduced search current and power: The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at...

20060114705 - Static content addressable memory cell: A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a...

20060114707 - Semiconductor memory device: A semiconductor memory device includes a first write wiring which has first to third running portions, first and second oblique running portions, the first and second running portions running in a first direction, the third running portion running on substantially a same line as the first running portion, the first...

20060114708 - Semiconductor memory device: Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written...

20060114710 - Ferroelectric-type nonvolatile semiconductor memory: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging...

20060114709 - Semiconductor storage device, operation method of the same and test method of the same: A semiconductor storage device comprises a bit line; a word line; a plate line; a ferroelectric capacitor having a ferroelectric substance between electrodes, one of the electrodes being connected to the plate line, the ferroelectric capacitor being capable of storing data; a selection transistor connected between the other of the...

20060114711 - Memory circuit: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line....

20060114716 - Magnetoresistance element, magnetic memory, and magnetic head: There is provided a magnetoresistance element including a free layer that includes a first ferromagnetic layer and a second ferromagnetic layer whose magnetization directions are equal to each other and a nonmagnetic film intervening between the first and second ferromagnetic layers, a pinned layer including a third ferromagnetic layer that...

20060114714 - Magnetroresistive random access memory and method of manufacturing the same: A magnetic memory includes a TMR element in its memory layer, wherein the TMR element in the memory layer has ferromagnetic layers which are kept in tensile strain, the ferromagnetic layers having either Fe, Co or Ni, and a wiring layer adjacent to each of the ferromagnetic layers includes either...

20060114715 - Memory: Each memory cell is composed of a storage layer (2) for storing therein information based on the magnetization state of a magnetic material, a magnetization fixed layer (4) provided on the storage layer (2) through an intermediate layer (3), a storage element (10) for applying an electric current in the...

20060114713 - Mram with coil for creating offset field: An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a...

20060114712 - Mram with switchable ferromagnetic offset layer: A magnetoresistive memory cell includes a magnetic tunnel junction including first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers being antiferromagnetically coupled. The magnetoresistive memory cell further includes a switchable ferromagnetic offset field layer being provided with a free magnetic moment...

20060114717 - Low power programming technique for a floating body memory transistor, memory cell, and memory array: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a...

20060114718 - Nonvolatile semiconductor memory device which stores multi-value information: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit)...

20060114719 - Novel combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications: A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile...

20060114720 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality...

20060114721 - Method and system for regulating a program voltage value during multilevel memory device programming: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage...

20060114722 - Nonvolatile memory device, and its manufacturing method: On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across...

20060114723 - Page buffer and verify method of flash memory device using the same: Disclosed herein are a page buffer and a verify method of a flash memory device where the page buffer of a dual register structure includes a switch, which is driven according to a voltage level of an input terminal of a main latch, to output an erase-verify signal, and a...

20060114724 - Non-volatile semiconductor memory: A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector comprises a plurality of...

20060114725 - Non-volatile memory device and associated method of erasure: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation...

20060114726 - Nonvolatile memory: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address...

20060114727 - Audio visual architecture: Aspects of an audio/visual architecture are disclosed. In one aspect, a system is disclosed where the system has a media manager object, an audio/visual program, and a player/recorder object so that when the program is selected, the media manager dynamically loads the player/recorder object for either playing or recording the...

20060114728 - Data storage device having multiple buffers: A data storage device having multiple buffers is proposed. When storing data, a controller makes use of a host's bus to select and transmit multiple block data to multiple buffers for temporary storage and then records relevant details. Next, the controller transmits the data from the buffers to a storage...

20060114729 - Non-volatile semiconductor memory device and memory system using the same: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged...

20060114730 - Nonvolatile memory devices and programming methods using subsets of columns: Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that...

20060114731 - Method and apparatus for controlling a high voltage generator in a wafer burn-in test: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor...

20060114732 - Semiconductor device: A semiconductor device capable of exchanging fuse data between registers is provided. Fuse circuits 20 to 24 are respectively connected to register circuits 10 to 14, and output fuse data that is stored in the built-in fuses to the respective register circuits 10 to 14. Register circuits 15 to 19...

20060114733 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein the sense amplifier circuit includes: a first transistor disposed between a bit line of the memory cell array and...

20060114736 - Nonvolatile semiconductor memory cell and method of manufacturing the same: A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second...

20060114735 - Semiconductor memory device and refresh control method: Disclosed is a semiconductor-memory device comprising a selector for performing switching control such that in the standby state the refresh operation is performed responsive to an external-refresh-execution command supplied from outside the semiconductor-memory device, while in the active state, the refresh operation is performed, not under the control from outside...

20060114734 - Temperature based dram refresh: A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of...

20060114737 - Data processing device: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines...

20060114738 - Non-volatile semiconductor memory device: A load of a main cell for applying a power to a sensing node of the main cell is equivalent to a load of a reference cell for applying a power to a sensing node of a reference cell. A high voltage higher than a power supply voltage is applied...

20060114740 - Ferroelectric memory and method of driving the same: A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver circuits; each of the memory cells including a ferroelectric capacitor. A wordline driver circuit circuits includes: a driver DRV...

20060114739 - Method and circuit for controlling generation of a boosted voltage in devices receiving dual supply voltages: A row driver circuit receives a first supply voltage and a second supply voltage. The circuit provides the first supply voltage on an output responsive to the first supply voltage being greater than a threshold value. The circuit generates a boosted voltage that is greater than the first supply voltage...

20060114741 - Program invocation methods and devices utilizing the same: An electronic device comprises a first operating system, another second operating system, a first application, an emulator, a switch, and a processor. The first application is executable on the second operating system. The emulator imitates the runtime environment of the second operating system while the first operating system is running....

20060114742 - Method and apparatus for optimizing strobe to clock relationship: To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or...