Static information storage and retrieval inventions 05/06

20060109703 - Ferroelectric-type nonvolatile semiconductor memory: A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging...

20060109704 - Nonvolatile memory device using resistor having multiple resistance states and method of operating the same: A nonvolatile memory device and method that uses a resistor having various resistance states. The memory device may include a switching device and a resistor. The resistor may be electrically connected with the switching device and may have one reset resistance state and at least two or more set resistance...

20060109705 - Integrated semiconductor memory device: An integrated semiconductor memory device includes external terminals to which an input signal can be applied to each external terminal, and a register circuit with registers. Each register stores a respective input signal. A programming circuit is also provided with programmable switching units configured such that, in a manner dependent...

20060109706 - Sram with dynamically asymmetric cell: A CMOS static random access memory (SRAM) array with dynamically asymmetric cells, an integrated circuit (IC) chip including the SRAM and a method of accessing data in the SRAM. Each column of cells is connected to a pair of column supply lines supplying power to the column. During each SRAM...

20060109707 - Energy adjusted write pulses in phase-change memories: A memory cell device that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least two states. The write pulse generator generates a write pulse for the plurality...

20060109708 - Method for improving the thermal characteristics of semiconductor memory cells: A non-volatile, resistively switching memory cell is disclosed. In one embodiment, the memory cell has a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal...

20060109709 - Semiconductor device and methods of manufacturing the same: A semiconductor device includes at least two transistors and a charge-trapping structure. The charge-trapping structure traps charges, which are moved from a selected transistor toward a non-selected transistor, adjacent to the selected transistor among the transistors, thereby preventing a threshold voltage of the non-selected transistor from being increased. Thus, the...

20060109712 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks...

20060109711 - Semiconductor device and method for controlling the same: A semiconductor memory device has a read ground and a write ground, these grounds being separately provided. Even when the read and verify operations are simultaneously executed, the source potential of an involved memory cell obtained at this time is equal to that obtained when either one of the read...

20060109714 - Circuit for indicating termination of scan of bits to be programmed in nonvolatile semiconductor memory device: A circuit for indicating termination of scan of bits to be programmed in a nonvolatile semiconductor memory device includes a counting unit, a set bit number provision unit and a comparison unit. The counting unit counts the predetermined number of bits to be programmed, and provides a group of counting...

20060109713 - Memory device: A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one...

20060109715 - Nand flash memory device capable of improving read speed: A NAND flash memory device according to the present invention is provided which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first...

20060109716 - Nonvolatile memory devices and methods of controlling the wordline voltage of the same: A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages...

20060109710 - Memory device having a virtual ground array and methods using program algorithm to improve read margin loss: A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current...

20060109717 - Method and apparatus for programming nonvolatile memory: Programming nonvolatile memory cells is affected by the program disturb effect which causes data accuracy issues with nonvolatile memory. Rather than masking the voltage conditions that cause the program disturb effect, voltages are applied to neighboring nonvolatile memory cells, which takes advantage of the program disturb effect to program multiple...

20060109718 - System and method for preventing read margin degradation for a memory array: An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right bit....

20060109719 - Charge pump for use in a semiconductor memory: In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up generation during a charge non-transfer period. A charge transmission transistor transmits the voltage of a boosting node to a...

20060109720 - Writing driver circuit of phase-change memory: A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the...

20060109721 - Random access memory having fast column access: A memory comprises a column decoder and a circuit. The circuit is configured to receive a column address strobe signal, a column active signal, and a column addresses signal. The circuit is configured to pass the column addresses signal to the column decoder if the column address strobe signal and...

20060109722 - Active termination circuit and method for controlling the impedance of external integrated circuit terminals: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled...

20060109723 - Active termination circuit and method for controlling the impedance of external integrated circuit terminals: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled...

20060109725 - Apparatus and method for managing bad blocks in a flash memory: A method and an apparatus for managing bad blocks generated while a flash memory is being used. A method for managing a bad block in a flash memory includes (a) allocating a used area having a plurality of used blocks and a spare area having a plurality of spare blocks...

20060109724 - Memory device capable of changing data output mode: Disclosed herein is a memory device capable of changing data output modes. According to the present invention, an address that is input to a circuit, which is designed in 8-bit output mode, is internally modified, to operate in 16-bit output mode, and a test operation is performed in 8-bit output...

20060109726 - Method, apparatus, and computer program product for implementing enhanced dram interface checking: A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are...

20060109727 - Integrated semiconductor memory device: An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to...

20060109728 - Common-mode data transmission for power over ethernet system: Circuitry and methodology for providing data transmission in a Power over Ethernet (PoE) system having a Power Sourcing Equipment (PSE) for providing power to a PoE link, and a Powered Device (PD) coupled to the PoE link for receiving the power from the PSE. The PSE and PD support data...

20060109729 - Semiconductor storage device and mobile electronic device: When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to...

20060109730 - Storage device: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command...

20060109732 - Semiconductor memory device capable of operating at high speed: A plurality of sub-arrays include a plurality of memory elements. First bit line pairs are connected to a plurality of memory elements provided in each of the sub-arrays. Second bit line pairs are provided so as to correspond to a plurality of sub-arrays. The first bit line pairs supply signals...

20060109731 - Twin-cell bit line sensing configuration: Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word lines in an array, may be used to selectively couple bit...

20060109733 - High performance register file with bootstrapped storage supply and method of reading data thereform: A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses....

20060109734 - Service providing system, information processing device, method, and program: The present invention relates to a service providing system, an information processing apparatus, an information processing method, and a program. An information processing apparatus (base unit) 2 receives user information detected by sensors provided in an information processing apparatus (remote unit) 3 from the information processing apparatus (remote unit) 3,...

20060109735 - Flexible internal address counting method and apparatus: A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array, comprising, rendering a normal overflow condition of the counter modified, thereby enabling alteration of the count provided by...

20060104100 - Mismatch-dependent power allocation technique for match-line sensing in content-addressable memories: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low...

20060104102 - Layout structures in semiconductor memory devices including bit line layout for higher density migration: A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising...

20060104101 - Memory and related manufacturing method thereof: A memory manufactured through a semiconductor process includes a substrate, a memory cell array formed on the substrate, a peripheral circuit formed on the substrate and electrically connected to the memory cell array for controlling access of the memory cell array, and a power distribution network formed substantially above the...

20060104103 - Method for optical authentication and identification of objects and device therefor: The method in accordance with the invention consists in illuminating with coherent light a volume-wise at least partially scattering surface of reference objects under specified illumination conditions, in recording the speckle patterns thus obtained for various nominal values of illumination parameters and in a range of values around these nominal...

20060104104 - Methods for accelerated erase operations in non-volatile memory devices and related devices: Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to...

20060104105 - Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods: A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side...

20060104106 - Memory element and memory device: A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a...

20060104108 - Semiconductor integrated circuit device and method of manufacturing the same: A semiconductor integrated circuit device comprises a first transistor formed on a bulk substrate region in a semiconductor substrate and having a source or drain layer connected to a first reference voltage; and a second transistor including an impurity layer region formed on the bulk substrate region and being of...

20060104107 - Word line driver circuit for a static random access memory and method therefor: A static random access memory (14) has a normal mode of operation and a low voltage mode of operation. A memory array (15) includes memory cells (16) coupled to a first power supply node (VDD) for receiving a power supply voltage. A plurality of word line drivers is coupled to...

20060104109 - Thin film magnetic memory device with memory cells including a tunnel magnetic resistive element: A data bus is precharged to a precharge voltage before data read operation. In the data read operation, the data bus thus precharged is electrically coupled to the same voltage as the precharge voltage through a selected memory cell. A driving transistor couples the data bus to a power supply...

20060104110 - Spin-current switchable magnetic memory element and method of fabricating the memory element: A spin-current switchable magnetic memory element (and method of fabricating the memory element) includes a plurality of magnetic layers having a perpendicular magnetic anisotropy component, at least one of the plurality of magnetic layers including an alloy of a rare-earth metal and a transition metal, and at least one barrier...

20060104111 - Diode array architecture for addressing nanoscale resistive memory arrays: The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and...

20060104112 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second...

20060104114 - Non-volatile semiconductor memory device and electric device with the same: A non-volatile semiconductor memory device includes: a memory cell array in which a plurality of electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to write M-value data (where, M is an integer equal to 4 or more) to pair-cells each constituted by simultaneously selected first...

20060104116 - Method of operating a flash memory device: A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a...

20060104115 - Robust and high-speed memory access with adaptive interface timing: Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access....

20060104117 - Electrically rewritable nonvolatile semiconductor memory device: A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and...

20060104113 - Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each...

20060104118 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, a plurality of first assist gates extending toward the memory cell, a connection portion connecting end portions of the first assist gates, a...

20060104119 - Local input/output line precharge circuit of semiconductor memory device: A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when...

20060104120 - High speed programming system with reduced over programming: A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or...

20060104121 - Integrated circuit having a non-volatile memory with discharge rate control and method therefor: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well...

20060104122 - Integrated circuit having a non-volatile memory with discharge rate control and method therefor: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well...

20060104123 - Data latch: A high-speed latch includes a latch unit and a first current source. The latch unit has a first input terminal for receiving a first input signal and a first output terminal for outputting a first output signal. The first current source is coupled to the first output terminal, and is...

20060104126 - Device for controlling data output for high-speed memory device and method thereof: Disclosed are a DDR group (DDR I, DDR II, DDR III, . . . ) data output control device for controlling a time point of data output by using a DLL circuit and a method thereof. The data output control device includes a latch part for storing data read out...

20060104124 - Dual-edge triggered multiplexer flip-flop and method: A dual edge multiplexing flip-flop comprises a first circuit block having a first data input, a first clock signal input, a supply voltage input, and a ground connection; a second circuit block having a second data input, a second clock signal input, a supply voltage input, and a ground connection....

20060104127 - Memory device capable of detecting its failure: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for...

20060104125 - Method of reading a flash memory device: A method of reading a flash memory device wherein the status of a predetermined cell is read in such a way that a plurality of page buffers connected to a memory cell array through a plurality of bit lines are divided into at least two group, and the page buffers...

20060104128 - Method and apparatus to clamp sram supply voltage: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to...

20060104129 - Method for memory access and corresponding device: A ROM or flash memory with low power consumption includes control data used to retain information on the number of data bits that do not change relatively to an initial state. The proposed method allows the end of a reading operation to be determined with certainty, even under the effect...

20060104130 - Circuit and method for generating wordline voltage in nonvolatile semiconductor memory device: A circuit and method for generating a wordline voltage in a nonvolatile semiconductor memory device. The circuit comprises a switching unit to provide an external program voltage as the wordline voltage, together with a wordline voltage pump to generate the wordline voltage by pumping a power source voltage. After the...

20060104131 - Semiconductor memory device: A semiconductor memory device has: a word driver configured to apply a driving voltage to a word line connected to a memory cell; and an internal power supply circuit configured to supply the driving voltage to the word driver and to apply a substrate voltage to back gates of transistors...

20060104132 - Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system: A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst...

20060104135 - Data receiving apparatus and control method thereof: A data receiving apparatus and control method are provided. The apparatus includes a determining part determining whether a clock signal and a data signal are respectively in a high state and/or in a low state based on a predetermined value of a standard level, when the clock signal and the...

20060104133 - Reliability test method for a ferroelectric memory device: A reliability test method for a ferroelectric memory device having a ferroelectric capacitor evaluates, under acceleration conditions (acceleration temperature T2 and test time t2), whether or not life of retention characteristics of the ferroelectric memory device is guaranteed under actual use conditions (guarantee temperature T1 and guarantee time t1). The...

20060104134 - Semiconductor memory devices incorporating voltage level shifters for controlling a vpp voltage level independently and methods of operating the same: A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage...

20060104136 - Sense amplifier bitline boost circuit: A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and...

20060104137 - Deferring refreshes during calibrations in xdrtm memory systems: A method, an apparatus, and a computer program are provided to control refreshes in Extreme Data Rate (XDR™) memory systems. XDR™ memory systems employ calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions...

20060104138 - Internal voltage generator for semiconductor device: Disclosed is an internal voltage generator, which includes a detecting means for detecting a level of an internal voltage, an oscillator for generating a driving pulse signal in response to an output signal of the detecting means, a first driving unit for outputting a first pulse signal after receiving the...

20060104141 - Memory logic for controlling refresh operations: In a self-refresh mode, alternative refresh commands such as auto-refresh and row active commands are applied to a volatile memory device in response to stored refresh and address information to implement different refresh times for memory cells having different refresh characteristics....

20060104139 - Method of refreshing a memory device utilizing pasr and piled refresh schemes: In a memory device having an N number of banks, a refresh operation according to a piled refresh scheme is performed during a self-refresh mode to refresh the N number of banks in regular sequence when it is necessary to refresh all of the N number of banks. A refresh...

20060104140 - Semiconductor memory device and refresh method thereof: In a refresh method of a semiconductor memory device, two output pulses having different division ratios are generated by dividing a clock pulse. One of them having a shorter cycle is used to execute a short cycle refresh operation after a self-refresh operation starts. After a predetermined period of time...

20060104142 - Software refreshed memory device and method: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory...

20060104143 - Internal voltage supplier for memory device: Disclosed is an internal voltage supplier for the memory device, the internal voltage supplier comprising: a first switching means for selecting one of a first voltage generated from an interior of the memory device and a second voltage applied from an exterior of the memory device; and a divider for...

20060104144 - Semiconductor memory device: A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode register setting unit...

20060104145 - Memory tiling architecture: A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks....

20060104146 - Word line driving circuit of semiconductor memory device: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor...

20060104147 - Disk-shaped information recording medium, recording method and reproducing method thereof, information recording device and information reproducing device thereof: s

20060104148 - Command decoder of semiconductor memory device: A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite phase to...

20060104150 - Semiconductor memory device: The present invention relates to a semiconductor memory device operating synchronously with a clock signal. The memory device includes a circuit for converting an external command signal supplied via an external terminal into an internal command signal including latency and outputting a detection signal when a collision between the internal...

20060104151 - Single-clock, strobeless signaling system: A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by...

20060104149 - Synchronous semiconductor memory device: A synchronous semiconductor memory device reduces operation current by limiting unnecessary internal operations with a command interval defined in JEDEC Standard. The synchronous semiconductor memory device comprises a clock buffer, a plurality of command, a plurality of address buffers, a command decoder, a clock driving unit and a plurality of...

20060104152 - Controlling an addressable array of circuits: An addressable array of circuits is grouped into a plurality of sub-arrays. The addressable array of circuits is controlled by selecting a sub-array to reset and independently of the sub-array selected to be reset, selecting a sub-array to load with data. The sub-array selected to be reset is reset. Data...

20060098468 - Low power content addressable memory array (cam) and method of operating same: A content addressable memory (CAM) system that includes a row of NAND-type CAM cells divided into a plurality of segments. Each segment includes a plurality of series-connected switching transistors, wherein each of the switching transistors is part of a corresponding NAND-type CAM cell. The series-connected switching transistors of each segment...

20060098469 - Circuit wiring layout in semiconductor memory device and layout method: An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to...

20060098470 - Circuit for generating a centered reference voltage for a 1t/1c ferroelectric memory: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once...

20060098471 - High reliability area efficient non-volatile configuration data storage for ferroelectric memories: Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to...

20060098472 - Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a diode structure disposed on the resistor structure, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one...

20060098473 - Semiconductor memory element and semiconductor memory device: A semiconductor memory element that stores data as a resistance difference. The memory element comprises a MIS transistor, a two-terminal variable resistor element, and a fixed resistor element. The MIS transistor has a gate. The two-terminal variable resistor element is connected between the gate of the MIS transistor and a...

20060098476 - Circuit arrangement having security and power saving modes: Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another...

20060098474 - High performance, low leakage sram device and a method of placing a portion of memory cells of an sram device in an active mode: An SRAM device a method of placing a portion of memory cells of an SRAM device in an active mode. In one embodiment, the SRAM device includes (1) a set of memory cells and (2) biasing circuitry, coupled to the set, configured to bias a subset of the set based...

20060098475 - Static random access memory and pseudo-static noise margin measuring method: A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, which are connected between third and fourth...

20060098479 - cmi-001u solid state magnetic memory system and method: A solid state magnetic memory system and method disposes an array of magnetic media cells in an array on a substrate. In an exemplary embodiment, drive electronics are fabricated into the substrate through conventional CMOS processing in alignment with associated cells of the array. The magnetic media cells each include...

20060098478 - Magnetic memory device and writing method of the same: The present invention provides a magnetic memory device based on a novel driving method realizing reliable writing and a method of writing the magnetic memory device. Four parallel portions are formed in a pair of loop-shaped write lines (6Xn) and (6Yn). Magnetoresistive devices (12A) and (12B) disposed in the parallel...

20060098477 - Magnetic random access memory: A magnetic random access memory is composed of a plurality of first signal lines provided to extend in a first direction, a plurality of second signal lines provided to extend in a second direction substantially perpendicular to the first direction, a plurality of memory cells respectively provided at the intersections...

20060098480 - Memory: A memory is composed o a storage element 10 having a magnetization fixed layer 3 provided relative to a storage layer 5 through an intermediate layer 4 in which the direction of magnetization of the storage layer 5 is changed with application of an electric current to the storage element...

20060098481 - Circuitry for and method of improving statistical distribution of integrated circuits: An integrated circuit device comprising a memory array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is...

20060098482 - Floating-body dynamic random access memory with purge line: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell....

20060098483 - Variable programming of non-volatile memory: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are...

20060098484 - Memory block quality identification in a memory device: If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect. This indication is stored in the memory device. In one embodiment, the quality indication is stored in a predetermined location...

20060098485 - Printable non-volatile passive memory element and method of making thereof: Passive memory devices comprising at least one passive memory element and a support having a non-conductive surface on the at least one side provided with the passive memory element, the passive memory element comprising a first electrode system, an insulating system and a second electrode system, wherein the first electrode...

20060098486 - P-channel nand flash memory and operating method thereof: A p-channel NAND flash memory includes a plurality of memory cells in series connection between a p-type source region and a p-type drain region. Each memory cell includes a tunneling dielectric layer, a floating gate, and a control gate. An erase gate is formed between two adjacent memory cells, and...

20060098487 - Pumping voltage generating circuit in nonvolatile semiconductor memory device: Disclosed is a pumping voltage generating circuit in a nonvolatile semiconductor memory device. The present pumping voltage generating circuit begins a pumping operation for a wordline voltage in response to an accelerating start signal activated from a supply of an external program voltage, rather than a pumping enable signal activated...

20060098488 - Semiconductor memory device: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit...

20060098489 - Semiconductor integrated circuit device and non-volatile memory system using the same: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue...

20060098490 - Non-volatile semiconductor memory device and method for reading the same: In a reference cell 202, first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF1 of the first cell 50 is set to be a minimum value of a memory cell current after an erase operation....

20060098491 - Non-volatile memory device providing controlled bulk voltage during programming operations: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program...

20060098493 - Comprehensive erase verification for non-volatile memory: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements...

20060098494 - Comprehensive erase verification for non-volatile memory: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements...

20060098492 - Erase-verifying method of nand type flash memory device and nand type flash memory device thereof: An erase-verifying method of a NAND type flash memory device and NAND type flash memory device thereof, wherein an erase-verifying operation is performed by applying a positive voltage as a source voltage. Considering a variation width of a threshold voltage of an erase cell, which shifts due to various factors,...

20060098495 - Systems for comprehensive erase verification in non-volatile memory: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements...

20060098496 - Method and apparatus for setting operational information of a non-volatile memory: A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or...

20060098497 - Method and apparatus for filtering output data: Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option....

20060098498 - Methods of reading data including comparing multiple measurements of a characteristic of a data storage element and related devices: A method of reading data stored in a data storage element of an integrated circuit memory device may include applying a first electrical signal to the data storage element, and while applying the first electrical signal, taking a first measurement of an electrical characteristic of the data storage element. After...

20060098499 - Random access memory with stability enhancement and early read elimination: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the...

20060098500 - Truly random number generating circuit and method thereof: A chaotic circuit for truly random number generation is provided. The chaotic dynamical system used in the circuit is implemented based on the charge redistribution of capacitors. The random number generator circuit is a switched network including four capacitors and eight switches that are controlled by two-phase non-overlapping clock signals....

20060098501 - Voltage generating circuit and semiconductor memory device having the same: The present invention provides a voltage generating circuit and a semiconductor memory device having the same. The voltage generating circuit includes an internal voltage generating portion for generating an internal voltage in response to a signal input from an external portion; a sensing portion for outputting a sensing signal when...

20060098502 - Semiconductor memory device: A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write...

20060098503 - Apparatus and method for repairing semiconductor memory device: Apparatus and methods are provided for repairing semiconductor memory devices having an open bit line sense amplifier architecture with cell array blocks having memory blocks formed of edge sub-blocks, main sub-blocks, dummy sub-blocks. Row defects can be processed using a straight edge block when DQ data are outputted by enabling...

20060098504 - Semiconductor memory: A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lines upon every refresh request. An activation...

20060098505 - Failure test method for split gate flash memory: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first...

20060098506 - Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device: A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable...

20060098507 - Bridging circuit: A bridging circuit is provided. The bridging circuit includes a USB interface, a USB host, a memory card interface, a buffer and a microprocessor controller. The USB host reads data from and outputs data to a USB device via the USB interface. The memory card interface reads data from and...

20060098508 - Dram memory with common pre-charger: A memory layout where the pre-charger circuits are connected between different pairs of bit lines than are the sense amplifiers: The two bits lines in each bit line pair are connected to different pre-charge circuits and thus they can be charged to different pre-charge voltages. That is, the bit line...

20060098509 - Sequential tracking temperature sensors and methods: Temperature detectors include a temperature sensor that is configured to generate temperature tracking signals that indicate that a detected temperature is above, below or in a temperature range that corresponds to a selected one of a series of temperature control signals that indicate a series of temperature ranges. A control...

20060098510 - Volatile memory devices with auto-refresh command unit and circuit for controlling auto-refresh operation thereof and related memory systems and operating methods: Methods for automatically refreshing a plurality of memory cells in a volatile memory device are provided in which an auto-refresh mode of the volatile memory device is activated in response to an auto-refresh mode activation command. Thereafter, an auto-refresh operation may be performed on the plurality of memory cells in...

20060098511 - Method of using an e-fuse device: A method of using an e-fuse device is provided. The e-fuse device includes a poly-fuse having one end connected to a source/drain region of a MOS transistor and the other end biased to a voltage (VFS). In operation, a gate of the MOS transistor receives a step waveform pulse signal....

20060098512 - Electronic apparatus: There is provided an electronic apparatus comprising a battery holder, a detector detecting a battery, a non-volatile memory storing a program for initialization, a volatile memory, a first power supply for the non-volatile memory, a second power supply for the volatile memory, a power switch, a power supply controller activating...

20060098513 - Determining operation mode for semiconductor memory device: A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit....

20060098514 - Circuit for controlling differential amplifiers in semiconductor memory devices: Disclosed herein is a differential amplifier control circuit in which a signal indicating that all banks are not activated is provided to a differential amplifier, so that the differential amplifier does not operate, thereby reducing unnecessary current consumption in an ICC2N situation. An all bank idle notification unit generates an...

20060098518 - Memory array with staged output: Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments,...

20060098516 - Semiconductor memory device: A semiconductor memory device includes: a plurality of memory cells, a plurality of word lines and a plurality of column selecting lines. The plurality of memory cells is configured to be arrayed in a matrix. The plurality of word lines is configured to extend in a first direction which is...

20060098517 - Semiconductor memory device: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the...

20060098515 - Semiconductor memory device with column selecting switches in hierarchical structure: A semiconductor memory device has column selecting switches in a hierarchical structure. A plurality of local column selecting switches (LYSW) for controlling connections between bit lines (BLT/BLB) and local I/O lines (LIO). A global column selecting switch (GYSW) connects column selecting lines and four local column selecting switches (LYSW) when...

20060098519 - Semiconductor memory devices having a dual port mode and methods of operating the same: A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data received through a data bus to the first port in response to a leading edge...

20060098520 - Apparatus and method of word line decoding for deep pipelined memory: A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number...

20060098522 - Decoder for memory data bus: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page...

20060098523 - Semiconductor memory device capable of driving non-selected word lines to first and second potentials: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation...

20060098521 - Transistor array substrate and display panel: A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned...

20060098524 - Forming planarized semiconductor structures: A planarized surface may be formed by initially forming an aperture through an insulating layer. The insulating layer and its aperture may be conformally coated with a conductive material that ultimately acts as a planarization stop. The conductive material may then be covered with another insulator that fills the remainder...

20060098525 - Array substrate and display apparatus having the same: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the...

20060092679 - Array substrate, method of inspecting the array substrate and method of manufacturing the array substrate: An array substrate comprising a substrate on which a plurality of scanning lines and a plurality of signal lines are arranged so as to intersect each other, pixel sections formed on the substrate and including an auxiliary capacitor and a switching element which is located close to each of intersections...

20060092680 - Semiconductor memory device: A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port 13a, and a plurality of second word lines WLB0-WLBn connected to a second port 13b. Each of a...

20060092681 - Semiconductor device and method for testing semiconductor device: A semiconductor device includes a memory cell array, in which bit lines intersect word lines to form a memory cell. Representative pads are selected from among pads. Data input to the representative pads is decompressed to data corresponding to all of the pads, and is written in corresponding memory cells....

20060092682 - Semiconductor memory device and a method for arranging signal lines thereof: The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first...

20060092683 - Operating techniques for reducing program and read disturbs of a non-volatile memory: The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a...

20060092684 - 3-bit nrom flash and method of operating same: Operation of conventional nitride read-only-memory (NROM) cells is modified, such that each charge trapping region of an NROM cell is capable of storing any one of three charge states. For example, each charge trapping region can have an erased state, a first programmed state, or a second programmed state. Each...

20060092685 - Storage apparatus: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state...

20060092686 - Semiconductor memory device for low power condition: A semiconductor memory device for reading or writing data from or to a memory cell includes at least one cell array having a plurality of memory cells for outputting a stored data to one of a bit line and a bit line bar in response to inputted address and command;...

20060092687 - Molecular memory devices and methods: A molecular memory element comprising a switching device; at least a first bit line and a first word line coupled to said switching device; and an array of storage locations, each coupled to a bit line and a word line, said elements comprising a first electrode with storage molecules comprising...

20060092692 - Magnetic random access memory: Setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write...

20060092690 - Magneto-resistive ram having multi-bit cell array structure: A magnetic random access memory (RAM) with a multi-bit cell array structure includes an access transistor formed on a substrate, first through third resistance-variable elements, and first through third current supplying lines. The first through third resistance-variable elements are disposed between a bit line and the access transistor, and electrically...

20060092691 - Memory element and method of driving the same: A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of...

20060092689 - Reference current source for current sense amplifier and programmable resistor configured with magnetic tunnel junction cells: A reference current source for a magnetic memory device is preferably configured with magnetic tunnel junction cells and includes more than four reference magnetic memory cells to improve reliability of the magnetic memory device and to reduce sensitivity at a device level to individual cell failures. The reference current source...

20060092688 - Stacked magnetic devices: Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying...

20060092694 - Phase change memory device and method of operating the same: A phase change memory device and a method of operating the same are provided. The phase change memory device may include a plurality of unit cells arranged in a matrix composed of rows and columns; a plurality of program bit lines and read bit lines arranged in rows, each of...

20060092693 - Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same: A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed in electrical contact with the first electrode....

20060092695 - Hybrid memory array with single cycle access: A memory array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory cells to be of a single cycle....

20060092696 - Storage element and memory: A memory includes a storage element (10) composed of a storage layer (5) for holding information with the magnetization state of a magnetic material, a magnetization fixed layer (3) provided relative to the storage layer (5) through an intermediate layer (4), the magnetization of the storage layer (5) being changed...

20060092697 - Addressing architecture for perpendicular giant magnetoresistance memory: A magnetic memory storage device with at least one magnetic storage element comprising electrical addressing leads to inject electrical current directly through a single magnetic memory storage element. The number of electrical addressing leads is at least one more than the number of magnetic memory storage elements....

20060092698 - Magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures and related methods: A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent...

20060092699 - Semiconductor storage device: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array;...

20060092700 - Semiconductor device having enhanced breakdown voltage: A semiconductor device has: a main circuit including a plurality of MOS transistors operating at a first voltage; a memory requiring an operation at a second voltage higher than the first voltage; and a drive circuit for driving the memory, the drive circuit comprising one well, two or more MOS...

20060092701 - Nonvolatile memory circuit: A nonvolatile memory circuit includes a flip-flop to degrade an internal circuit irreversibly based on a voltage applied to a first or second bit line so as to latch data in a nonvolatile manner, a first switch coupled between a first output terminal of the flip-flop and the first bit...

20060092702 - Apparatus and method for programming and erasing virtual ground eeprom without disturbing adjacent cells: A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions....

20060092707 - Bitline bias circuit and nor flash memory device including the bitline bias circuit: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible...

20060092703 - Flash memory device and method of programming the same: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a...

20060092704 - Semiconductor device: A semiconductor device includes an electrical circuit formed on a substrate; a level detector outputting a first level signal which has a signal level based on power supply voltage and which determines an operation of the electrical circuit; a command decoder decoding a command that is inputted from the outside,...

20060092706 - Semiconductor device and method for controlling the same: A semiconductor device includes a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, and a pull-down circuit that pulls down a potential of an output of the program voltage supply circuit in accordance with a current that flows in a data bus...

20060092705 - Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge...

20060092708 - Semiconductor memory device and electric device with the same: A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal...

20060092709 - Devices and methods to improve erase uniformity and to screen for marginal cells for nrom memories: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other...

20060092712 - Branch target buffer and method of use: A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line...

20060092711 - Efficient implementation of a read scheme for multi-threaded register file: A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line...

20060092710 - Efficient method of data transfer between register files and memories: A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and...

20060092713 - Synchronous memory open page register: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment,...

20060092715 - Circuit: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level....

20060092718 - Flash memory data bus for synchronous burst read page: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page...

20060092716 - Memory devices using tri-state buffers to discharge data lines, and methods of operating same: A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output...

20060092717 - Methods and computer program products for determining simultaneous switching induced data output timing skew: A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is...

20060092714 - Semiconductor memory device with simplified data control signals: A semiconductor memory device for reducing data line length includes a plurality of data input strobe signal generation units each of which for generating a plurality of data input strobe signals based on a plurality of data input control code signals; and a plurality of data coders one-to-one corresponded to...

20060092719 - Semiconductor memory device: A semiconductor memory device has a memory cell array, first dummy bit lines, second dummy bit lines, first dummy cells each of which is connected to the corresponding first dummy bit line and generates a reference current for data “0”, second dummy cells each of which is connected to the...

20060092720 - Semiconductor memory: A semiconductor memory in which a drop in the potential of a bit line due to coupling capacitance at the time of writing data can be restored in a space-saving way without increasing a load at read time. In response to a selection signal, a selection circuit selects complementary bit...

20060092721 - Memory system, a memory device, a memory controller and method thereof: The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level...

20060092722 - Data arrangement control signal generator for use in semiconductor memory device: A data arrangement control signal generation circuit for use in a semiconductor memory device includes a plurality of data arrangement control signal generation units connected in series, each for selectively generating a data arrangement control signal according to a column address strobe (CAS) latency....

20060092723 - Data input/output method of semiconductor memory device and semiconductor memory device for the same: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and...

20060092726 - Memory redundancy programming: A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes...

20060092725 - Redundancy circuit and repair method for a semiconductor memory device: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units,...

20060092724 - Semiconductor memory device with mos transistors each having floating gate and control gate: A semiconductor memory device includes a row address transition detector. The semiconductor memory device remedies a fault by replacing a column in a memory cell array with a redundancy bit line. The row address transition detector detects a change in a row address signal for selecting the row direction of...

20060092728 - Circuit and method for test mode entry of a semiconductor memory device: A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is...

20060092727 - Flood mode implementation for continuous bitline local evaluation circuit: A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a...

20060092729 - Verifying circuit and method of repairing semiconductor device: Example embodiments of the present invention disclose a verifying circuit and a method of repairing a semiconductor device. The verifying circuit may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on...

20060092730 - Semiconductor memory device for low power condition: An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar. The apparatus includes a precharge block for precharging the bit line and the bit...

20060092731 - Semiconductor memory device for low power system: An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar. A precharge block precharges the bit line and the bit line bar at a...

20060092732 - Semiconductor memory device for low power system: An apparatus included in a semiconductor memory device for precharging a bit line and a bit line bar and sensing and amplifying a data delivered to one of the bit line and the bit line bar includes a precharge means for precharging the bit line and the bit line bar...

20060092733 - Semiconductor memory device for low power system: A semiconductor memory device for outputting or storing a data in response to inputted address and command includes a first cell array for outputting the data to one of a bit line and a bit line bar; a first reference cell block for outputting a reference signal to the other...

20060092734 - Read circuit of semiconductor memory: A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes...

20060092736 - Integrated semiconductor memory device including sense amplifiers: An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within the memory cell array. When a memory cell is...

20060092735 - Method for measuring offset voltage of sense amplifier and semiconductor employing the method: A semiconductor memory device precisely measures the offset voltage of a bit line sense amplifier. The semiconductor memory device of the invention includes: a bit line sense amplifier for amplifying a voltage difference between a bit line and an inversion bit line, which carry data written on a memory cell...

20060092737 - Memory and semiconductor device: A memory includes: memory elements arranged in a matrix, each memory element having such characteristics that when an electric signal at a level equal to or higher than that of a first threshold signal is applied to the memory element, the resistance thereof is changed from a high value to...

20060092739 - Semiconductor memory device: A semiconductor memory device has memory cells each of which has a MIS type of transistor capable of setting one of two kinds of threshold potentials, reference cells used for determining data stored in the memory cells, which have the same size, shape and electrical properties as those of the...

20060092738 - Semiconductor memory device for low power system: A semiconductor memory device for outputting or storing a data in response to inputted address and command includes a first cell array for outputting the data to one of a bit line and a bit line bar; a first reference cell block for outputting a reference signal to the other...

20060092740 - Multiport semiconductor memory device: In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD−Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports...

20060092741 - Self refresh circuit of psram for real access time measurement and operating method for the same: A self refresh circuit includes a refresh control unit and an internal refresh circuit. The refresh control unit generates a refresh control signal based on a refresh period pulse when a MRS (Mode Set Register) command is deactivated, interrupts an output of the refresh control signal based on a self-refresh-entrance...

20060092742 - Otp antifuse cell and cell array: Different embodiments of a one-time-programmable antifuse cell are provided in this disclosure. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a...

20060092744 - Power supply control circuit and controlling method thereof: The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in...

20060092743 - Semiconductor memory device and internal voltage generating method thereof: A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active...

20060092745 - Semiconductor memory device with internal power supply: Provided is a semiconductor memory device including an internal power supply with low current consumption, which includes: an active interval security block for generating active interval security signals with operation intervals by a row active signal and a column active signal; an active driving signal generating block for generating an...

20060092746 - Semiconductor memory device capable of reducing power consumption during reading and standby: The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many...

20060092747 - Memory bank structure: The present invention relates to a memory bank structure. The memory bank structure includes: a plurality of sub-banks identified by a predetermined additional address; a plurality of local input/output line precharge units for precharging local input/output lines included in each of the sub-banks; and a plurality of local input/output line...

20060092748 - Semiconductor memory: A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in...

20060092749 - Bitline layout in a dual port memory array: A multi-port memory array according to some embodiments of the present invention includes a first complementary pair of bit lines of length L corresponding to a first port; a second complementary pair of bit lines of length L corresponding to a second port, wherein the first complementary pair of bit...

20060092750 - Line driver circuit for a semiconductor memory device: A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word...

20060092751 - Peripheral management: A peripheral management system includes a listing of a plurality of peripheral types and at least one driver associated with selected ones of the plurality of peripheral types....

20060092752 - Multiple chip package and ic chips: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on...

20060092753 - Semiconductor device and testing method for semiconductor device: To test a memory operation at as high speeds as high clock frequencies only with low clock frequencies. A semiconductor device according to an embodiment of the present invention includes: a clock output part; and a delay circuit, the clock output part setting a first state in accordance with an...

20060092754 - Semiconductor memory device with reduced number of pads: A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the...

20060092755 - Semiconductor test apparatus and control method therefor: There is provided a semiconductor test apparatus including: a first waveform generating means that generates a common pattern waveform corresponding to common information common to each of a plurality of semiconductor devices; a plurality of second waveform generating means that generates individual pattern waveforms corresponding to a plurality of individual...