FREE patent keyword monitoring and additional FREE benefits. /images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
Fresh Patents freshpatentsnav7_icons (5K)
browse patent apps by agents browse patent apps by inventors browse patent apps by industry browse patents by location monitor patent applications
    



USPTO Class 365  |  Browse by Industry: Previous - Next | All     monitor keywords
04/2006 | Recent  |  08: Dec | Nov | Oct | Sp | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 07: D | N | O | S | A | J | J | M | A | M | F | J |  | 06: 12 | 11 | 10 | 09 | 8 | 7 | 6 | 5 | 4 | Dec | Nov |  | 2010 | 2009 |

    SEARCH:      Monitor Keywords | rss Custom RSS

Static information storage and retrieval April category listing, related patent applications 04/06

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
04/27/2006 > 37 patent applications in 23 patent subcategories. category listing, related patent applications

20060087873 - Method and sum addressed cell encoder for enhanced compare and search timing for cam compare: A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment...

20060087874 - Magnetic memory device: A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ...

20060087875 - Polymer de-imprint circuit using negative voltage: Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another...

20060087877 - Phase-change semiconductor memory device and method of programming same: Disclosed are a semiconductor memory device and a method of programming the same. The semiconductor memory device comprises a plurality of memory cells, each of the memory cells having a plurality of phase change variable resistors and a selection transistor. Each of the phase change variable resistors has a first...

20060087876 - Semiconductor memory device: A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal...

20060087878 - Forced pulldown of array read bitlines for generating mux select signals: An apparatus, a method, and a computer program product are provided for time reduction in an array read access control consisting of a bitcell and a pulldown device outside of the bitcell. To reduce gate delay, this design implements a pulldown device that controls the bitcell readout. A pulldown signal...

20060087879 - Mram architecture for low power consumption and high selectivity: The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossing each other at a cross-point region but not being in direct contact. According to...

20060087880 - Spin-transfer based mram using angular-dependent selectivity: A magnetic random access memory (“MRAM”) device can be selectively written using spin-transfer reflection mode techniques. Selectivity of a designated MRAM cell within an MRAM array is achieved by the dependence of the spin-transfer switching current on the relative angle between the magnetizations of the polarizer element and the free...

20060087881 - Advanced multi-bit magnetic random access memory device: An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more pair-cells. A pair-cell is two memory cells. Each memory cell has a magnetic multilayer structure. The structure includes a magnetically changeable...

20060087883 - Anti-tamper module: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided...

20060087882 - Data retention kill function: A secure memory device that is configured to prevent unauthorized access of data is disclosed. More specifically, a kill function logic device is capable of initiating security measures upon the occurrence of some event. The security measures may include disabling read access to the memory device, accelerated erasing of the...

20060087884 - Semiconductor memory device and method of controlling semiconductor memory device: A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite...

20060087885 - Memory card, semiconductor device, and method of controlling memory card: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile...

20060087886 - Nonvolatile integrated circuit memory devices having staged application of program voltages and methods for programming the same: A nonvolatile integrated circuit memory device includes a memory cell array having a plurality of memory cells. A high voltage generating unit generates first, second, and third program voltages used in programming the memory cell array. A program control unit controls times of applying the second and third program voltages...

20060087887 - Non-volatile semiconductor memory device: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data...

20060087891 - Non-volatile memory device and method of programming same: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage...

20060087890 - Non-volatile memory device having controlled bulk voltage and method of programming same: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by...

20060087889 - Nonvolatile memory device and method of improving programming characteristic: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second...

20060087888 - Nonvolatile memory device and method of programming same: A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is...

20060087892 - Programming flash memories: A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted to perform a method of...

20060087893 - Storage device and information processing system: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from...

20060087894 - Interface circuit for adaptively latching data input/output signal by monitoring data strobe signal and memory system including the interface circuit: In a memory system, a memory device that outputs a data strobe signal and memory cell data according to a read command. A memory controller receives the data strobe signal and latches the memory cell data that is output by the memory device, using an interface circuit that realigns the...

20060087895 - Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution: The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main memory block. The substitution memory block is arranged to substitute at least one bitline-related or wordline-related set of memory cells...

20060087896 - Semiconductor memory: The invention relates to semiconductor memories and in particular to DRAMs. A semiconductor memory is provided comprising at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, further comprising a tri-state...

20060087897 - Memory output data systems and methods with feedback: Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a memory through feedback of the output data signal....

20060087898 - Leakage current control device of semiconductor memory device: A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control...

20060087899 - Wordline voltage generating circuit including a voltage dividing circuit for reducing effects of parasitic capacitance: Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected...

20060087900 - Semi-conductor component, as well as a process for the in-or output of test data: The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor...

20060087901 - Device for controlling temperature compensated self-refresh period: A device for controlling a temperature compensated self-refresh period clamps a self-refresh signal at high temperature over a specific temperature to maintain the self-refresh period, thereby removing dependency on temperature. In the device, an oscillating signal having a period varied depending on temperature change is generated below a specific temperature,...

20060087904 - Memory device capable of refreshing data using buffer and refresh method thereof: An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes...

20060087903 - Refresh control method of a semiconductor memory device and semiconductor memory device: A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, comprising: a step for dividing the...

20060087902 - Selective bank refresh: A method of refreshing several memory banks of a memory device that receives command signals from a memory controller. The method includes monitoring command signals received by a memory device and refreshing the several memory banks based on the monitored command signals so as to avoid unnecessary power consumption for...

20060087905 - Voltage translator for multiple voltage operations: A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes...

20060087906 - Simulating a floating wordline condition in a memory device, and related techniques: A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area. The extra wordlines...

20060087907 - Delay stage-interweaved analog dll/pll: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency...

20060087908 - Delay stage-interweaved analog dll/pll: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency...

20060087909 - Semiconductor integrated circuit device: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit...

  
04/20/2006 > 64 patent applications in 42 patent subcategories. category listing, related patent applications

20060083040 - Programmable non-volatile semiconductor memory device: The present invention relates to a programmable non-volatile semiconductor memory device comprising a matrix of rows and columns of memory cells (1). To reduce the required memory area a 3T memory cell is proposed comprising a bridge of two bridge transistors (MN0, MN1), preferably NMOS transistors, a read transistor, preferably...

20060083041 - Matchline sense circuit and method: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit...

20060083042 - Multiple match detection circuit and method: A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order...

20060083043 - Memory system topology: A memory subsystem. A memory subsystem includes a memory controller coupled to a processor and a plurality of N memory modules. The memory controller is directly coupled to convey information to the Nth memory module through a downstream link, and is directly coupled to receive information from a first memory...

20060083044 - Mmc memory card with tsop package: The MMC memory card with TSOP package includes a circuit board with a plurality of passive elements and ICs installed thereon and a plastic housing is covered over and enclosing the circuit board to form a memory card structure. At least one flash memory of the ICs is used with...

20060083045 - Semiconductor memory device with mos transistors each having floating gate and control gate: A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. Each word line is formed by connecting commonly the...

20060083046 - Semiconductor integrated circuit: A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a...

20060083049 - Ferroelectric memory: For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the logic values of data stored...

20060083048 - Multi-stable vortex states in ferroelectric nanostructure: A ferroelectric nanostructure formed as a low dimensional nanoscale ferroelectric material having at least one vortex ring of polarization generating an ordered toroid moment switchable between multi-stable states. Such a nanostructure is capable of achieving ultrahigh recording density in non-volatile ferroelectric random access memory (NFERAM) and may have applications in...

20060083051 - Nonvolatile ferroelectric memory device having a multi-bit control function: A nonvolatile ferroelectric memory device having a multi control function can amplify sensing voltage levels in a sensing critical voltage and determine a plurality of cell data when a plurality of reference timing strobes are applied on a basis of a time axis. In a read mode, a plurality of...

20060083050 - Nonvolatile memory cell and methods for operating a nonvolatile memory cell: A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile memory cells (2). The memory cell (1) has a programmable component (3) having an electrical resistance that can be altered by reprogramming, and also first...

20060083047 - Nonvolatile memory for logic circuits: A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the at least one nonvolatile memory includes a high resistive state and a low resistive state. The volatile data storage...

20060083052 - Self reverse bias low-power high-performance storage circuitry and related methods: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second...

20060083056 - Magnetic memory layers thermal pulse transitions: A ferromagnetic thin-film based digital memory having a bit structures therein a magnetic material film in which a magnetic property thereof is maintained below a critical temperature above which such magnetic property is not maintained, and may also have a plurality of word line structures each with heating sections located...

20060083053 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes a magnetoresistive element which has a planar shape having a plurality of corners and in which at least one corner has a radius of curvature of 20 nm or less....

20060083054 - Methods of operating a magnetic random access memory device and related devices and structures: A magnetic random access memory (MRAM) device may include a magnetic tunnel junction structure between first and second electrodes. Methods of operating such as MRAM device may include providing a write current through the first electrode, through the magnetic tunnel junction structure, and through the second electrode. An auxiliary switching...

20060083055 - Providing a reference voltage to a cross point memory array: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug....

20060083057 - Magnetoresistive element: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual...

20060083058 - Semiconductor memory and fbc memory cell driving method: A semiconductor memory comprises a semiconductor substrate including a semiconductor film on a first insulating film; a memory cell that stores data by charging or discharging a body region formed in said semiconductor film, the memory cell including a source layer on one side of said body region and a...

20060083059 - Semiconductor device, reset control system and memory reset method: In a semiconductor device comprising a non-volatile memory, a reset input control circuit is provided not to supply the reset signal to the non-volatile memory even when the reset signal is supplied from the external side while the BUSY/READY signal from the non-volatile memory is activated. With the reset input...

20060083060 - Flexible otp sector protection architecture for flash memories: A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds...

20060083061 - Flash cell fuse circuit: Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of...

20060083062 - Block switch in flash memory device: Disclosed herein is a block switch of a flash memory device in which a voltage higher than a predetermined operating voltage is generated to drive path transistors in order to stably apply the predetermined operating voltage to a selected cell block of the flash memory device. The block switch generates...

20060083063 - Memory devices with page buffer having dual registers and method of using the same: A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the...

20060083065 - Nand flash memory and blank page search method therefor: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds...

20060083064 - Semiconductor memory device with mos transistors each having floating gate and control gate and method of controlling the same: A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix and a second cell array including...

20060083068 - Apparatus and method of driving non-volatile dram: A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer...

20060083067 - Method for determining programming voltage of nonvolatile memory: A method for determining programming voltage of a nonvolatile memory in which any variation in the threshold voltage at the memory cell after programming by hot carrier injection can be suppressed includes the steps of: setting the drain voltage to an initial setting level; applying the drain voltage and a...

20060083066 - Nonvolatile semiconductor memory device with memory cells, each having an fg cell transistor and select gate transistor, and a method of writing data into the same: A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the...

20060083069 - System and method of controlling a three-dimensional memory: A system and method of controlling a three dimensional memory is disclosed. In a particular embodiment, the system is implemented as an integrated circuit including a microcontroller having a control signal output, a three-dimensional monolithic non-volatile memory having a plurality of levels of memory cells above a silicon substrate and...

20060083070 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes a memory cell 6 composed of a memory cell transistor 1 having a floating gate and a control gate and a memory cell selecting transistor 2, a reference cell 12 composed of a reference cell transistor 30 having the same structure as the memory cell...

20060083071 - Nonvolatile semiconductor memory device and an operation method thereof: A nonvolatile semiconductor memory device comprises a memory cell array which a plurality of an electrically rewritable nonvolatile memory cell is arranged and a sense amplifier having first, second and third circuits holding write-in data; and the first circuit receives data from the outside and transmits the data to the...

20060083073 - Method for setting erasing pulse and screening erasing defect of nonvolatile memory: Method for determining the number of applications of erasing pulses, memory cells comprises, extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased memory cells in the target block to be erased after the accumulated number of the erasing...

20060083072 - Semiconductor memory device with mos transistors each having floating gate and control gate: A semiconductor memory device comprises a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate...

20060083074 - Array read access control using mux select signal gating of the read port: An apparatus, a method, and a computer program product are provided for time reduction for an array read access control consisting of a bitcell with logic gating and a pull down device included, therein. To reduce gate delay this design implements gating logic inside the bitcell. The multiplex select gating...

20060083075 - Combined receiver and latch: A combined receiver and latch circuit is configured to receive an external clock signal, an external reference voltage and an external command signal. The circuit includes first and second nodes, first and second control gates, and an output circuit. The first and second nodes are each configured to be precharged...

20060083076 - Data management apparatus: A backup data storage control unit makes a write-once storage medium store by-generation backup data in order of generations. A generation identification data storage control unit makes a generation identification data of the backup data stored at a storage position right in front of the by-generation backup data in the...

20060083077 - Memory device: A semiconductor memory device includes a plurality of memory cells arranged according to a plurality of rows and a plurality of columns. The memory devices further includes a plurality of bit lines, each bit line being associated with a respective column of the plurality, and a selecting structure of the...

20060083078 - Memory device: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of...

20060083079 - Output buffer of a semiconductor memory device: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a...

20060083080 - User configurable commands for flash memory: A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the boot data includes a reconfigured command, that command is loaded into the register. A signal...

20060083081 - Memory system, memory device, and output data strobe signal generating method: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more...

20060083082 - Dqs for data from a memory array: A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal...

20060083083 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line...

20060083087 - Apparatus and method for semiconductor device repair with reduced number of programmable elements: An apparatus and method using a reduced number of nonvolatile programming elements for enabling redundant memory blocks in a semiconductor memory is disclosed. A redundancy selection module may be configured using N fuses to configure and select 2N-1 repair modules. Programming fuses effectively separates the repair modules into two sets,...

20060083085 - Integrated circuit device and testing method thereof: An integrated circuit device has a plurality of memory macros that include a redundant circuit to replace a defective cell and a plurality of bits of nonvolatile memory elements that store redundant replacement information to replace a defective cell of a first memory macro selected from the plurality of memory...

20060083086 - Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions: A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the...

20060083084 - Semiconductor test system: The semiconductor test system comprises a test device 10 for testing semiconductor devices including redundant circuits to obtain fail information of defective parts of the semiconductor devices; a redundant remedy judging device 14 which includes fail memories 36a-36d for storing the fail information, and a redundant remedy judging unit 40...

20060083090 - Method and apparatus for identifying short circuits in an integrated circuit device: The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a second memory cell associated with a second...

20060083089 - Non-volatile memory with test rows for disturb detection: A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not...

20060083088 - Spintronic devices with integrated transistors: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in...

20060083091 - Semiconductor storage device precharging/discharging bit line to read data from memory cell: A read circuit includes a precharge circuit, a discharge circuit, and a sense amplifier. The precharge circuit includes a first transistor which has a gate connected to the bit line, a second transistor which has a gate connected to the bit line, the second transistor having a current path one...

20060083092 - Dynamical adaptation of memory sense electronics: A circuit and a method are given, to realize a dynamically adapting response speed behavior of memory sense electronics for Sense Electronics Endowed (SEE) memory devices. Fast memories use sense amplifiers in the read path in order to react fast with the data being delivered from a given address position....

20060083094 - Method and apparatus for controlling refresh operations in a dynamic memory device: A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more...

20060083093 - Non-volatile configuration data storage for a configurable memory: Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset....

20060083095 - Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features: An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die...

20060083097 - Method and system for providing sensing circuitry in a multi-bank memory device: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common...

20060083096 - Semiconductor memory device and package thereof, and memory card using the same: Disclosed herein are a semiconductor memory device and package thereof, and a memory card using the same. The semiconductor memory device may include a memory cell array in which a plurality of memory cells that share a word line constitutes a page. The same row address signal is inputted to...

20060083098 - Electronic memory with binary storage elements: An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used...

20060083100 - Integrated semiconductor memory and method for operating an integrated semiconductor memory: A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that...

20060083099 - System and method for redundancy memory decoding: A redundancy system for disabling access to normal memory elements when memory addresses corresponding to those normal memory elements match programmed redundancy addresses before the memory addresses and the programmed redundancy addresses are compared. Access to the normal memory elements is disabled based on the programmed redundancy addresses....

20060083101 - Method of address distribution time reduction for high speed memory macro: An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate...

20060083102 - Failover control of dual controllers in a redundant data storage system: A redundant data storage system is provided comprising a first controller with top-level control of a first memory space and a second controller with top-level control of a second memory space different than the first memory space. The system is adapted for asynchronously reflectively writing state information by the first...

20060083103 - Buffered continuous multi-drop clock ring: A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free...

  
04/13/2006 > 51 patent applications in 30 patent subcategories. category listing, related patent applications

20060077702 - Semiconductor memory: Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a...

20060077703 - Integrated circuit device provided with series-connected tc parallel unit ferroelectric memory and method for testing the same: An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected...

20060077704 - Integrated circuit including sensor to sense environmental data, and system for testing: An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and to the operational circuitry and configured to affect the operational circuitry to at least partially counteract the effects of the environmental parameter. A method of testing an integrated...

20060077705 - Methods of accelerated life testing of programmable resistance memory elements: A method of testing a programmable resistance memory element. The method comprises applying a plurality of reset pulses to the memory element. Each of the reset pulses having an energy which is greater than the minimum energy needed program the memory element from its set state to its reset state....

20060077706 - Multilevel phase-change memory, operating method and manufacture method thereof: A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved...

20060077707 - Thermomagnetically assisted spin-momentum-transfer switching memory: A ferromagnetic thin-film based digital memory having a substrate supporting bit structures that are electrically interconnected with information storage and retrieval circuitry and having first and second oppositely oriented relatively fixed magnetization layers and a ferromagnetic material film in which a characteristic magnetic property is substantially maintained below an associated...

20060077711 - Method for improving programming speed in memory devices: A high voltage up to 20V is usually applied to a NAND flash memory device for programming or easing a memory section. The programming/easing voltage must reach that high voltage state when the R/B signal is in the L state to start the actual cell programming or erasing. To improve...

20060077712 - Non-volatile semiconductor memory device, electronic card using the same and electronic apparatus: Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and...

20060077713 - Semiconductor device: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first...

20060077708 - Distributed programmed memory cells used as memory reference currents: A memory circuit for an inkjet print head having a plurality of memory cells switchably connected to a source and configured in an array, wherein at least one of the memory cells is a reference memory cell and at least one of the remaining cells are data memory cells, and...

20060077710 - Reading circuit and method for a nonvolatile memory device: Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents...

20060077709 - System and method for avoiding offset in and reducing the footprint of a non-volatile memory: A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the...

20060077714 - Method and system for a programming approach for a nonvolatile electronic device: Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a...

20060077715 - Read-accessible column latch for non-volatile memories: Program column latch circuitry of nonvolatile memory is provided with read-back capability to verify that data bits have been correctly loaded into the latch circuits and written to the memory cells. The interface between the low voltage latches and the external input and output data paths is provided with opposite-facing...

20060077717 - Row decoder circuit for use in non-volatile memory device: The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage,...

20060077716 - Row decoder circuit of nand flash memory and method of supplying an operating voltage using the same: A row decoder circuit of a NAND flash memory and method of supplying an operating voltage using the same. To prevent an operating voltage (e.g., a program voltage, a pass voltage, or a read voltage) from being abnormally transferred to a gate of a memory cell because a pumping voltage...

20060077718 - Nonvolatile memory and method of erasing for nonvolatile memory: The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from...

20060077720 - High speed programming for nonvolatile memory: A nonvolatile memory device is programmed by selectively scanning input data bits to detect data bits to be programmed, and programming the detected data bits. The detected data bits may be programmed in predetermined units. The input data bits may be selectively scanned by combining input data bits in groups,...

20060077719 - Reprogrammable integrated circuit (ic) with overwritable nonvolatile storage: A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then,...

20060077721 - Semiconductor integrated circuit with flash interface: A semiconductor integrated circuit has a flash interface for receiving command codes and controlling a flash memory to perform corresponding read, write, and erase operations. The flash interface generates a status signal indicating whether the flash memory is currently being controlled or not. The flash interface includes an address circuit...

20060077722 - Direct memory access interface in integrated circuits: A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit...

20060077723 - Memory circuit arrangement and method for the production thereof: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the...

20060077727 - Data latch circuit and semiconductor device using the same: There is provided a data latch circuit that comprises a first buffer for buffering an input data signal in synchronization with an input strobe signal, a first latch unit for conducting a switching operation in response to the strobe signal and latching an output signal from the first buffer for...

20060077725 - Data output controller for memory device: Disclosed is a data output controller for a memory device. The data output controller for a memory device, the data output controller comprising a control part for generating a first pulse control signal and a second pulse control signal through a combination of an internal clock signal outputted from a...

20060077726 - Data transfer method, storage apparatus and computer-readable storage medium: A data transfer method transfers data stored in a first storage part to a second storage part within a storage apparatus. All data stored in units of data regions within the first storage part are transferred to the second storage part, and with respect to each data region for which...

20060077724 - Disk array system: The present invention enables to secure data reliability by avoiding data loss in an early failure period of an operation of a disk array system to which no particular measures have been taken conventionally. A controller of the disk array system stores first data to be stored in a HDD...

20060077728 - Method for fabricating flash memory device and structure thereof: A method for fabricating a flash memory device is provided. A tunnel oxide layer is formed over a substrate. Thereafter, a floating gate, an inter-gate dielectric layer, and a control gate are sequentially formed over the tunnel oxide layer. Since the floating gate includes a plurality of nanocrystals, the memory...

20060077729 - Low current consumption at low power dram operation: A memory device connectable to an external power supply voltage, includes an array of memory cells defined by a plurality of bit lines and a plurality of word lines, each memory cell corresponding to a respective bit line and a respective word line; an equalization circuit for equalizing the plurality...

20060077730 - Memory control module and method for operating a memory control module: The invention relates to a method for transmitting memory data from a memory to a memory control module, in which method a read command is transmitted from the memory control module to the memory, and the memory data which correspond to the read command are transmitted from the memory to...

20060077731 - Memory module with termination component: A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal...

20060077734 - Direct mapped repair cache systems and methods: The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a repair verification router that compares a memory address 604 for a read/write request to a list or series of...

20060077733 - Memory structure with repairing function and repairing method thereof: A memory structure with a repair function and a repairing method thereof are provided. The memory structure has an independent main memory unit and register file design. It also incorporates a record control unit for storing the fault information of the main memory unit. Upon receiving an access command, the...

20060077732 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value of the normal data is changed or not, and a determination circuit which determines whether a value of the normal data is...

20060077735 - Memory regulator system with test mode: A system for switching between a read mode and a write mode. The system includes a voltage regulating circuit and a memory array. The voltage regulating circuit includes a voltage input and a control input, wherein the control input regulates the voltage input between at least a first voltage output...

20060077736 - Semiconductor device, semiconductor device testing method, and programming method: A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes:...

20060077738 - Light emitting display and data driver there of: An organic light emitting diode display being driven according to a current programming method. A digital/analog converter of a data driver sequentially converts data signals representing gray scales to data currents and sequentially transmits the data currents to an output stage. The output stage sequentially samples the data currents and...

20060077737 - Non-volatile semiconductor memory device: A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are...

20060077739 - Low voltage sense amplifier for operation under a reduced bit line bias voltage: A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (Vcc), generates a regulated voltage (VSA) over a range of supply voltages. The regulated charge pump powers sense amplifier and differential amplifier circuits of the memory device to permit a...

20060077740 - Apparatus and method for generating an imprint-stabilized reference voltage for use in a ferroelectric memory device: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is...

20060077742 - Memory devices configured to detect failure of temperature sensors thereof and methods of operating and testing same: A memory device includes a temperature sensor configured to generate a temperature detection signal responsive to a temperature of the memory device and a self-refresh control circuit configured to control a refresh of the memory device responsive to the temperature detection signal. The device further includes a temperature-detection-error sensing circuit...

20060077743 - Memory devices including barrier layers and methods of manufacturing the same: Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may...

20060077741 - Multilevel phase-change memory, manufacturing and status transferring method thereof: A multilevel phase-change memory, manufacturing method and status transferring method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a series structure to form a memory cell. A current-drive mode is employed to control and drive the memory such that multilevel memory states may be...

20060077744 - Internal voltage supply circuit: Disclosed herein is an internal voltage supply circuit for a semiconductor device. The internal voltage supply circuit includes a first voltage driver for supplying a first voltage in response to a first enable signal, a second voltage driver for supplying a second voltage in response to a second enable signal,...

20060077745 - Semiconductor device and method for boosting word line: A semiconductor device of the present invention includes a booster circuit 20 that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit...

20060077748 - Address buffer circuit and method for controlling the same: An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is disabled in response to a second level of the control signal. An address buffer control unit...

20060077746 - Column decoding architecture for flash memories: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state...

20060077747 - Semiconductor device and data reading method: The present invention has an arrangement that includes a Y decoder that selects a main bit line MBL to which sub bit lines SBL connected to memory cells MC are connected and selects main bit lines MBL adjacent to the selected main bit line MBL, and a YRST transistor that...

20060077751 - Latency control circuit and method of latency control: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the...

20060077749 - Memory card structure and manufacturing method thereof: A memory card structure comprising a substrate, a plurality of memory chips, some package material and an ultra-thin plastic shell is provided. To fabricate the memory card, a substrate having a first surface and a second surface is provided. The first surface has a plurality of outer contacts and the...

20060077750 - System and method for error detection in a redundant memory system: A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical...

20060077752 - Phase controlled high speed interfaces: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a...

  
04/06/2006 > 17 patent applications in 14 patent subcategories. category listing, related patent applications

20060072354 - Information processing device and method, recording medium, and program: To make it possible to reserve recording of a program without imposing a large load on a user. A server 2-1 transmits program attribute information to a video recording and reproducing apparatus 11 via a network 1. The program attribute information is constituted by program attribute names and program attribute...

20060072355 - Electrostatic capacitance detection device and smart card: An electrostatic capacitance detection device for detecting electrostatic capacitance that changes in accordance with a distance from a target object to read surface contours of the target object, including electrostatic capacitance detection elements arranged in M rows and N columns, a power supply line supplying power to the electrostatic capacitance...

20060072356 - State-retentive mixed register file array: A storage cell having a storage circuit and a readout circuit may be used in power-saving environments, where the storage circuit may be maintained in an ultra-drowsy mode during power-saving periods while the readout circuit may be powered down during power-saving periods. A pull-down transistor may be incorporated into the...

20060072357 - Method of operating a programmable resistance memory array: A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include phase-change materials such as chalcogenides....

20060072359 - Semiconductor memory device and memory card: A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines...

20060072358 - Nonvolatile memory device controlling common source line for improving read characteristic: A non-volatile memory device capable of improving a read characteristic is disclosed. A non-volatile memory device includes memory blocks, each memory block having a plurality of word lines. A common source line is arranged to be shared by the memory blocks. A first transistor is connected to the common source...

20060072360 - Electrochemical lithography memory system and method: Electronic memory devices fabricated using nanolithography techniques enables rapid and reliable storage of data on a substrate. One such device includes a memory access head, which includes a conductive member and an insulative member. The conductive member includes a proximal conductive tip, a distal conductive tip, and a body portion....

20060072361 - Semiconductor memory device with adjustable i/o bandwidth: A semiconductor memory device with adjustable I/O bandwidth includes a plurality of data I/O buffers connected one by one to a plurality of I/O ports, a switch array including a plurality of switches for connecting the plurality of data I/O buffers to a plurality of sense amplifier arrays, and a...

20060072362 - Memory device and test method thereof: A memory device and a test method thereof enable verification of fail of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device comprises a plurality of bit line switches and a separation control unit. The bit line switches connect the...

20060072363 - High speed and high precision sensing for digital multilevel non-volatile memory system: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed...

20060072364 - Fuse circuit and semiconductor device using fuse circuit thereof: A fuse circuit according to the present invention uses an electrically writable fuse circuit and comprises a first fuse unit provided with a first electrically writable fuse, and a second fuse unit provided with a second electrically writable fuse, and the state of logical add of the states of the...

20060072365 - Electronic control device: An electronic control device includes: a microprocessor that operates using electricity supplied from a battery through a switch operated in conjunction with an ignition switch, and a main power circuit; a volatile memory for temporarily storing data to be updated, the memory being operated using electricity supplied through the main...

20060072366 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a...

20060072368 - High density memory card assembly: A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so...

20060072367 - Information management device: An information management device and method, an information processing device and method, a recording medium, and a program that allow the provision of optimum content to each individual user are provided. In a Pochara service server 9, a matching is executed between the feature information of music selection Pochara and...

20060072370 - Phase-changeable memory devices and methods of forming the same: A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the...

20060072369 - System and method for automatically saving memory contents of a data processing device on power failure: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to...

Previous industry: Electric power conversion systems
Next industry: Agitating


######

RSS FEED for 20141204: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.



Results in 0.8806 seconds

PATENT INFO