Static information storage and retrieval inventions 03/06

20060067097 - Binary and ternary non-volatile cam: A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller...

20060067098 - Content addressable memory cell including resistive memory elements: A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and...

20060067099 - One-time programmable (otp) memory devices enabling programming based on protected status and methods of operating same: A One-Time Programmable (OTP) memory device can include a first OTP memory cell enabled for programming responsive to protected status associated with a second OTP memory cell configured for programming prior to the first OTP memory cell. Related methods are also disclosed....

20060067101 - Memory: A memory capable of easily setting a reference potential and correctly determining data is provided. This memory comprises a ferroelectric capacitor holding data, and a driving line and a data line linked with the ferroelectric capacitor. The memory applies a voltage pulse to the ferroelectric capacitor through the driving line...

20060067102 - Non-volatile logic circuit and system lsi having the same: A non-volatile logic circuit according to the present invention is comprised of: a logic circuit block; and an input/output unit operable to input and output data between the logic circuit block and the input/output unit and between a data bus and the input/output unit, wherein the input/output unit has a...

20060067100 - Semiconductor storage device: A semiconductor storage device comprises first and second memory cells, each connected to the first pair of word line and bit line and a second pair of word line and bit line, a sense amplifier connected between the first and second bit lines, a first capacitor whose storage electrode being...

20060067104 - Complementary output resistive memory cell: A complementary resistive memory structure is provided comprising a common source electrode and a first electrode separated from the common source electrode by resistive memory material; and a second electrode adjacent to the first electrode and separated from the common source electrode by resistive memory material, along with accompanying circuitry...

20060067105 - Control of memory devices possessing variable resistance characteristics: Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant...

20060067103 - Resistive memory cell configuration and method for sensing resistance values: A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form...

20060067106 - Storage device and semiconductor device: A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and...

20060067107 - Integrated semiconductor memory: An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of...

20060067108 - Bitcell having a unity beta ratio: In one embodiment, the present invention includes a memory device formed of a latch device that includes a pair of pull-up transistors and a pair of pull-down transistors to store data, and a pair of wordline transistors coupled between a wordline and the latch device. The pull-down transistors and the...

20060067109 - Sram cell power reduction circuit: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would...

20060067110 - Sram cell with horizontal merged devices: A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory...

20060067111 - Magnetic storage cell, magnetic memory device and magnetic memory device manufacturing method: A magnetic storage cell being capable of stable writing and having little adverse influence on an adjacent magnetic storage cell, and a magnetic memory device using the magnetic storage cell, and its manufacturing method are provided. In the invention, a plurality of TMR devices (1a) (1b) each including a TMR...

20060067113 - Methods for fabricating a magnetic keeper for a memory device: An MRAM device comprising an array of MRAM elements, with each element having an MRAM bit influenced by a magnetic field from a current flowing through a conductor, also includes a magnetic keeper formed adjacent the conductor to advantageously alter the magnetic field. The magnetic keeper alters the magnetic field...

20060067112 - Resistive memory cell random access memory device and method of fabrication: A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split...

20060067114 - Storage apparatus and semiconductor apparatus: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application...

20060067116 - Low power consumption magnetic memory and magnetic information recording device: A highly integrated magnetic memory with low power consumption is provided. A first element portion which has a free layer, a first pinned layer formed in the film thickness direction of the free layer, and an insulation barrier layer formed between the free layer and the first pinned layer, and...

20060067115 - Mram with improved storage and read out characteristics: The object of designing a magneto resistive memory such that it is as resistant as possible to magnetic stray fields, offers a longest possible retention time of the information stored, and ensures a good read signal, which is achieved by the MRAM memory cells comprising a first ferromagnetic layer or...

20060067117 - Fuse memory cell comprising a diode, the diode serving as the fuse element: A memory cell is formed of a semiconductor junction diode interposed between conductors. The cell is programmed by rendering the memory cell very high-resistance, such that current no longer flows between the conductors on application of a read voltage. In this cell the diode behaves as a fuse. The semiconductor...

20060067119 - Integrated memory circuit arrangement: A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properties of the memory circuit...

20060067118 - Nonvolatile memory structure: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled...

20060067122 - Charge-trapping memory cell: The channel region is slightly elevated with respect to the source and drain regions to form steps in the semiconductor surface, which are covered by a dielectric memory layer sequence provided for charge-trapping, the memory layer sequence comprising a lower confinement layer, a memory layer and an upper confinement layer....

20060067123 - Serial flash semiconductor memory: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential...

20060067124 - Nonvolatile memory structure: The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled...

20060067128 - Flash memory: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period....

20060067126 - Floating-body memory cell write: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the...

20060067127 - Method of programming a monolithic three-dimensional memory: A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels...

20060067125 - Programming and erasing method for charge-trapping memory devices: A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to...

20060067120 - Method and circuit arrangement for reading from a flash/eeprom memory cell: The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with...

20060067121 - Variable current sinking for coarse/fine programming of non-volatile memory: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory...

20060067129 - Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead: The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually...

20060067130 - Nonvolatile memory devices including overlapped data sensing and verification and methods of verifying data in nonvolatile memory devices: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a...

20060067131 - Non-volatile memory device and program method thereof: A non-volatile memory device and a program method thereof are provided. Data is scanned to search data bits to be practically programmed. The searched data bits are simultaneously programmed as many times as a predetermined number. Since data scanning and programming are conducted using a pipeline processing, an average time...

20060067132 - Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device: In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level...

20060067133 - Apparatus and method for a one-phase write to a one-transistor memory cell array: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of...

20060067134 - Dynamic multi-vcc scheme for sram cell stability control: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing...

20060067135 - Semiconductor memory device and method for testing same: A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuit 21 which forcefully controls the logic of write data into memory cells...

20060067136 - Low leakage and leakage tolerant stack free multi-ported register file: A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode,...

20060067139 - Memory: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected...

20060067137 - Semiconductor device and method of forming a semiconductor device: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in...

20060067138 - Semiconductor memory device having memory cells to store cell data and reference data: A semiconductor memory device includes a memory cell array, a sense amplifier, and a voltage generator. The memory cell array has a plurality of memory cells. Each of the memory cells is written with “0” or “1” as reference data after “0” or “1” as cell data has been read...

20060067140 - Maximum swing thin oxide levelshifter: An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The second transistor pair may be (i) implemented as thick...

20060067141 - Integrated circuit buffer device: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The...

20060067142 - Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device: A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address...

20060067143 - Array substrate and method of manufacturing the same: According to an embodiment of the invention, an array substrate includes a first test line, a second test line, a first source line group, a second source line group, a plurality of gate lines and a switching device. The first test line extends along a first direction. The second test...

20060067144 - Memory array with precharge control circuit: In one embodiment, a memory apparatus is provided with at least one local bit-line; a precharge control circuit, coupled to the at least one local bit-line, and adapted to be operable to initiate a precharge pulse after the at least one local bit-line is discharged and to terminate the precharge...

20060067145 - Semiconductor memory device: There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor...

20060067146 - Integrated circuit memory system having dynamic memory bank count and page size: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense...

20060067147 - Arrangement and method for reading from resistance memory cells: A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage...

20060067148 - Semiconductor device and data write method: A semiconductor device is provided that can perform simultaneous writing of a large number of bits, without an increase in chip size. This semiconductor device includes: a write data bus via which data are written into memory cells; a read data bus via which the data are read from the...

20060067149 - Semiconductor memory: A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second...

20060067151 - Memory: A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a...

20060067150 - Method and apparatus to control a power consumption of a memory device: In one embodiment, a method is provided. The method comprises upon entering a self-refresh mode, refreshing memory cells in a memory device at a first refresh frequency; and upon a predefined event refreshing the memory cells at a second refresh frequency, while in the self-refresh mode....

20060067152 - Crosspoint memory array utilizing one time programmable antifuse cells: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed....

20060067153 - Memory arrangement: A memory arrangement including a memory array, which has at least one memory block with a power supply device which can be activated, an address decoder, which is coupled to the at least one memory block in order to control access to the at least one memory block, and an...

20060067154 - Biasing circuit for use in a non-volatile memory device: A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to...

20060067158 - Integrated circuit memory device supporting an n bit prefetch scheme and a 2n burst length: The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme....

20060067155 - Latency normalization by balancing early and late clocks: A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal....

20060067156 - Memory device, memory controller and memory system having bidirectional clock lines: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and...

20060067157 - Memory system with two clock lines and a memory device: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a...

20060056214 - Memory module with reduced input clock skew: A memory module capable of exhibiting reduced input clock skew. More particularly, an unbuffered memory module that comprises a substrate, multiple memory components mounted to the substrate, and input/output and address and command bus connectors that transmit digital information to and from the memory components further includes a phase lock...

20060056215 - Method for increasing frequency yield of memory chips through on-chip or on-module termination: A memory module adapted for installation in an open memory socket on a mainboard of a computer. The memory module includes a substrate with an edge connector comprising pins along an edge of the substrate, and at least one memory package mounted to the substrate and containing a memory die...

20060056217 - Magnetic memory device: A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass...

20060056219 - Method for designing semiconductor device and semiconductor device: A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose...

20060056216 - Multi-chip card: A portable object (1) of the smart card type comprises a main circuit (3, 8, 9, 10) for internal processing and storage of data. The main circuit comprises several integrated circuits (3, 10). The portable object comprises a supply voltage circuit (7) for applying a first supply voltage (3 to...

20060056218 - Semiconductor memory devices and signal line arrangements and related methods: A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected...

20060056220 - Sram memory cell protected against current or voltage spikes: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage...

20060056221 - Readout circuit, solid state image pickup device using the same circuit, and camera system using the same: The present invention is mainly aimed at obtaining excellent sensor output free from periodic fixed pattern noise even if the pieces of holding capacity are converted into blocks, and the specific solution unit is described below. The signal readout unit includes: a line memory; first switches each connected to a...

20060056222 - One-time programmable memory devices: The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground...

20060056225 - Ferroelectric memory device: The present invention is provided with an MFSFET 100 having a ferroelectric thin film at its gate portion, word line 104, bit line 105, and bit line 106 so as to apply voltage equal to or higher than the coercive electric field of the ferroelectric thin film between the bit...

20060056224 - Ferromagnetic random access memory: A ferromagnetic random access memory includes a first and second blocks. Each of the first and second blocks includes a switch transistor and memory cells connected in series between a first and second end. The memory cell includes a ferromagnetic capacitor and a cell transistor connected in parallel. A first...

20060056223 - Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference: An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of...

20060056226 - Over-driven access method and device for ferroelectric memory: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using...

20060056227 - One time programmable phase change memory: A one time programmable phase change memory may include an array of phase change memory cells. Because the array is one time programmable, users may provide the manufacturer with code to be pre-programmed into the array. The memory may be programmed, for example, by fusing one or more cells to...

20060056228 - Transistor, memory cell array and method of manufacturing a transistor: A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions,...

20060056230 - Implementation of a multivibrator protected against current or voltage spikes: A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and...

20060056229 - Semiconductor integrated circuite device: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit...

20060056231 - Multivibrator protected against current or voltage spikes: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells,...

20060056232 - Magnetic memory and manufacturing method thereof: A magnetic memory capable of reducing diffusion of ferromagnetic material into semiconductor element area is provided. A magnetic memory 1 includes plural memory areas 3 disposed in two-dimension of m rows and n columns (m, n are integers of 2 or more). The magnetic memory 1 includes semiconductor layer 6...

20060056235 - Electrical memory component and a method of construction thereof: An electrical memory component is provided, comprising read/write probes and a chalcogenide storage media. Each read/write probe is adapted for selective electrical connection to a memory portion of the chalcogenide storage media and for performing read and write operations upon the memory portion. The chalcogenide storage media has a second...

20060056233 - Using a phase change memory as a replacement for a buffered flash memory: A phase change memory may be utilized to replace NAND flash memory in combination with a buffer such as a static random access memory and/or a dynamic random access memory. Because the phase change memory may have sufficiently low cost, it may replace low cost NAND flash and because the...

20060056234 - Using a phase change memory as a shadow ram: A processor-based system may use a volatile memory with a shadow phase change memory. The shadow phase change memory may be directly coupled to the controller. The controller may also be coupled to the volatile memory which, in turn, may, in some embodiments, be directly coupled to the phase change...

20060056236 - Thin film magnetic memory device having a highly integrated memory array: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As...

20060056237 - Non-volatile memory device with scanning circuit and method: I describe and claim an accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device comprises a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a...

20060056238 - Flash memory devices having a voltage trimming circuit and methods of operating the same: A flash memory device includes a trimming circuit that is configured to generate a plurality of identification voltages associated with a plurality of memory cell threshold voltage states, respectively, and to trim the plurality of identification voltages responsive to trimming information....

20060056239 - Method for programming memory cells including transconductance degradation detection: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises...

20060056240 - Method, circuit and system for erasing one or more non-volatile memory cells: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or...

20060056241 - Artificial aging of chips with memories: An apparatus for aging a chip, comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell; an access circuit for accessing the first memory cell via the first bit line and for accessing the second memory cell via the...

20060056242 - Communication system: A communication system that can improve communication quality by accurately re-creating reproduction timing at the receiving end even at the time of receiving VBR data or in the case of the occurrence of a packet loss. A send rate recognition section recognizes a send rate from a time stamp. A...

20060056243 - Reduction of fusible links and associated circuitry on memory dies: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values...

20060056244 - Memory systems with variable delays for write data signals: Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also referred to as a write data valid signal or...

20060056245 - Method for generating a cue delay circuit: A method for generating a delayed cue signal begins by receiving a tachometer input and writing a cue signal to a write address into a memory element that includes a read address. A memory output signal is read from the read address and a delayed cue signal is created from...

20060056247 - Memory device: First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic...

20060056246 - Semiconductor memory device outputting identifying and roll call information: A semiconductor memory device has an information storing circuit such as a fuse box as well as a memory cell array with redundant memory cells that can be used to replace defective memory cells. Address information indicating which memory cells have been replaced is stored in the information storing circuit,...

20060056248 - Multi-chip semiconductor packages and methods of operating the same: Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips includes a high voltage generator configured to receive an input voltage through the common input/output pad and generate...

20060056249 - Semiconductor memory storage device and its control method: A redundancy judge circuit (3) includes a redundancy judge circuit address+1 controller (30), an even-numbered redundant address judge section (31), an odd-numbered redundancy judge section (32), a redundant address ROM (33), a redundant IOROM (34), and a select section (35). The redundancy judge circuit (3) may also include a memory...

20060056250 - Magnetic memory, and its operating method: A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the...

20060056251 - Using a phase change memory as a replacement for a dynamic random access memory: A phase change memory may be utilized in place of a dynamic random access memory in a processor-based system. The memory may keep track of the number of read or write cycles so that it may determine when a refresh cycle will occur. During the refresh cycle, the phase change...

20060056253 - Dram circuit and its operation method: A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) is arranged between cell areas. Specifically, arrays are...

20060056252 - Memory device having open bit line cell structure using burn-in testing scheme and method therefor: A memory device having an open bit line cell structure uses a wafer burn-in testing scheme and a method for testing the same. The memory device includes a sense amplifier having first and second input terminals; a bit line connected to the first input terminal of the sense amplifier and...

20060056254 - Electric circuit for providing a selection signal: An electric circuit for providing a selection signal being used to select a control value of a control variable which oscillates, at steady state, about a reference value about a first control value and a second control value with a first period duration comprises a first differential circuit which provides...

20060056259 - Memory controller method and system compensating for memory cell data losses: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from...

20060056260 - Memory controller method and system compensating for memory cell data losses: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from...

20060056257 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a logic circuit and a plurality of semiconductor memory devices formed on a semiconductor substrate, and a refresh control circuit for controlling the semiconductor device. The refresh control circuit controls a refresh control signal and a clock signal input to a plurality of memories in...

20060056258 - Semiconductor memory and method for operating the same: A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects an error for each read data string, and sets the most reliable result of the...

20060056255 - Semiconductor memory apparatus and method for operating a semiconductor memory apparatus: The invention relates to a semiconductor memory apparatus and a method for operating a semiconductor memory apparatus which can be operated in a normal operating mode and in a self-refresh mode. The method comprises the following steps in the self-refresh mode: determining the operating temperature of the semiconductor memory apparatus;...

20060056256 - Semiconductor memory device and test method therefor: Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first...

20060056261 - Method for producing an extended memory array and apparatus: The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with...

20060056263 - Semiconductor memory device and electronic apparatus: A semiconductor memory device includes a plurality of banks including memory cell arrays in which dynamic type memory cells are arranged in a matrix, according to an input address and an input control command in synchronization with a clock signal, the memory cell corresponding to the input address being accessed...

20060056262 - Serial memory comprising means for protecting an extended memory array during a write operation: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address...

20060056267 - Driving unit and display apparatus having the same: In a driving unit (e.g., a gate driving unit) and a flat panel display apparatus having the driving unit, a circuit portion of the driving unit includes a plurality of driving stages cascade-connected to one another and outputs a (gate) driver signal (a plurality of gate-driving signals) based on a...

20060056266 - Integrated semiconductor memory comprising at least one word line and method: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or...

20060056265 - Nonvolatile phase change memory device and biasing method therefor: A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row...

20060056264 - Variable boost voltage row driver circuit and method and memory device and system including same: A row driver circuit receives a supply voltage and operates to develop a boosted voltage having a magnitude that is equal to the sum of an incremental boost voltage and a magnitude of the supply voltage. The magnitude of the incremental boost voltage is a function of the magnitude of...

20060056268 - Address buffer circuit for memory device: Disclosed is an address buffer circuit for a memory device, the address buffer circuit comprising: a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the second address input buffer...

20060056269 - Timing generation circuit and semiconductor test device having the timing generation circuit: A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 for loading timing data output from the TMM and outputting a pulse...

20060050544 - Information recording method, reproducing method, and recording reproducing method utilizing holography: A method for recording information on a recording medium utilizing an interference pattern by interference between an information light modulated spatially with digital pattern information displayed on a spatial light modulator having multiple pixels and a reference light for recording. In order to provide a novel recording method capable of...

20060050549 - Electro-resistance element and electro-resistance memory using the same: A electro-resistance element with good heat treatment stability under a hydrogen-containing atmosphere and a electro-resistance memory with good resistance change characteristics and productivity are provided. The electro-resistance element has two or more states in which electric resistance values are different, and is switchable from one of the states selected from...

20060050545 - Integrated memory arrangement based on resistive memory cells and production method: An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases its capacitance, and to a production method....

20060050546 - Memory circuit having memory cells which have a resistance memory element: In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor...

20060050547 - Resistive memory arrangement: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular,...

20060050548 - Semiconductor memory device capable of compensating for leakage current: A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line...

20060050550 - High reliability triple redundant memory element with integrated testability and voting structures on each latch: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first,...

20060050551 - Memory array method and system: An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control, a shared switched voltage line that is capable of applying a voltage to the voltage divider inputs...

20060050552 - Method and apparatus for multi-plane mram: A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and...

20060050556 - Method and apparatus for operating charge trapping nonvolatile memory: A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts...

20060050554 - Method and apparatus for operating nonvolatile memory cells in a series arrangement: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of...

20060050555 - Method and apparatus for operating nonvolatile memory cells in a series arrangement: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of...

20060050553 - Method and apparatus for sensing in charge trapping non-volatile memory: A memory cell with a charge trapping structure is read by measuring current between the substrate region of the memory cell and one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the...

20060050557 - Nonvolatile semiconductor memory device: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select...

20060050558 - Semiconductor device and an integrated curcuit card: There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memory cells sharing a source, and disposed at symmetrical...

20060050559 - Nonvolatile semiconductor memory device: The nonvolatile semiconductor memory device of this invention has a trench region in a semiconductor substrate and has a NAND type memory cell unit in three dimensions in both sides of a side wall of one trench region, respectively. And these NAND memory cell units are connected to one bit...

20060050560 - Semiconductor memory device with reduced number of high-voltage transistors: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potential on the word lines and bit lines according to the input data. The control circuit further controls the operations of writing data...

20060050561 - Bitline governed approach for program control of non-volatile memory: In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage...

20060050562 - Non-volatile memory and method with improved sensing: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground...

20060050563 - Display device and driving method thereof: A display device includes gate lines transmitting a first gate-on voltage and a second gate-on voltage, data lines transmitting data voltages, pixels including switching elements and pixel electrodes, a gate driver electrically connected to the gate lines and sequentially applying the first and second gate-on voltages to the gate lines,...

20060050564 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged: a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored...

20060050565 - Method and apparatus for operating nonvolatile memory in a parallel arrangement: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of...

20060050566 - Semiconductor device: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to...

20060050567 - Using transfer bits during data transfer from non-volatile to volatile memories: Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient...

20060050568 - Programmable logic auto write-back: A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to a first load path. The load path couples to a latch ring, which receives configuration data from the first memory. An...

20060050569 - Semiconductor memory apparatus and activation signal generation method for sense amplifier: A semiconductor memory apparatus, comprising a cell array comprising a plurality of memory cells; a sense amplifier; and a self-timing unit comprising a plurality of dummy bit-lines, selecting the dummy bit-line based on the position of the memory cell of which a data is read out, and generating an activation...

20060050570 - Access circuit and method for allowing external test voltage to be applied to isolated wells: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one...

20060050571 - Transmitter of a semiconductor device: Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a control circuit. The pre-driver unit modifies a common mode level and...

20060050572 - Memory circuit with supply voltage flexibility and supply voltage adapted performance: The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means...

20060050574 - Memory device with column select being variably delayed: A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of...

20060050573 - Semiconductor memory devices and methods of delaying data sampling signal: According to the example embodiments of semiconductor memory devices and the methods of delaying a sample data signal of the present invention, the delay characteristics of the data sampling signal (FRT) are adjusted based on the location of the memory unit in a row direction and/or in a column direction...

20060050575 - Row decoder for nand memories: A row decoder for an electrically programmable NAND memory further includes a first means for keeping at least a control node of an addressed memory block charged at a select voltage. A second means decouples all select lines from a global select line. A third means provides an access voltage...

20060050578 - Decoder of semiconductor memory device: A column decoder in a semiconductor memory device in which address setting cannot be performed but only a serial access can be performed. The column decoder is constructed by: a redundant fuse for generating a redundant fuse signal; a column decoding circuit for decoding a column address; a column decoding...

20060050579 - High speed redundant data sensing method and apparatus: An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the second bit...

20060050577 - Memory module with programmable fuse element: The invention relates to a memory module for providing a storage capacity, comprising a printed circuit board, one or more memory components which are applied to the printed circuit board and which in each case have a regular memory area and a redundant memory area, a connecting interface for connecting...

20060050576 - Nand flash memory device and copyback program method for same: A NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently...

20060050580 - Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device: A semiconductor device including memory cells such as flip-flops, RAMs or SRAMs is powered on, and first logic signals of Hi or Lo output from the respective memory cells are obtained. A combination of the logic signals is used as a unique identification code for identifying a semiconductor device....

20060050582 - Method and apparatus for a sense amplifier: A gain stage in a sense amplifier receives an input signal representing a stored value and senses if the input signal is less than or not less than a reference signal and generates an output signal indicative of a first state when the input signal is less than the reference...

20060050583 - Semiconductor integrated circuit device: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to...

20060050581 - Sense amplifier circuits and high speed latch circuits using gated diodes: A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second...

20060050584 - Current sense amplifier: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled...

20060050585 - Device for setting up a write current in an mram type memory and memory comprising: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current...

20060050586 - Semiconductor memory device: A memory array, a sense amplifier circuit, a replica circuit and a dummy cell are disposed. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line....

20060050587 - Fully-hidden refresh dynamic random access memory: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the...

20060050588 - Semiconductor integrated circuit device: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem...

20060050590 - Logic device with reduced leakage current: A logic device operates with reduced leakage current. Controllability is achieved by using a reference voltage to control the amount of leakage reduction. A method of temperature dependent reference voltage generation is given which maintains virtual supply in acceptable range to provide sufficient noise margin in logic devices including memory...

20060050589 - Power voltage supplier of semiconductor memory device: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying...

20060050591 - Address coding method and address decoder for reducing sensing noise during refresh operation of memory device: An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in...

20060050592 - Compact module system and method: A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form...

20060050593 - Non-volatile memory device: A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of pages. Each page includes a plurality of non-volatile memory cells, a first region for storing data, and a second region for...

20060050594 - Flash memory device and method of erasing flash memory cell thereof: A flash memory device and method of erasing flash memory cells thereof are provided. The erase of a cell block unit or a page unit is effected by a word line switch included in a predecoder according to a page erase signal. If the erase is effected in the cell...

20060050597 - Active termination control through module register: A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module...

20060050596 - Dynamic monitoring of activation of g-protein coupled receptor (gpcr) and receptor tyrosine kinase (rtk) in living cells using real-time microelectronic cell sensing technology: The present application includes systems and methods for identifying a compound capable of interacting with a G-Protein Coupled Receptor (GPCR) or Receptor Tyrosine Kinase (RTK) including providing a device capable of measuring cell-substrate impedance operably connected to an impedance analyzer, adding test cells expressing a GPCR or a RTK to...

20060050595 - Semiconductor memory device with reduced leak current: A semiconductor memory device includes a memory cell array, a decoder circuit configured to assert a decoding signal for selecting an access position in the memory cell array in response to an address signal supplied from an exterior, and a first circuit configured to put the decoding signal of the...

20060050599 - Memory device and method for burn-in test: A memory device and a method for burn-in test are described. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line...

20060050598 - Memory using variable tunnel barrier widths: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory...

20060050602 - Apparatus and method for generating a variable-frequency clock: Apparatus and method for generating a variable-frequency clock is disclosed. A control state machine defines various commands and generates corresponding control signals. A variable-frequency clock generator then outputs the variable-frequency clock that has a specific pattern corresponding with the respective command, where the variable-frequency clock is constructed with a first...

20060050600 - Circuit for verifying the write speed of sram cells: A circuit for measuring the performance of a memory cell. The circuit includes a ring oscillator, which includes a plurality of memory cells. The performance of the memory cell can be determined from an oscillation frequency of the ring oscillator. The circuit accurately verifies the performance of the memory cell...

20060050603 - Parallel asynchronous propagation pipeline structure and methods to access multiple memory arrays: A method is disclosed to carry out a data access operation in a data memory device that is subdivided into a plurality of memory arrays each array includes a plurality of memory cells accessible by an identifiable address. The method includes a step of asynchronously propagating in parallel a plurality...

20060050601 - Semiconductor memory device: A semiconductor memory device processes external commands in parallel using divided clocks, which embodies a high-speed operation of a DRAM in increase of clock frequency. In the semiconductor memory device, command processing blocks are separated into row and column paths in parallel, and the command processing blocks connected in parallel...

20060044860 - Memory stacking system and method: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the...

20060044861 - System and method using a one-time programmable memory cell: A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element comprises a thin gate-oxide that acts as a resistance element, which, depending on whether...

20060044862 - Photon-based memory device: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel....

20060044863 - One-transistor composite-gate memory: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more...

20060044864 - Structure of ac light-emitting diode dies: A structure of light-emitting diode (LED) dies having an AC loop (a structure of AC LED dies), which is formed with at least one unit of AC LED micro-dies disposed on a chip. The unit of AC LED micro-dies comprises two LED micro-dies arranged in mutually reverse orientations and connected...

20060044866 - Semiconductor device: The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines for reading data from the memory circuits, second signal lines for...

20060044865 - Semiconductor storage device: A semiconductor storage device includes first and second additional FETs disposed in parallel on one of potential lines for supplying first and second drive potentials to each SRAM memory cell. When each memory cell is selected, a selection signal is supplied to the gate terminal of the first additional FET...

20060044867 - Magnetic resistance memory and method of writing data: A magnetic resistance memory includes an identity determining unit that compares, bit by bit, first data stored in an address specified by a write request with second data to be written to the address, and that determines whether bit-by-bit values of the first data and the second data are identical;...

20060044868 - Apparatus and methods for storing data in a magnetic random access memory (mram): An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments...

20060044869 - Data write circuit and data write method for semiconductor storage device: A data write circuit of a semiconductor storage device is provided in which a multi-bit write method can be employed even if data input takes a long time. The data write circuit includes a multi-bit decoder and data latch circuit for sequentially latching a plurality of data to be respectively...

20060044870 - Integrated dram-nvram multi-level memory: An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory...

20060044871 - Semiconductor integrated circuit: The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which...

20060044872 - Nand flash depletion cell structure: NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rdS resistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings....

20060044873 - Semiconductor device and a method of manufacturing the same: A semiconductor device including an SOI substrate and a MONOS type nonvolatile memory cell with a first drain composed of an n+ type diffusion region and a second drain composed of a p+ type diffusion region, wherein the first and second drains are arranged in different planar locations in a...

20060044874 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation...

20060044875 - Method and unit for verifying initial state of non-volatile memory device: A method of verifying an initial state of a non-volatile memory device, a command for verify an initial state of a unit and a unit address corresponding to the unit received from a memory controller. An initial state of memory cells, which correspond to the unit address, is verified in...

20060044876 - Programming and manufacturing method for split gate memory cell: A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is provided. The split gate memory cell has two bitlines of a second conductive type, e.g., n-type, a select...

20060044877 - Non-volatile memory device, and control method therefor: During an erase operation, lower decoder groups 20(i) and 21(i) (i=1 to m) of erase-target sectors are connected, at their respective low voltage power supply terminals (VL), to a first negative voltage supply line (VM) via switches (B) (50 and 51, respectively) and a negative bias voltage is supplied to...

20060044878 - Programming of programmable resistive memory devices: Programming of a programmable resistive memory device includes supplying programming power to the device; generating feedback as to when the device has been programmed; and removing the programming power when the feedback indicates that the device has been programmed....

20060044880 - Multiple-level data compression read more for memory testing: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be...

20060044879 - Semiconductor memory device: A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask...

20060044881 - Unified multilevel cell memory: A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast...

20060044882 - Circuit and method for current pulse compensation: A circuit and method of operation compensates for current pulses on a regulated voltage of a voltage supply. The regulated voltage supply is coupled to a plurality of loads that are enabled by a first set of control signals. The enable loads place current pulses having a predetermined plurality on...

20060044883 - Low supply voltage temperature compensated reference voltage generator and method: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with...

20060044884 - Semiconductor device capable of generating ripple-free voltage internally: A semiconductor device that generates a regulated high voltage. The device includes, a high voltage generation circuit for supplying a high voltage to the first power line, a current bypass circuit for supplying current to a second power line from the first power line, a PMOS transistor coupled between a...

20060044886 - Semiconductor storage device and electronic equipment: Characteristic fluctuation of a reference cell due to read disturb is prevented. A memory cell 27m and a reference cell 27r respectively have memory function bodies that are formed on both sides of a gate electrode and have a function to retain electric charge or polarization. The memory cell 27m...

20060044885 - System and method for preserving an error margin for a non-volatile memory: A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to...

20060044889 - Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same: There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La...

20060044888 - Level shifter for low voltage operation: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent...

20060044887 - Power efficient memory and cards: A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard device as...

20060044890 - Semiconductor storage apparatus: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: a cell array including a plurality of memory cells, each being connected to bit lines and word lines arranged in a row direction and a column direction; and a sense amplifier which controls read-out of data stored...

20060044891 - Memory system and method for strobing data, command and address signals: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe...

20060044892 - Method for detecting data strobe signal: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the...

20060044893 -