Static information storage and retrieval inventions 01/06

20060018141 - Apparatus and method for power savings in high-performance cam structures: This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or portions of the compare data inputs vary infrequently. The apparatus sometimes may be referred to as local match line...

20060018142 - Concurrent searching of different tables within a content addressable memory: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM...

20060018143 - Logical arrangement of memory arrays: An aspect of the present invention is a logical arrangement of memory arrays. The logical arrangement includes a plurality of memory arrays deposed in a row-column configuration, a controller coupled to the plurality of memory arrays and at least one power line, at least one sense line and at least...

20060018144 - Ferroelectric memory: An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through...

20060018145 - Semiconductor device that initializes memory cells of an activated wordline group: A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value during an initial value setting operation; a first power supply...

20060018147 - Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (pmosfet) sram cells: Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of the first PMOSFET is connected to a drain of the second PMOSFET at a first...

20060018146 - Power management circuit and memory cell: A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at...

20060018150 - Antiferromagnetically stabilized pseudo spin valve for memory applications: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of...

20060018151 - Ferroelectric memory device and its driving method: A ferroelectric memory device equipped with a plurality of memory cells and a control section that stores memory data indicated by a data signal when a write control signal changes from a first logical value to a second logical value, the ferroelectric memory device wherein, when the write control signal...

20060018148 - Method and device to detect the likely onset of thermal relaxation in magnetic data storage devices: Reference magnetic elements or bits with a range of magnetic volumes smaller than the minimum size used for actual data storage are written or patterned in the data storage device. The reference elements or bits have dimensions such that their magnetization will relax in a shorter time than that of...

20060018149 - Two terminal memory array having reference cells: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a...

20060018153 - Operating array cells with matched reference cells: A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to...

20060018152 - Semiconductor memory device and electric device with the same: A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, each memory cell storing one of first, second, third and fourth data defined as being arranged in order of threshold voltage height; a read/write circuit configured to read data of and write...

20060018154 - Partial permanent write protection of a memory card and partially permanently write protected memory card: This invention relates to a method permanently write protecting a portion of a memory card. According to the invention a bit indicating permanent write protection or permanent write protection of a portion of the memory card is set in the specific data register of the memory card to indicate that...

20060018155 - Flash memory devices having power level detection circuits: Flash memory devices are provided including a power supply pad unit. The power supply pad unit includes a first power supply pad, a second power supply pad and a power level detection circuit. The first power and second power supply pads are electrically coupled to the power level detection circuit....

20060018156 - Memory device with thermal insulating layers: A memory device is described an active material configured to be placed in amore or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity....

20060018157 - Semiconductor memory device: A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is...

20060018158 - Memory devices and programming methods that simultaneously store and erase status indications for memory blocks: Methods are provided to program a memory device having a plurality of memory blocks. A first address for selecting a row of each of the memory blocks is generated according to a multi-page program operation. A second address for selecting a memory block is received and latched, which is repeated...

20060018159 - Programmable nand memory: An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and each memory block including a plurality of memory pages; means for receiving an address corresponding to a respective memory block;...

20060018160 - Non-volatile system with program time control: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the...

20060018162 - Semiconductor memory device and method of controlling write sequence thereof: A semiconductor memory device includes: a memory cell array having a plurality of word lines and a plurality of bit lines, which cross each other, and electrically rewritable and non-volatile memory cells disposed at crossings thereof; a read/write circuit configured to write data into a selected memory cell with applying...

20060018161 - Single poly non-volatile memory: An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the...

20060018164 - Nor-type channel-program channel-erase contactless flash memory on soi: A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The...

20060018163 - Selective erase method for flash memory: Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At...

20060018165 - Digital ram memory circuit with an expanded command structure: The subject matter of the invention is a digital memory circuit having a multiplicity of memory cells, address terminals for applying address information for addressing respectively selected memory cells, data terminals for inputting and outputting the memory data which is to be written into, or has been read out at...

20060018166 - Method and managing bad memory blocks in a nonvolatile memory device, and nonvolatile-memory device implementing the management method: A method for managing bad memory blocks of a nonvolatile-memory device, in which the available memory blocks are divided into a first set, formed by addressable memory blocks that are to be used by a user, and a second set, formed by spare memory blocks that are to replace bad...

20060018167 - Flash memory device capable of reducing test time and test method thereof: A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and...

20060018168 - Semiconductor memory device and method of precharging global input/output lines thereof: There are provided a semiconductor memory device and a method of precharging global input/output (I/O) lines thereof, for reducing power consumption during a precharge operation. The semiconductor memory device includes a pair of first global I/O lines; a pair of second global I/O lines; a first precharge circuit for precharging...

20060018169 - Dynamical biasing of memory sense amplifiers: A circuit and a method are given, to realize a dynamical biasing of memory sense amplifiers for Sense Electronics Endowed (SEE) memory devices. Fast memories uses sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to...

20060018170 - Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system: A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a...

20060018171 - Memory system having fast and slow data reading mechanisms: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from...

20060018172 - Semiconductor integrated circuit device: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface...

20060018175 - Electrical via connection and associated contact means as well as a method for their manufacture: An electrical via connection and associated contact means in an organic electronic circuit, particularly a memory circuit is provided interfacing a layer of active organic dielectric material comprising various organic compounds. The via connection is provided in a via opening extending through the active dielectric material and connected with first...

20060018173 - Method for using non-volatile memory and electronics device thereof: A method for using non-volatile memory and an electronics device thereof is provided. The method includes the following steps. First, a non-volatile memory pre-loaded with a plurality of original data is provided. When updating the original data with new data, if free space is available in the non-volatile memory, then...

20060018174 - Semiconductor memory device performing auto refresh in the self refresh mode: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a...

20060018176 - Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system: In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the...

20060018177 - Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write)...

20060018178 - Circuit of sdram and method for data communication: A data communication circuit of a SDRAM for data communication comprises a plurality of data lines coupled to a plurality of data pins. The number of the data lines, according to an embodiment of the present invention, is less than the number of the data pins. When the data communication...

20060018179 - Cost-aware design-time/run-time memory management methods and apparatus: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical...

20060018180 - Nonvolatile semiconductor memory with x8/x16 operation mode using address control: The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality...

20060018181 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in...

20060018183 - Content addressable memory cell: A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content...

20060018182 - Solid state microoptoelectromechanical system (moens) for reading photonics diffractive memory: The present invention comprises a solid-state system for reading information from a photonics diffractive memory. An acousto-optic deflector directs a convergent light beam onto a micr-mirror array which then reflects the light beam onto the photonics diffractive memory at a predetermined point and angle so as to access a packet...

20060018184 - Source controlled operation of non-volatile memories: Non-volatile memory such as flash EEPROM has memory cells that may be programmed in parallel using a self-limiting programming technique. Individual cells have charge storage units that may be charged by hot electrons in a self-limiting manner. As the charge storage unit reaches the required level of charge, hot electrons...

20060018185 - Memory control apparatus and electronic apparatus: In order to control a synchronous memory, a synchronous signal is required. In most cases, a clock signal is used for this purpose. This approach has room for improvement in power consumption etc. A synchronous signal generating circuit 22 generates a synchronous signal for a synchronous memory from an asynchronous...

20060013028 - High-speed and low-power differential non-volatile content addressable memory cell and array: A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal,...

20060013029 - Low cost high density rectifier matrix memory: The present invention is a means for constructing a high density memory device for very low cost by fabricating the device three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the...

20060013031 - Assay systems with adjustable fluid communication: Systems, including apparatus and methods, for performing assays with adjustable fluid communication between samples....

20060013030 - Refresh-free dynamic semiconductor memory device: In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into...

20060013032 - Nonvolatile semiconductor storage device: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a...

20060013033 - Ferroelectric memory device and electronic apparatus: A ferroelectric memory device equipped with: a voltage source for generating a predetermined voltage; a first ferroelectric capacitor having one end electrically connected to a first bit line; a first resistance having a first resistance value, provided between the first bit line and the voltage source; a second ferroelectric capacitor...

20060013034 - Die customization using programmable resistance memory elements: A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display....

20060013035 - Low-noise leakage-tolerant register file technique: A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the...

20060013036 - Semiconductor device: In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is to be made gentler, whereby reduced power source noise and low...

20060013037 - Read/write circuit for accessing chalcogenide non-volatile memory cells: A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element...

20060013038 - Adaptive algorithm for mram manufacturing: Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read only memory (EEPROM), FLASH EEPROM or one-time-programmable (OTP) EPROM. Due to the randomness of manufacturing process, the magnetic tunnel junctions (MTJ) in...

20060013040 - Adjusting the frequency of an oscillator for use in a resistive sense amp: A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed through logic gates to determine whether the sensing output contains a predetermined string of logic ones or zeroes. If a string of ones is...

20060013039 - Read out scheme for several bits in a single mram soft layer: A magnetic tunnel junction (MTJ) device is configured to store at least two bits of data in a single cell utilizing the variable resistance characteristic of a MTJ. The MTJ includes a soft and two fixed magnetic layers with fixed field directions oriented in perpendicular directions. The soft magnetic layer...

20060013041 - Nonvolatile memory structure with high speed high bandwidth and low voltage: The invention is directed to a via-mask read only memory (ROM) layout structure, including a dynamic random access memory (DRAM) like layout structure, serving as a main body structure and having an array of coding transistors. A grounding structure line is disposed over the source regions of the coding transistors....

20060013042 - In-service reconfigurable dram and flash memory device: A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of...

20060013043 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device is provided comprising a plurality of memory cell arrays, each of which consists mainly of sidewall type memory cells arranged in a matrix, the memory cell having a MOSFET structure where memory functional element for holding charges are provided on both sides of a gate...

20060013044 - Programmable soft-start control for charge pump: A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an integrated circuit. The two memory registers are programmed to provide two different soft-start settings for two distinct charge pump turn-on conditions, initial power-up and flash programming....

20060013046 - Integrated circuit apparatus having improved test circuit and method of testing the integrated circuit apparatus: An integrated circuit apparatus including an improved test circuit and a method of testing the integrated circuit apparatus are provided. The integrated circuit apparatus determines pass or fail of the integrated circuit apparatus itself by comparing internal DQ data output by a core logic circuit with test patterns set by...

20060013045 - Page buffer of non-volatile memory device and method of programming and reading non-volatile memory device: A page buffer of a non-volatile memory device and a method for programming and reading the same is provided. The page buffer includes a first latch unit and one or more second latch units for storing data, transfer units connected between the first latch unit and the second latch units...

20060013047 - Charge pump circuit: A charge pump circuit is provided which outputs a high voltage by using a boosting circuit with a smaller number of stages. A diode is used to give a back-gate voltage for a MOS transistor composing the charge pump circuit, thereby minimizing a reduction in a boosted voltage due to...

20060013048 - Memory systems including defective block management and related methods: A memory system may include a plurality of non-volatile memory cells and a memory controller coupled to the plurality of non-volatile memory cells. The plurality of non-volatile memory cells may be arranged in blocks with each block including a plurality of pages of non-volatile memory cells. Moreover, the plurality of...

20060013049 - Semiconductor memory device with small number of repair signal transmission lines: In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select...

20060013050 - Magnetic memory device having a plurality of magneto-resistance effect elements arranged in a matrix form and method for manufacturing the same: A magnetic memory device comprises a plurality of magneto-resistance effect elements arranged in a matrix form. The each of a plurality of magneto-resistance effect elements have a pattern shape which substantially internally touches an ellipse having major and minor axes of the magneto-resistance effect element as major and minor axes...

20060013051 - Local sense amplifier in memory device: A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first...

20060013054 - Dram with hidden refresh: A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh operations on a periodic basis while avoiding collisions...

20060013052 - Method and system for controlling refresh to avoid memory cell data losses: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in...

20060013053 - Semiconductor memory device for performing refresh operation: A semiconductor memory device comprises a sensing control unit, a separation control unit and a sense amplifier enable unit. The sensing control unit outputs a plurality of mat enable signals in response to a mat selecting signal, a clock enable signal, a refresh signal and a test mode signal. The...

20060013055 - Adaptive power managing device and method: An adaptive power managing device for an IC chip or a circuit system comprises a tunable voltage generator, a data generator, a data processing unit, a data checking unit and a control unit; the tunable voltage generator is used for providing the IC chip or the circuit system with an...

20060013056 - Memory architecture: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between...

20060013058 - Phase change memory device for use in a burst read operation and a data reading method thereof: A phase change memory device for use in a burst read operation and a data reading method are provided. The memory device includes a plurality of bit lines and a plurality of word lines. A memory cell array block has a plurality of phase change memory cells that are connected...

20060013057 - Semiconductor memory device including circuit to store access data: We describe a semiconductor memory device including a memory cell array and a storage device to store access data. The memory cell array is accessed responsive to the access data. The memory cell array access is determined by the access data stored in the storage device. The memory cell array...

20060013059 - System for placing elements of semiconductor integrated circuit, method of placing elements thereon, and program for placing elements: An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information necessary to execute routing, a placement improvement library that stores specified element information...

20060013060 - Write address synchronization useful for a ddr prefetch sdram: Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the...

20060007722 - Operating temperature optimization in a ferroelectric or electret memory: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power...

20060007723 - Electro-optical device, signal processing circuit thereof, signal processing method thereof and electronic apparatus: An electro-optical device includes a plurality of scanning lines that extends in a row direction, a plurality of data lines that extends in a column direction, a plurality of pixels which are provided at intersections of the scanning lines and the data lines and whose gray-scale levels are designated by...

20060007724 - Double-cell memory device: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the...

20060007725 - Ferroelectric memory device, electronic device: A ferroelectric memory device including a pair of main bit lines (MBLU1, MBLL1) having generally identical line width and line length, a sense amplifier (SA) that lies between one of the main bit lines and the other of the main bit lines, a plurality of local bit lines (LBLU1, etc.)...

20060007726 - Voltage buffer for capacitive loads: A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level...

20060007727 - Memory cell: A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging/discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates a memory transistor that can be implemented in either silicon...

20060007728 - Nonvolatile memory vertical ring bit and write-read structure: A magnetoresistive memory cell and array are provided for nonvolatile storage of binary information. According to an embodiment, a memory cell has a ring-shaped magnetoresistive multilayer element (or bit). A plurality of vias pass through a center hole in the ring-shaped element. Each end of each via is coupled with...

20060007729 - Phase change memories and/or methods of programming phase change memories using sequential reset control: Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits...

20060007730 - Magnetic cell and magnetic memory: A magnetic cell comprises: a first ferromagnetic layer whose magnetization is substantially fixed in a first direction; a second ferromagnetic layer whose magnetization is substantially fixed in a second direction opposite to the first direction; a third ferromagnetic layer provided between the first and the second ferromagnetic layers, a direction...

20060007731 - Database query tools: A system that facilitates one or more of querying and updating a multi-dimensional structure comprises a component that receives a statement in a declarative language relating to a typed object associated with a multi-dimensional structure. A conversion component analyzes context associated with the statement and automatically converts the object to...

20060007733 - Semiconductor device having switch circuit to supply voltage: A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell...

20060007736 - Method and system for programming and inhibiting multi-level, non-volatile memory cells: A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed....

20060007737 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is...

20060007738 - Area management type memory system, area management type memory unit and area management type memory controller: In a storage medium which has a number of areas, access to any area is controlled in accordance with whether or not access to another area is possible, and thereby, destruction of data due to malfunctioning or a wrong operation is prevented. A link control part which controls access to...

20060007739 - Semiconductor device and test method thereof: Data read out from each memory cell in a memory cell array is compared with an expected value by a comparator, and the quality of a memory cell is determined by performing program verify and erase verify. Based on the comparison result of the comparator, a detected defective cell is...

20060007732 - Charge trapping non-volatile memory and method for operating same: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor...

20060007740 - Non-volatile memory device: A non-volatile memory device includes: a first memory cell array having memory cells, in which one bit data is stored by a plurality of memory cells concurrently; and a second memory cell array having memory cells, in which one bit data is stored by a single memory cell. The device...

20060007742 - Charge trapping non-volatile memory and method for gate-by-gate erase for same: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor...

20060007741 - Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same: A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct...

20060007743 - Flash memory: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period....

20060007744 - Flash memory: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period....

20060007745 - Two-bit charge trap nonvolatile memory device and methods of operating and fabricating the same: Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word lines crossing over the device isolation layers, and a multiple insulation layer intervened between the word line and the active region. The...

20060007747 - Flash memory: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period....

20060007750 - Flash memory: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period....

20060007748 - Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity....

20060007746 - Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity....

20060007749 - Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices: Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity....

20060007751 - Nonvolatile semiconductor memory: A block comprises physical addresses 0, 1, 2, 3. In an initial state, all the physical addresses 0, 1, 2, 3, are in an erase state. When data LA0, LA1, LA2, LA3 are written in the physical addresses 0, 1, 2, 3, count values are “1”, respectively. In this manner,...

20060007735 - Memory array including multiple-gate charge trapping non-volatile cells: An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping...

20060007734 - System and method for over erase reduction of nitride read only memory: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase...

20060007752 - Method of improving erase voltage distribution for a flash memory array having dummy wordlines: Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage...

20060007753 - Isolation control circuit and method for a memory device: A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation...

20060007754 - Memory systems and methods: Systems and methods are disclosed for memory, including techniques for reading and writing to memory. For example, in accordance with an embodiment of the present invention, a method of implementing a read and a write operation (e.g., a read before write operation) is disclosed for a memory, such as for...

20060007755 - Nonvolatile memory device efficiently changing functions of field programmable gate array at high speed: A switch section for changing the function of an FPGA is provided with a data latch circuit used for connection control. The data latch circuit includes program sections in which program data is stored in advance, and latch unit. At the time of changing the function, control signals are selectively...

20060007756 - Semiconductor memory device and control method for semiconductor memory device: Provided is a semiconductor memory device using a single-bit line method that determines read operation timing in accordance with operation of a replica bit line. Further provided is a control method for the semiconductor memory device. Even when a transistor property fluctuation has occurred, the semiconductor memory device and the...

20060007758 - Method and apparatus for setting cas latency and frequency of heterogenous memories: A method and apparatus for setting column address strobe (CAS) latency and frequency for heterogeneous memories are provided. The method includes obtaining setting information related to CAS latencies and frequencies supported by two or more memories, and comparing the CAS latencies supported by the memories with one another and setting...

20060007757 - Solution to dqs postamble ringing problem in memory chips: The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the...

20060007759 - Alignment of memory read data and clocking: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows...

20060007761 - Memory module with termination component: A memory module having a termination component. The memory module includes first and second memory devices, a termination component and three sets of signal lines. A first set of signal lines is coupled to the first memory device and dedicated to data transfers involving the first memory device. A second...

20060007760 - Programmable dqs preamble: A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is...

20060007762 - Memory array decoder: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein...

20060007763 - Memory row/column replacement in an integrated circuit: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored...

20060007764 - Semiconductor fabrication that includes surface tension control: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent....

20060007767 - Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made...

20060007766 - Rotating data transmission device for multiple channels: Described is a device for signal transmission in computer tomographs, comprising a rotating part (1) supported to be rotatable with respect to a stationary part (2). A transmission controller (4) is provided on the rotating part (1) for compiling, from video data (6) of a video source (5), and from...

20060007765 - Thermal recording material: A thermally sensitive recording medium comprising, a thermally sensitive recording medium providing an undercoating layer containing a pigment and a binder as main components and a thermally sensitive recording layer containing a colorless or pale colored basic leuco dye and a color developing agent, which reacts with said basic leuco...

20060007768 - Demultiplexer, and light emitting display using the same and display panel thereof: A demultiplexer, a light emitting display using the same, and a display panel thereof. The light emitting display includes: an image signal line for supplying a data signal for displaying an image through a plurality of first signal lines; a display area including a plurality of data lines for transmitting...

20060007769 - Adaptive programming technique for a re-writable conductive memory device: A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the...

20060007770 - Semiconductor memory: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal...

20060007771 - Semiconductor device for passive rfid, ic tag, and control method thereof: A semiconductor according to an embodiment of the invention has a supply voltage generator circuit generating a supply voltage based on a received radio signal, a voltage detector circuit detecting a reference voltage dependent on the supply voltage, a memory circuit storing data, and a control circuit executing write operation...

20060007773 - Negative differential resistance (ndr) elements and memory device using the same: A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source...

20060007772 - Non-volatile memory device: A non-volatile memory device includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which...

20060007774 - Page buffer circuit and method for a programmable memory device: A page buffer for an electrically programmable memory includes a plurality of storage units, each comprising a first latch and a second latch. Input switching means loads into the latch the data bit to be written and to be temporarily stored. The input switching means has an input terminal connected...

20060002163 - Apparatus and method for detecting multiple hits in cam arrays: An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components...

20060002164 - Anti-parallel tab sensor fabrication: A method for fabricating a sensor having anti-parallel tab regions. The method includes forming a free layer having tab areas on opposite sides of an active area, forming a first layer of a carbon composition above the active area of the free layer, the first layer of carbon being substantially...

20060002165 - High speed memory modules utilizing on-trace capacitors: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at...

20060002166 - Semiconductor memory device, electronic card and electronic device: A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a...

20060002167 - Minimizing adjacent wordline disturb in a memory device: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined...

20060002168 - Switchable memory diode - a new memory device: Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an...

20060002171 - Bimodal operation of ferroelectric and electret memory cells and devices: In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be...

20060002169 - Feram memory design using rom array architecture: A FeRAM array configured in a ROM format is provided. The FeRAM array includes a memory array that has a plurality of segmented BL/PL arrays, and each segmented BL/PL array defines an I/O. A plurality of charge transfer sense amplifiers is further provided. Each charge transfer sense amplifier is associated...

20060002170 - Semiconductor storage device and method of manufacturing the same: A semiconductor storage device wherein a plurality of ferroelectric capacitors are sufficiently covered with a hydrogen barrier film formed thereon comprises a field effect transistor formed on one surface side of a semiconductor substrate, a plurality of ferroelectric capacitors formed close to each other above the field effect transistor, an...

20060002173 - Accessing phase change memories: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal...

20060002174 - Driving method of variable resistance element and memory device: A variable resistance element is configured to be provided with a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance between the first electrode and the second electrode is changed by applying a voltage pulse of a predetermined polarity between the first electrode and the...

20060002172 - Providing current for phase change memories: A programmable current source for a phase change memory allows a single current source to controllably provide the current for reading and writing both set and reset bits. In addition, the current source can vary the current based on the characteristics of a particular run of wafers. In one embodiment,...

20060002175 - Semiconductor memory device: A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines,...

20060002176 - Method for chemically bonding langmuir-blodgett films to substrates: A method of attaching a molecular layer to a substrate includes attaching a temporary protecting group(s) to a molecule having a molecular switching moiety with first and second connecting groups attached to opposed ends thereof. The temporary protecting group(s) is attached to the first and/or second connecting group so as...

20060002178 - Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts: A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductors are located on the first surface. Each word conductor...

20060002177 - Six-transistor (6t) static random access memory (sram) with dynamically variable p-channel metal oxide semiconductor (pmos) strength: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS...

20060002183 - Magnetic memory with structure providing reduced coercivity: Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises a magnetic memory cell and a conductor configured to provide a magnetic field to write the magnetic memory cell. Structure is configured to direct the magnetic field and reduce coercivity of the magnetic memory...

20060002181 - Magnetic random access memory array with global write lines: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common...

20060002179 - Method and structure for selecting anisotropy axis angle of mram device for reduced power consumption: A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at least one ferromagnetic layer of the MRAM device. The...

20060002182 - Multi-bit magnetic random access memory element: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an...

20060002180 - Random access memory array with parity bit structure: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory...

20060002185 - Magnetic cell and magnetic memory: A magnetic cell comprises: a first ferromagnetic layer whose magnetization is substantially fixed in a first direction; a second ferromagnetic layer whose magnetization is substantially fixed in a second direction opposite to the first direction; a third ferromagnetic layer provided between the first and the second ferromagnetic layers, a direction...

20060002184 - Novel underlayer for high performance magnetic tunneling junction mram: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to...

20060002186 - Magnetic random access memory element: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A...

20060002187 - Programmable fuse and antifuse and method therefor: P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied negative gate bias voltage is sufficiently large to cause tunnel electrons to gain enough energy to exceed the band gap energy of the oxide. This causes energetic...

20060002188 - Write once read only memory employing floating gates: Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region,...

20060002190 - Reduction of adjacent floating gate data pattern sensitivity: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a...

20060002189 - System and method for determining service availability and soliciting customers: A system and method for determining service availability and soliciting customers is provided, whereby the availability of a power line communications system for a user is determined and, if the service is available, an offer is provided to that user in an attempt to solicit the user as a customer....

20060002191 - Random access memory cell of reduced size and complexity: s

20060002192 - Integrated circuit memory device and method: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide....

20060002194 - Faster method of erasing flash memory: An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed....

20060002193 - System and method for determining the value of a memory element: A method for determining memory element values may include: selecting a column of interest containing a desired memory element, disabling the desired memory element, measuring a first current provided to the column of interest, adjusting measurement circuitry to compensate for skew introduced by undesired memory elements, enabling the desired memory...

20060002196 - Memory system and test method therefor: A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test...

20060002195 - System and method for a high-speed access architecture for semiconductor memory: A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is...

20060002197 - Method and apparatus to detect invalid data in a nonvolatile memory following a loss of power: Briefly, in accordance with an embodiment of the invention, a method and apparatus to detect invalid data in a memory is provided. The method may include setting at least one power loss recovery (PLR) status bit in response to the writing to or erasing of a plurality of nonvolatile memory...

20060002198 - Data storage apparatus, data providing system and data providing method: The data that a user wants are reliably provided, while avoiding any fraudulent use of the provided data. The present invention provides a data storage apparatus to be connected to an external apparatus by way of a predetermined connection interface, the apparatus comprising a data storage section including a first...

20060002199 - Nonvolatile memory apparatus: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits,...

20060002200 - Voltage control circuit and semiconductor device: A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node....

20060002201 - Active termination control: A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module...

20060002203 - Input device having activating means: An activating section is bonded to the lower portion of an input section. When a face sheet is pushed by a finger or the like, the pushing force is transmitted to the interior of an input device, and an upper electrode comes into contact with a lower electrode so as...

20060002202 - Mask rom devices of semiconductor devices and method of forming the same: Disclosed are a mask ROM device and a method of forming the same. This device includes a plurality of cells. At least one among the plurality of cells is programmed. The programmed cell includes a cell gate pattern, cell source/drain regions, a cell insulating spacer, a cell metal silicide, and...

20060002204 - Redundancy program circuit and methods thereof: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control...

20060002205 - Semiconductor device having relief circuit for relieving defective portion: A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the...

20060002206 - Data path having grounded precharge operation and test compression capability: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and...

20060002208 - Housing for a semiconductor device and semiconductor device testing system for testing the contacting for semiconductor devices positioned one above the other: The invention relates to a housing for a semiconductor device and a novel semiconductor device testing system, in particular for testing the contacting of semiconductor devices positioned one above the other, which increases the parallelism during testing, is solved by the present invention in that recesses or notches, respectively, are...

20060002209 - Mode entry circuit and method: An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin....

20060002207 - Rom test method and rom test circuit: The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific ROM(3). Then, the selected data...

20060002210 - Ethernet controller with excess on-board flash for microcontroller interface: A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data...

20060002211 - Two transistor gain cell, method, and system: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line....

20060002212 - Semiconductor device: An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a...

20060002213 - Semiconductor storage device having page copying function: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to...

20060002214 - Semiconductor storage device having page copying function: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to...

20060002215 - Information processing apparatus and information display method: An information processing apparatus includes: an input unit; a storing unit configured to store wiring layout information and layer configuration information of a multilayer printed circuit board; a layout displaying unit configured to display a wiring layout drawing based on the wiring layout information; a clipping position specifying unit configured...

20060002216 - Thin film magnetic memory device and semiconductor integrated circuit device including the same as one of circuit blocks: Shape dummy cells that are designed to have the same dimensions and structures as MTJ memory cells are additionally provided in the peripheral portion of an MTJ memory cell array in which normal MTJ memory cells for storing data are arranged in a matrix. The MTJ memory cells and the...

20060002217 - Refreshing dynamic volatile memory: A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the...

20060002218 - Method and apparatus to implement a temperature control mechanism on a memory device: In one embodiment, a method is provided. The method comprises periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if...

20060002220 - Assessing energy requirements for a refreshed device: Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The time interval during which the refresh...

20060002219 - Power offloading for a subscriber line interface circuit: A power offload network has a first node for receiving a first supply V1 and a second node for receiving a second supply V2. The power offload network includes a plurality of switches and a power offload element providing a supply drop of VR. The switches are configurable for selecting...

20060002221 - Refresh counter circuit and control method for refresh operation: A refresh counter circuit generating a row address during refresh operation for the memory device which has a normal area for storing data bits and a parity area for storing parity bits, comprising; n-stage counter which generates the row address corresponding to an address space of the normal area represented...

20060002222 - Input/output circuit: Disclosed is a semiconductor memory device divided into a core region where memory cells are formed and a peripheral region where an input/output line circuit is formed. Particularly, the input/output line circuit of the semiconductor memory device can be operated without affecting other external devices and being affected by noise...

20060002223 - Sram employing virtual rail scheme stable against various process-voltage-temperature variations: An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising...

20060002224 - Bank assignment for partitioned register banks: Operands may be assigned to physical registers within partitioned register banks by identifying possible candidate register banks for an operand. Prior to allocation of the operand to a candidate register bank, conflicts between candidate register banks, if any, may be identified and resolved....

20060002225 - Semiconductor memory device capable of stably setting mode register set and method therefor: A semiconductor memory device having a mode register set (MRS) includes: a decoding unit for decoding a plurality of address signals included in the MRS and outputting a plurality of decoded signals; and an output unit for outputting a plurality of configuration signals and activating one of the plurality of...

20060002226 - Semiconductor memory device: The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or...

20060002227 - Fuse box, semiconductor memory device having the same and setting method thereof: A semiconductor memory device includes: a TCSR generator for generating an oscillation pulse; a TCSR fuse box for adjusting an oscillation pulse period of the TCSR generator; an SSR generator for generating an SSR mode oscillation pulse; an SSR fuse box for adjusting an oscillation pulse period of the SSR...