| Stacked memory cell utilizing negative differential resistance devices -> Monitor Keywords |
|
|
  Stacked memory cell utilizing negative differential resistance devicesUSPTO Application #: 20060125017Title: Stacked memory cell utilizing negative differential resistance devices Abstract: A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell. (end of abstract)
Agent: Bever, Hoffman & Harms, LLP - Livermore, CA, US Inventor: Tsu-Jae King Liu USPTO Applicaton #: 20060125017 - Class: 257365000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), With Plural, Separately Connected, Gate Electrodes In Same Device The Patent Description & Claims data below is from USPTO Patent Application 20060125017. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS Related Applications [0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 10/827,787, entitled "Method Of Making Memory Cell Utilizing Negative Differential Resistance Devices" filed Apr. 19, 2004 which is a divisional of U.S. patent application Ser. No. 10/029,077, entitled "Memory Cell Using Negative Differential Resistance Field Effect Transistors" filed Dec. 21, 2001, now U.S. Pat. No. 6,724,655. [0002] The present application is also related to the following applications, all of which are filed simultaneously with parent application Ser. No. 10/029,077, and which are hereby incorporated by reference as if fully set forth herein: [0003] An application Ser. No. 10/028,084 entitled "INSULATED-GATE FIELD-EFFECT TRANSISTOR INTEGRATED WITH NEGATIVE DIFFERENTIAL RESISTANCE (NDR) FET"; Attorney Docket No. PROG 2001-1; and [0004] An application Ser. No. 10/028,394 entitled "DUAL MODE FET & LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE"; Attorney Docket No. PROG 2001-3, now U.S. Pat. No. 6,518,589; [0005] An application Ser. No. 10/028,089 entitled "CHARGE PUMP FOR NEGATIVE DIFFERENTIAL RESISTANCE TRANSISTOR" Attorney Docket No. PROG 2001-4, now U.S. Pat. No. 6,594,193; [0006] An application Ser. No. 10/028,085 entitled "IMPROVED NEGATIVE DIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) & CIRCUITS USING THE SAME"; Attorney Docket No. PROG 2001-5; now U.S. Pat. No. 6,559,470. FIELD OF THE INVENTION [0007] This invention generally relates to semiconductor memory devices and technology, and in particular to static random access memory (SRAM) devices. BACKGROUND OF THE INVENTION [0008] The rapid growth of the semiconductor industry over the past four decades has largely been enabled by continual advancements in manufacturing technology which have allowed the size of the transistor, the basic building block in integrated circuits (ICs), to be steadily reduced with each new generation of technology. As the transistor size is scaled down, the chip area required for a given circuit is reduced, so that more chips can be manufactured on a single silicon wafer substrate, resulting in lower manufacturing cost per chip; circuit operation speed also improves, because of reduced capacitance and higher transistor current density. State-of-the-art fabrication facilities presently manufacture ICs with minimum transistor feature size smaller than 100 nm, so that microprocessor products with transistor counts approaching 1 billion transistors per chip can be manufactured cost-effectively. High-density semiconductor memory devices have already reached the gigabit scale, led by dynamic random access memory (DRAM) technology. The DRAM memory cell consists of a single pass transistor and a capacitor (1T/1C), wherein information is stored in the form of charge on the capacitor. Although the DRAM cell provides the most compact layout (with area ranging between 4F.sup.2 and 8F.sup.2, where F is the minimum feature half-pitch defined by lithography), it requires frequent refreshing (typically on the order of once per millisecond) because the charge on the capacitor leaks away at a rate of approximately 10.sup.-15 Amperes per cell. This problem is exacerbated by technology scaling, because the transistor leakage current increases with decreasing channel length, and also because a reduction in cell capacitance results in a smaller number of stored charge carriers, so that more frequent refreshing is necessary. Thus, scaling of DRAM technology to much higher densities presents significant technological challenges. [0009] Static RAM (SRAM) does not require refreshing and is generally faster than DRAM (approaching 1 ns access times as compared to tens of ns for DRAM). However, the SRAM cell is more complex, requiring either four n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and two p-channel MOSFETs, or four n-channel MOSFETs and two polycrystalline-silicon (poly-Si) load resistors, resulting in significantly larger cell size (typically greater than >80 F.sup.2). Innovations which provide significant reductions in SRAM cell size while allowing the SRAM cell to retain its favorable operating characteristics are therefore highly desirable. [0010] Negative differential resistance (NDR) devices have previously been proposed for compact static memory applications. E. Goto in IRE Trans. Electronic Computers, March 1960, p. 25 disclosed an SRAM cell consisting of two resonant tunneling diodes (RTDs) and a pass transistor. For a variety of NDR devices including RTDs, the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage over a range of applied voltages, exhibiting negative differential resistance over this range of applied voltages and reaching a minimum ("valley") value. At yet higher applied voltages, the current again increases with increasing applied voltage. Thus, the current-vs.-voltage characteristic is shaped like the letter "N". A key figure of merit for NDR devices is the ratio of the peak current to the valley current (PVCR). The higher the value of the PVCR, the more useful the NDR device is for variety of circuit applications. The PVCR of RTDs is generally not high enough to make it practical for low-power SRAM application, because in order for the RTDs in a Goto cell to have sufficient current drive, the valley current is too large, causing large static power dissipation. In addition, RTDs require specialized fabrication process sequences so that the complexity of an integrated RTD/MOSFET SRAM process would be substantially higher than that of a conventional complementary MOS (CMOS) SRAM process, resulting in higher manufacturing cost. [0011] Accordingly, there exists a significant need for NDR devices with very high (>10.sup.6) PVCR which can be easily integrated into a conventional CMOS technology, for compact, low-power, low-cost SRAM. SUMMARY OF THE INVENTION [0012] An object of the present invention is to provide a static random access memory (SRAM) cell of significantly smaller size as compared to a conventional six-transistor SRAM cell, while retaining the desirable operating characteristics of the conventional SRAM cell without significant increase in manufacturing cost. [0013] For achieving the object, the invention provides a semiconductor device comprising an n-channel insulated-gate field-effect transistor (IGFET) including a gate and source/drain electrodes, and two (preferably n-channel) NDR-FETs each including gate and source/drain electrodes, wherein the IGFET and NDR-FET elements are formed on a common substrate, with one of the source/drain electrodes of the IGFET semiconductor element connected to the drain electrode of a first NDR-FET and also to the source electrode of a second NDR-FET, the gate electrode of the IGFET connected to a first control terminal, the other one of the source/drain electrodes of the IGFET connected to a second control terminal, the drain electrode of the first NDR-FET connected to a power-supply terminal, the source electrode of the second NDR-FET connected to a grounded or negatively-biased terminal, and the gate electrodes of the NDR-FETs each biased at a constant voltage. The point of connection between the drain electrode of the first NDR-FET and the source electrode of the second NDR-FET is the data storage node. This semiconductor device can function as a bistable memory cell, with access to the data storage node provided via the IGFET. [0014] In various embodiments, the first NDR-FET, the second NDR-FET, and the IGFET access transistor that make up the SRAM cell can be formed in two or more semiconductor layers in a stacked configuration, thereby reducing the layout area requirements of the SRAM cell. In one embodiment, the first NDR-FET, the second NDR-FET, and the IGFET access transistor can be formed in two different semiconductor layers, such that one of the first and second NDR-FETs and the IGFET access transistor overlies another of the first and second NDR-FETs and the IGFET access transistor. In another embodiment, the first and second NDR-FETs and the IGFET access transistor can each be formed in a different semiconductor layer, such that the three transistors are arranged one above another (e.g., the first NDR-FET overlies the IGFET access transistor, and the second NDR-FET overlies the first NDR-FET). BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a circuit diagram of a static random access memory (SRAM) cell consisting of the combination of two NDR-FET elements which form a bistable latch and one n-channel enhancement-mode IGFET access element; [0016] FIG. 2 is a plot of the current vs. storage node voltage characteristic of the bistable latch formed by the combination of two NDR-FETs as shown in FIG. 1; [0017] FIG. 3 is a schematic cross-sectional view of an NDR-FET element connected to an IGFET, showing the various layers shared by the two elements which are co-fabricated using a single process flow. [0018] FIGS. 4A and 4B are cross-sectional views of SRAM cells consisting of the combination of two NDR-FET elements and one n-channel enhancement-mode IGFET access element formed in multiple stacked semiconductor layers. Continue reading... Full patent description for Stacked memory cell utilizing negative differential resistance devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Stacked memory cell utilizing negative differential resistance devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Stacked memory cell utilizing negative differential resistance devices or other areas of interest. ### Previous Patent Application: Esd protection for high voltage applications Next Patent Application: Cmos image sensor and method for fabricating the same Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Stacked memory cell utilizing negative differential resistance devices patent info. IP-related news and info Results in 2.89676 seconds Other interesting Feshpatents.com categories: Tyco , Unilever , Warner-lambert , 3m |
||
