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  Stable electroless fine pitch interconnect platingUSPTO Application #: 20060180461Title: Stable electroless fine pitch interconnect plating Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation. (end of abstract) Agent: Dickstein Shapiro Morin & Oshinsky LLP - Washington, DC, US Inventor: Joseph T. Lindgren USPTO Applicaton #: 20060180461 - Class: 204228300 (USPTO) Related Patent Categories: Chemistry: Electrical And Wave Energy, Apparatus, Electrolytic, With Current, Voltage, Or Power Control Means Responsive To Sensed Condition, Fluid Flow Sensing Means The Patent Description & Claims data below is from USPTO Patent Application 20060180461. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of U.S. patent application Ser. No. 10/622,497, filed Jul. 21, 2003, the subject matter of which is incorporated in its entirety by reference herein. FIELD OF THE INVENTION [0002] The invention relates to apparatus and techniques for plating small surface features of an integrated circuit device. BACKGROUND OF THE INVENTION [0003] As integrated circuit devices become increasingly complex and feature sizes become increasingly smaller, it becomes more difficult to plate conductive metals onto the very fine pitch features. For example, bond pads formed on dies require plating to form die contacts. Improper or incomplete plating of the bond pads results in die contacts having poor solderability, which decreases yield. Also, it can be difficult to maintain the stability of baths in which parts of various sizes are plated. Consequently, a system for plating small die features, using a stable plating bath, is desired. BRIEF SUMMARY OF THE INVENTION [0004] The present invention provides an integrated circuit plating apparatus having a bath for plating die contacts on wafers. Prior to plating, die contacts are conductively connected to larger supplemental plating structures on the wafer. Initiating a plating reaction on the larger supplemental plating structures inductively activates plating on the smaller die contacts. The supplemental plating structures are sacrificed during subsequent processing. Advantageously, the supplemental plating structures also can be used for probe testing prior to die singulation. [0005] The invention further provides a method of plating die contacts of a plurality of dice (chips) on a wafer, which includes fabricating the larger supplemental plating structures on the wafer, fabricating a conductive connection between the supplemental plating structures and the die contacts, maintaining a plating bath, inserting the wafer into the plating bath, and plating the supplemental plating structures and die contacts. Plating of the die contacts is induced as a result of the conductive connection to the supplemental plating structures. The method and apparatus facilitate the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. [0006] These and other features of the invention will be seen more clearly from the following detailed description of the invention which is provided in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0007] FIG. 1 is a schematic top view of a semiconductor wafer in one embodiment of the present invention. [0008] FIG. 2 shows in enlarged detail a portion of FIG. 1. [0009] FIG. 3 illustrates linear diffusion in an electroless plating bath. [0010] FIG. 4 illustrates non-linear diffusion in an electroless plating bath. [0011] FIG. 5 is a cross-sectional view of a solid catalytic surface to depict the inhibition reaction mechanism associated with the use of a stabilizer in an electroless plating bath. [0012] FIG. 6 is a schematic top view of a plating bath system for plating multiple wafers. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0013] Referring to FIG. 1, a semiconductor wafer 10 fabricated in accordance with an exemplary embodiment of the invention includes a substrate 14 on which numerous dice are formed through etching, deposition, and other integrated circuit (IC) fabrication techniques. The substrate 14 may be formed of a variety of semiconductor materials known in the art including silicon and gallium-arsenide, among others. The wafer 10 is not limited to any particular size or shape. [0014] Each wafer 10 includes many dice. For clarity of illustration, only dice 18A-C, 20A-C, and 22A-C (collectively "dice 18-22") are shown in FIG. 1. The dice are fabricated in the aggregate on wafer 10, and after fabrication are singulated from wafer 10 using a cutting process, for example. The separation takes place along the areas between adjacent dice, the so-called "street" areas. [0015] FIG. 2 shows a portion of the die 22 in greater detail. Small bond pads, e.g., 70A, 130A, 150A, are provided on each die. The bond pads require plating with a conductive metal to form die contacts. Once the bond pad is plated, the die contact is available for subsequent bonding of solder or wire to each die, e.g., 22A. The bond pads/die contacts 70A, 130A, 150A can be square and measure approximately 5 micrometers (.mu.m) or less on a side, although other shapes and dimensions can be used. As stated above, using conventional techniques to plate features having such small dimensions can be difficult. It also is difficult to probe such small features during die testing prior to singulation. [0016] In accordance with the exemplary embodiment, plating of the small die contacts 70, 130, 150 of each die is promoted by forming conductive connections between the die contacts and a larger supplemental plating structure provided on the wafer 10. For example, as shown in FIGS. 1 and 2, each of the die contacts 70A, 70B, 70C is commonly conductively connected to a larger supplemental plating structure 32. Similarly, the die contacts 130A, 130B, 130C are conductively connected to a larger supplemental plating structure 34, and die contacts 150A, 150B, 150C are conductively connected to a larger supplemental plating structure 36. Subsequent manufacturing steps include plating the supplemental plating structures at the time the die contacts are plated, which promotes plating of the die contacts 70A-C, 130A-C, 150A-C. Advantageously, the supplemental plating structures 26, 28, 30, 32, 34, 36 also can be used for probe testing the dice prior to singulation. [0017] As shown in FIG. 2, the supplemental plating structures, e.g., 32, 34 can be square in shape with each side measuring approximately 100 .mu.m. Other suitable shapes and dimensions can be used. In one example, the die contacts are square with a side length of 5 .mu.m, and the supplemental plating structures are square with a side length of 100 .mu.m. In the aforementioned example, the surface area of the supplemental plating structure is about 400 times as large as the surface area of a corresponding die contact. [0018] The supplemental plating structures 26, 28, 30, 32, 34, 36 are positioned about the wafer 10 such that the total number of dice on wafer 10 either is not reduced at all, or is reduced by a minimum amount by addition of the supplemental plating structures 26, 28, 30, 32, 34, 36. The supplemental plating structures 26, 28, 30, 32, 34, 36 may be placed, for example, along the edge of wafer 10 where there is available space, resulting from the round shape of wafer 10 and the non-round shape of the dice array. In another embodiment, the supplemental plating structures 26, 28, 30, 32, 34, 36 may be located in the dicing lanes, i.e., the so-called "street" areas, between the dice. [0019] FIG. 2 also shows conductive paths 52, 54, 56 used to connect the supplemental plating structures 26, 28, 30, 32, 34, 36 and the die contacts, routed in the streets and on the edges of the wafer 10. During the singulation process, the supplemental plating structures 26, 28, 30, 32, 34, 36 are sacrificed, and subsequently discarded. Also, streets and conductive paths arranged in the streets no longer are needed, and can be cut and discarded. Continue reading... Full patent description for Stable electroless fine pitch interconnect plating Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Stable electroless fine pitch interconnect plating patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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