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  Solder wall structure in flip-chip technologiesUSPTO Application #: 20070176288Title: Solder wall structure in flip-chip technologies Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps. (end of abstract)
Agent: Schmeiser, Olsen & Watts - Latham, NY, US Inventors: Timothy H. Daubenspeck, Jeffrey Peter Gambino, Christopher David Muzzy, Wolfgang Sauter USPTO Applicaton #: 20070176288 - Class: 257737000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead, Bump Leads The Patent Description & Claims data below is from USPTO Patent Application 20070176288. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates to flip-chip technologies, and more specifically, to a solder wall structure in flip-chip technologies. [0003] 2. Related Art [0004] In typical flip-chip technologies, solder bumps are formed on top of a chip to help bond the chip to a ceramic substrate. These solder bumps may be corroded by carbon dioxide and water vapor of the surrounding ambient environment. Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient. SUMMARY OF THE INVENTION [0005] The present invention provides a semiconductor structure, comprising (a) a first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps. [0006] The present invention also provides a semiconductor fabrication method, comprising providing a first semiconductor chip; forming N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and forming a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps. [0007] The present invention also provides a semiconductor structure, comprising (a) a first semiconductor chip comprising a crack stop on a perimeter of the first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps, and such that the first solder wall is overlapping the crack stop; and (d) a module substrate coupled to the first solder wall and the N solder bumps [0008] Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIGS. 1A-1G illustrate a fabrication method for forming a semiconductor structure, in accordance with embodiments of the present invention. [0010] FIG. 1Fi shows a top-down view of the semiconductor structure of FIG. 1F, in accordance with embodiments of the present invention. [0011] FIG. 1Gi shows a top-down view of a semiconductor chip after it is cut from the semiconductor structure of FIG. 1G, in accordance with embodiments of the present invention. [0012] FIG. 2 illustrates a fabrication method for forming a module, in accordance with embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0013] FIGS. 1A-1G illustrate a fabrication method for forming a semiconductor structure 100, in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A, in one embodiment, the fabrication of the semiconductor structure 100 starts with a semiconductor chip 102 and a dicing channel region 104. The semiconductor chip 102 comprises multiple interconnect layers 106a, 106b, 106c, and 106d. There may be additional device layers in a silicon substrate of the semiconductor chip 102 beneath and coupled to the interconnect layer 106d, but these additional device layers and the silicon substrate are not shown for simplicity. In the embodiment described above, there are only four interconnect layers 106a, 106b, 106c, and 106d. In general, the semiconductor chip 102 can have N interconnect layers, wherein N is a positive integer. [0014] In one embodiment, the top interconnect layer 106a of the semiconductor chip 102 includes (i) a dielectric layer 110a, (ii) an electrically conducting line 120a (comprising copper (Cu) in one embodiment) embedded in the dielectric layer 110a, and (iii) a metal region 122a (comprising Cu in one embodiment) embedded in the dielectric layer 110a. Similarly, the interconnect layers 106b, 106c, and 106d comprise dielectric layers 110b, 110c, and 110d, electrically conducting lines 120b, 120c, and 120d (comprising Cu in one embodiment), and metal regions 122b, 122c, and 122d (comprising Cu in one embodiment), respectively. In one embodiment, the metal regions 122a, 122b, 122c, and 122d run on a perimeter of the semiconductor chip 102 and form a crack stop 122 surrounding the semiconductor chip 102. In one embodiment, the crack stop 122 is to prevent cracking from propagating from the dicing channel region 104 to the semiconductor chip 102 during a chip dicing process. It should be noted that from FIG. 1B to FIG. 1G, a bottom part of the structure 100, which comprises the interconnect layers 106b, 106c, and 106d, is omitted for simplicity, the only top interconnect layer 106a is shown. [0015] Next, with reference to FIG. 1B, in one embodiment, portions of the dielectric layer 110a are removed so as to create a hole 124 and a trench 126 such that top surfaces 125 and 127 of the Cu line 120a and the crack stop 122, respectively, are exposed to the surrounding ambient. In one embodiment, the trench 126 runs along the crack stop 122 of the chip 102. [0016] Next, in one embodiment, a bond pad 130 (comprising aluminum (Al) in one embodiment) is formed on top of the Cu line 120a and the dielectric layer 110a such that the Al bond pad 130 is electrically coupled to the Cu line 120a. In one embodiment, a wall base 132 (comprising Al in one embodiment) is formed on top of the crack stop 122 and the dielectric layer 110a such that the Al wall base 132 is in direct physical contact with the crack stop 122. Illustratively, the Al bond pad 130 and the Al wall base 132 can be simultaneously formed by (a) forming an Al layer (not shown) on the entire structure 100, and then (b) directionally and selectively etching back the Al layer stopping at the dielectric layer 110a. The directional and selective etching in step (b) may be performed using a traditional lithographic and etching process such that what remains of the Al layer after the etching are the Al bond pad 130 and the Al wall base 132 (as shown in FIG. 1B). In one embodiment, the Al wall base 132 runs along the crack stop 122 of the chip 102 (i.e. the Al wall base 132 runs on the perimeter of the semiconductor chip 102). [0017] Next, with reference to FIG. 1C, in one embodiment, a patterned support/interface layer 140 (comprising polyimide in one embodiment) is formed on top of the entire structure 100 of FIG. 1B. In one embodiment, the patterned support/interface layer 140 comprises a hole 142 and a trench 146 such that (i) a top surface 144 of the Al bond pad 130 is exposed to the surrounding ambient environment via the hole 142 and (ii) a top surface 148 of the Al wall base 132 is exposed to the surrounding ambient environment via the trench 146. In one embodiment, the trench 146 runs along the Al wall base 132 of the chip 102 (i.e. the trench 146 runs on the perimeter of the semiconductor chip 102). [0018] In one embodiment, the patterned support/interface layer 140 is formed using a photosensitive method. More specifically, the patterned support/interface layer 140 is formed by (i) spin-applying a polyimide film (not shown) on the structure 100 of FIG. 1B, (ii) then curing the polyimide film at a high temperature, (iii) then exposing the polyimide film to light through a mask (not shown) in a photo stepper lithographic tool (not shown), (iv) and then developing the polyimide film so as to form the patterned support/interface layer 140. It should be noted that polyimide is a photosensitive polymer. In general, other photosensitive polymers may be used instead of polyimide. [0019] Next, with reference to FIG. 1D, in one embodiment, a bump limiting metallurgy (BLM) film 150 is formed on top of the entire structure 100 of FIG. 1C by, illustratively, sputter deposition or plating or a combination of sputter deposition and plating. [0020] Next, with reference to FIG. 1E, in one embodiment, a patterned photo-resist layer 160 is formed on top of the BLM film 150. In one embodiment, the patterned photo-resist layer 160 is formed by using a conventional lithographic process. In one embodiment, the patterned photo-resist layer 160 comprises (i) a hole 162 aligned with the hole 142 and (ii) a trench 166 aligned with the trench 146 such that top surfaces 164 and 168 of the BLM film 150 are exposed to the surrounding ambient environment via the hole 162 and the trench 166, respectively. It should be noted that the holes 142 and 162 can be collectively referred to as a hole 142,162. Similarly, the trenches 146 and 166 can be collectively referred to as a trench 146,166. In one embodiment, the trench 146,166 runs on the perimeter of the semiconductor chip 102. Continue reading... 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