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  Soi bipolar transistors with reduced self heatingUSPTO Application #: 20080102568Title: Soi bipolar transistors with reduced self heating Abstract: A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method including steps of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material. (end of abstract) Agent: Michael Buchenhorner, P.A. - Miami, FL, US Inventors: Qiqing Ouyang, Kai Xiu USPTO Applicaton #: 20080102568 - Class: 438155000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.), Having Insulated Gate, And Additional Electrical Device On Insulating Substrate Or Layer The Patent Description & Claims data below is from USPTO Patent Application 20080102568. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a division of co-pending commonly-owned U.S. patent application Ser. No. 11/173,540 filed Jul. 1, 2005, which is incorporated by reference herein. STATEMENT REGARDING FEDERALLY SPONSORED-RESEARCH OR DEVELOPMENT [0002] None. INCORPORATION BY REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC [0003] None. FIELD OF THE INVENTION [0004] The invention disclosed broadly relates to the field of semi-conductor devices, and more particularly relates to bipolar transistors. BACKGROUND OF THE INVENTION [0005] Transistors, a basic component of analog and digital circuits, are commonly implemented using Complementary Metal Oxide Semiconductor (CMOS) technology. That technology increasingly uses SOI (Silicon on Insulator) substrate for device scaling. Both lateral and vertical bipolar transistors have been implemented with this technology. Furthermore, vertical bipolar transistors on thin SOI substrate with partially or fully depleted collector have shown high Early Voltage, high breakdown voltage, and reduced collector-base capacitance. [0006] However, due to the poor thermal conductivity of buried oxide (BOX) layers, the self heating in lateral SOI BJTs and vertical SOI BJTs, especially on thin SOI substrates, can significantly degrade the performance of those devices. For example, the SiGe bipolar transistors on SOI substrate suffer from thermal runaway (for fixed V.sub.be) or current collapse (for fixed I_b). The thinner the SOI is, and/or the thicker the BOX layer is, the worse these effects. Currently, trench technology is often used as device isolation, and the trenches tend to block the heat flow and make the self heating worse. In order to reduce the self-heating, better and or more heat conducting paths must be created within the device and/or among the devices on the same chip. Therefore, there is a need for an improved transistor structure that reduces self-heating. SUMMARY OF THE INVENTION [0007] Briefly, according to an embodiment of the invention, a method for constructing a bipolar transistor including a collector, a base and an emitter, all located over a substrate, includes steps or acts of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material. BRIEF DESCRIPTION OF THE DRAWINGS [0008] To describe the foregoing and other exemplary purposes, aspects, and advantages, we use the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which: [0009] FIG. 1 shows the cross-sectional schematic of a vertical SOI BJT structure with reduced self-heating according to an embodiment of the invention. [0010] FIG. 2 shows the cross-sectional schematic of disclosed lateral SOI BJT structure with reduced self-heating according to another embodiment of the invention. [0011] FIGS. 3A through 3C show simulated geometry effects on the highest temperature in the device with the heat drainage. [0012] FIG. 4 shows the schematic of a complementary BiCMOS integrated circuit with heat drainage according to another embodiment of the invention. [0013] FIG. 5 is a flow chart of a method for constructing a bipolar transistor structure according to another embodiment of the invention. [0014] While the invention as claimed can be modified into alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention. DETAILED DESCRIPTION [0015] We describe a structure that has reduced self-heating in SOI (Silicon on Insulator) bipolar junction transistors (BJTs). By creating a heat conducting path with better thermal-conducting materials such as metal or polysilicon, the self heating can be reduced significantly. We also discuss methods for reducing self-heating in SOI bipolar transistors. [0016] We use the fact that in a bipolar transistor structure most power is generated in the collector. For example in a SiGe-base BJT, the total power generated at a collector is more than 1 mW. This power consumption heats up the transistor in which it occurs. One way to dissipate the heat generated by this power consumption is to use "heat drainage." The size of the heat drainage element does not have to be larger than it is for electrodes (for example, 90 nm minimum contact size for the state of art CMOS technologies). This is because metal has much larger thermal conductivity (10-20.times. better) than oxide. Therefore, adding this heat "drainage" element does necessarily not increase the chip size. Alternatively, doped polysilicon can be used for heat "drainage" as well. Continue reading... Full patent description for Soi bipolar transistors with reduced self heating Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Soi bipolar transistors with reduced self heating patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Soi bipolar transistors with reduced self heating or other areas of interest. ### Previous Patent Application: Method for making thin film transistor Next Patent Application: Method of fabricating vertical body-contacted soi transistor Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Soi bipolar transistors with reduced self heating patent info. IP-related news and info Results in 0.26423 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
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