| Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture -> Monitor Keywords |
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Sliding window scheme (sws) for determining clock timing in a mesh-based clock architectureRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width), Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing)Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070016882, Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application claims the benefit under 35 U.S.C. .sctn. 119(e) of U.S. Provisional Application No. 60/697,110, filed Jul. 6, 2005. TECHNICAL FIELD OF THE INVENTION [0002] This invention relates in general to designing integrated circuits (ICs) and more particularly to determining clock timing in a mesh-based clock architecture. BACKGROUND OF THE INVENTION [0003] Mesh architectures often distribute critical global signals on a chip such as clock and power/ground. Redundancy created by loops present in a mesh tends to smooth out undesirable variations between signal nodes spatially distributed over the chip. However, accurate analysis of a mesh architecture is difficult. BRIEF DESCRIPTION OF THE DRAWINGS [0004] To provide a more complete understanding of the present invention and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which: [0005] FIG. 1 illustrates an example clock mesh architecture; and [0006] FIG. 2 illustrates an example connection of a global H-tree to a mesh; [0007] FIG. 3 illustrates an example single-.pi. model of a wire; [0008] FIG. 4 illustrates an example 3-.pi. model of a wire; [0009] FIG. 5 illustrates an example window; and [0010] FIG. 6 illustrates an example method for SWS-based clock mesh analysis. DESCRIPTION OF EXAMPLE EMBODIMENTS [0011] FIG. 1 illustrates an example clock mesh architecture. Mesh (or grid) architectures often distribute critical global signals on a chip, such as, for example, clock and power/ground. The mesh architecture uses redundancy created by loops to smooth out undesirable variations between signal nodes spatially distributed over the chip. These variations can be due to non-uniform switching activity in the design, within-die process variations and asymmetric distribution of circuit elements, such as, for example, flip-flops (FFs). For power/ground, mesh can help reduce voltage variations at different nodes in the network due to non-uniform switching activities. For the clock signal, a mesh (such as the example mesh illustrated in FIG. 1) may achieve very low skew in microprocessor designs, e.g., Digital 200-MHz Alpha and 600-MHz Alpha; IBM G5 S/390, Power4, and PowerPC; and SUN Sparc V9. Mesh also has desirable jitter mitigation properties. [0012] However, a problem that has limited the applicability of mesh architectures is the difficulty of analyzing them with sufficient accuracy. Reasons for this difficulty include the large number of circuit nodes needed to accurately model a fine mesh in a large design and the large number of metal loops present in the mesh structure. As a result, circuit simulators such as SPICE either require a large amount of memory, a long run-time, or both. [0013] Particular embodiments provide a scheme (called herein a sliding-window scheme (SWS)) for analyzing clock meshes. Particular embodiments accurately compute the clock arrival time at the clock input pin of each FF. In particular embodiments SWS is substantially accurate, requires substantially less memory, and may analyze large industrial designs in a relatively short amount of time. In particular embodiments SWS is also easily amenable to distributed (or grid) computing. Particular embodiments provide effective solutions to problems associated with traditional clock mesh analysis. Particular embodiments facilitate the use of clock mesh architectures in application-specific integrated circuit (ASIC) and processor design. [0014] The mesh architecture illustrated in FIG. 1 may distribute a clock signal from a phase-locked loop (PLL) or root buffer to sequential elements, such as, for example, FFs and latches on a chip. The mesh architecture illustrated in FIG. 1 has three main components: a uniform mesh, a global tree that drives the mesh, and a local interconnect, where the clock inputs of FFs connect directly to the nearest point on the mesh. Although a uniform mesh is illustrated and described, the present invention contemplates nonuniform meshes, as well as uniform meshes. The mesh illustrated in FIG. 1 is a uniform rectangular grid of wires spanning the entire chip area (or the smallest rectangular region spanned by FFs) driven by the mesh buffers and propagating the clock to the FFs. An m.times.n mesh has m rows (horizontal wires) and n columns (vertical wires). The size of a mesh stands for m.times.n. For a given chip size, the greater the mesh size, the more fine-grain the mesh. A mesh node (or grid node) is the point where each row is connected to each column. FIG. 2 illustrates an example connection of a global H-tree to a mesh. The global tree delivers the clock signal to the mesh nodes via buffers called mesh buffers. Assume a uniform array of k.times.l mesh buffers. In FIG. 2, k=m=4 and l=n=4. The mesh wire between two adjacent mesh nodes is called a mesh segment. [0015] In a clock distribution scheme, a concern is to accurately compute the clock arrival time a (also called clock delay or latency) at the clock input pin of each FF. Assume a path P in a design having start and end gates that are FFs F.sub.s, and F.sub.e, respectively. Let clock arrival times at these FFs be a.sub.s, and a.sub.e, respectively. The maximum delay d.sub.max allowed on P is a function of a.sub.e-a.sub.s, the difference in clock arrival times at the two FFs.d.sub.max.ltoreq.a.sub.e-a.sub.s+.tau.-t.sub.set.sup.--.sub.up (1) where .tau. is the clock cycle and t.sub.set.sup.--.sub.up is the set-up time for F.sub.e. a.sub.e-a.sub.s is the skew between F.sub.s, and F.sub.e. By comparing the arrival times among all FFs, the worst relevant clock skew in the design may be computed. This is the maximum difference in arrival times at two FFs connected to each other by a data path. The worst skew impacts the maximum operating frequency for the design, since it limits the maximum delay in the data path. [0016] Traditional static timing analysis (STA) techniques typically assume an acyclic underlying structure for the logic and interconnect and cannot handle loops present in the clock mesh. Moreover, industry-standard STA tools usually have up to a 15% difference vis-a-vis SPICE with respect to cell and interconnect delays. Such a large inaccuracy in timing is unacceptable for the clock signal. As a result, particular embodiments use SPICE for accurate timing analysis of the clock mesh. [0017] It is relatively straightforward and fast to compute the latency on the global tree. Particular embodiments address only the mesh timing-analysis problem. The same clock signal may be assumed to drive all mesh buffers. It may be assumed that the design is already placed and FF locations are known. Particular embodiments accurately compute the arrival time of the rising edge of the clock at each FF. [0018] In particular embodiments, wires compose a mesh. In such embodiments, an accurate wire model for the mesh is important. To model wires smaller than approximately 100 .mu.w, particular embodiments use a single-.pi. model, which has two capacitors, a resistor, and an inductor. FIG. 3 illustrates an example single-.pi. model. For longer wires, particular embodiments use a 3-.pi. model. FIG. 4 illustrates an example three-.pi. model. In particular embodiments, such a scheme may provide accuracy to within approximately 0.5% of 4-.pi. and 5-.pi. models, while helping to reduce the number of nodes in the SPICE model. Particular embodiments use the same rule to model the wires that connect FFs to the mesh. Particular embodiments model the clock pin of a FF as a simple equivalent capacitance. [0019] The use of a mesh is often limited by difficulties associated with analyzing the mesh. SPICE simulations may be performed to analyze the mesh, but SPICE analysis often fails on clock meshes for chip-level circuits, such as, for instance, a 64.times.64 mesh for a circuit with 100 K FFs. Such simulations may run out of memory or require excessive CPU time for one or both of the following reasons: [0020] 1. Model size: Due to importance of the interconnect in determining path delays, interconnect should be modeled accurately. Each mesh wire segment contributes three nodes if a single-.pi. model is used, and seven nodes for a 3-.pi. model. Similarly, each FF is a node and its connection point to the mesh is one node. Thus, just the mesh and the local FF connections can contribute hundreds of thousands of nodes in the SPICE model. SPICE runs of memory when generating the model or the run-time requirements are excessive, since the run-time of SPICE grows as O(N.sup.p), where N is the number of nodes in the model and 1<p<2. [0021] 2. Due to a large number of cycles and redundancy present in the mesh structure, simulation of the mesh by a circuit simulator is excessively time consuming. Continue reading about Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture... Full patent description for Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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