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Slater & Matsil, L.L.P. patentsThe following is a sampling of recent Slater & Matsil, L.L.P. patent applications (USPTO Patent Application #, Patent Title) sorted by month.
June 2009 - Slater & Matsil, L.L.P. patents
20090160020 - Moisture barrier capacitors in semiconductor components
20090160027 - Methods of manufacturing semiconductor devices and optical proximity correction
20090160062 - Semiconductor devices and methods of manufacturing thereof
20090161565 - System and method of remote testing in loopback mode using mgcp/ncs
20090152672 - Semiconductor devices and methods of manufacture thereof
20090154035 - Esd protection circuit
20090146146 - Semiconductor device formed in a recrystallized layer
20090146217 - Semiconductor devices and methods of manufacture thereof
20090147420 - Circuit arrangement with an overcurrent fuse
20090140248 - On-chip test circuit for an embedded comparator
20090140335 - Drain-extended field effect transistor
20090140372 - Semiconductor devices and methods of manufacture thereof
20090140707 - Circuit for an active diode and method for operating an active diode
20090141424 - Semiconductor devices and methods of manufacture thereof
20090141691 - Access point for wireless local area network
20090141816 - Method of transmission power control and communication device
May 2009 - Slater & Matsil, L.L.P. patents
20090134497 - Through substrate via semiconductor components
20090135655 - Embedded flash memory devices on soi substrates and methods of manufacture thereof
20090127597 - Photodiode structure
20090128282 - Integrated lateral short circuit for a beneficial modification of current distribution structure for xmr magnetoresistive sensors
20090121321 - Wafer and a method of dicing a wafer
20090122460 - Semiconductor device and method for producing the same
20090124027 - Structure and method for placement, sizing and shaping of dummy structures
20090124089 - Device and method for stopping an etching process
20090114955 - Method for fabricating a fin-shaped semiconductor structure and a fin-shaped semiconductor structure
20090114979 - Finfet device with gate electrode and spacers
20090115074 - Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element
20090115487 - Level converter
April 2009 - Slater & Matsil, L.L.P. patents
20090110088 - System and method for providing a versatile rf and analog front-end for wireless and wired networks
20090110100 - Allocating data between tones
20090111550 - Text message entry of a remote contest using participation code awarded at a local arcade game
20090101975 - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor
20090101975 - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor
20090101975 - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor
20090096068 - System and method for stabilizing an amplifier
20090098692 - Method for fabricating a semiconductor gate structure
20090091729 - Lithography systems and methods of manufacturing using thereof
20090092926 - Lithography systems and methods of manufacturing using thereof
20090093127 - Treatment of a substrate with a liquid medium
20090085035 - Method of producing a semiconductor element in a substrate and a semiconductor element
20090085035 - Method of producing a semiconductor element in a substrate and a semiconductor element
20090086554 - System and method for operating a semiconductor memory
20090086554 - System and method for operating a semiconductor memory
20090087631 - Wafer and a method for manufacturing a wafer
20090087632 - Wafer and method for producing a wafer
20090087631 - Wafer and a method for manufacturing a wafer
20090087632 - Wafer and method for producing a wafer
20090088113 - Fast hopping frequency synthesizer
20090088113 - Fast hopping frequency synthesizer
March 2009 - Slater & Matsil, L.L.P. patents
20090079005 - Integrated circuits and methods of design and manufacture thereof
20090079449 - Test structures, systems, and methods for semiconductor devices
20090081563 - Integrated circuits and methods of design and manufacture thereof
20090072315 - Semiconductor manufacturing process charge protection circuits
20090073620 - Circuit arrangement comprising an electronic component and an esd protection arrangement
20090077525 - System and method for semiconductor device fabrication using modeling
20090065349 - Plasma vapor deposition
20090065868 - Electronic circuit and method of manufacturing an electronic circuit
20090065870 - Semiconductor devices and methods of manufacture thereof
20090066550 - Sigma-delta modulator for operating sensors
20090066951 - Method for evaluating an optical imaging process
20090068771 - Electro chemical deposition systems and methods of manufacturing using the same
20090057826 - Semiconductor devices and methods of manufacture thereof
20090057923 - Methods of fabricating semiconductor devices and structures thereof
20090058468 - Method of detecting the frequency of an input clock signal of an integrated circuit and integrated circuit
20090059239 - Method of determining the depth profile of a surface structure and system for determining the depth profile of a surface structure
20090059678 - Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
February 2009 - Slater & Matsil, L.L.P. patents
20090050970 - Diode-based esd concept for demos protection
20090050972 - Strained semiconductor device and method of making same
20090053654 - Mask and method for patterning a semiconductor wafer
20090045879 - Amplifier and method for operating the same
20090046568 - Communication apparatus and method
20090046822 - System and method for clock drift compensation
20090049369 - Circuit arrangement and method for error detection and arrangement for monitoring of a digital circuit
20090039442 - Semiconductor devices and methods of manufacture thereof
20090041028 - Method and device for reconstructing a data clock from asynchronously transmitted data packets
20090042359 - Structure and method of producing isolation with non-dopant implantation
20090043972 - Memory updating
20090032841 - Semiconductor devices and methods of manufacture thereof
20090033538 - Ramp linearization for fmcw radar using digital down-conversion of a sampled vco signal
January 2009 - Slater & Matsil, L.L.P. patents
20090026539 - Method and layout of semiconductor device with reduced parasitics
20090026555 - Transistor with dopant-bearing metal in source and drain
20090026572 - Method of manufacturing a semiconductor device, method of manufacturing a soi device, semiconductor device, and soi device
20090029108 - Barrier layers for conductive features
20090020800 - Semiconductor device and method of making same
20090023078 - Lithography masks and methods of manufacture thereof
20090023259 - Method of producing non volatile memory device
20090023405 - Rf front-end circuitry with reduced dc offset
20090014832 - Semiconductor device with reduced capacitance tolerance value
20090015252 - Magnetoresistive magnetic field sensor structure
20090015334 - Bypass circuit for radio-frequency amplifier stages
20090015975 - Overvoltage protection apparatus and an associated protection circuit
20090010315 - Communication methods and apparatuses
20090011360 - Photo-resist material structure and method of producing the same
20090001502 - Semiconductor devices and methods of manufacture thereof
20090001964 - Integrated hybrid current sensor
20090001965 - Magnetic-field sensor and method of calibrating a magnetic-field sensor
20090001982 - Method and apparatus for defined magnetizing of permanently magnetizable elements and magnetoresistive sensor structures
20090002905 - Over-voltage and under voltage protection circuit
April 2008 - Slater & Matsil, L.L.P. patents
20080093675 - Mos devices with continuous contact etch stop layer
20080093682 - Polysilicon levels for silicided structures including mosfet gate electrodes and 3d devices
20080094114 - Controller including a sawtooth generator and method of operating the same
20080094223 - Asset including a radio frequency identification tag and method of forming the same
20080096336 - Method of forming integrated circuit devices having n-mosfet and p-mosfet transistors with elevated and silicided source/drain structures
20080096363 - High dielectric constant materials
20080096380 - Low-k interconnect structures with reduced rc delay
20080087921 - Image sensor device suitable for use with logic-embedded cis chips and methods for making the same
20080090347 - Lateral power mosfet with high breakdown voltage and low on-resistance
20080091765 - Method and system for detecting undesired email containing image-based messages
20080092215 - System and method for transparent single sign-on
20080083948 - Sige selective growth without a hard mask
20080084842 - Method and system for foreign agent relocation in wireless network
20080085590 - Method of making fusi gate and resulting structure
20080085606 - Method for fabricating a structure for a semiconductor component, and semiconductor component
20080085607 - Method for modulating stresses of a contact etch stop layer
20080078114 - Fishing lure
20080079455 - Ic chip package, test equipment and interface for performing a functional test of a chip contained within said chip package
20080080432 - Carrying mobile station specific information in the reverse access channel in a wireless communications system
20080081382 - Method for reducing layout-dependent variations in semiconductor devices
20080081613 - Sending quick paging messages and regular paging messages in a wireless communications system
March 2008 - Slater & Matsil, L.L.P. patents
20080073688 - One-transistor random access memory technology compatible with metal gate process
20080073689 - Program/erase schemes for floating gate memory cells
20080073745 - High-voltage mos device improvement by forming implantation regions
20080073747 - Electromagnetic shielding using through-silicon vias
20080073753 - Test line placement to improve die sawing quality
20080067557 - Mos devices with partial stressor channel
20080067577 - Multi-trapping layer flash memory cell
20080068887 - Program methods for split-gate memory
20080070370 - Silicide formation with a pre-amorphous implant
20080070542 - Power allocation in a mimo system without channel state information feedback
20080070603 - Idle mode notification
20080071511 - Prediction and control of nbti of integrated circuits
20080061338 - Method for processing a structure of a semiconductor component, and structure in a semiconductor component
20080061379 - Mos devices with graded spacers and graded source/drain regions
20080061441 - Flexible via design to improve reliability
20080054250 - Structure and methods for forming sige stressors
20080054301 - Mos transistor with in-channel and laterally positioned stressors
20080054304 - Semiconductor device including a lateral field-effect transistor and schottky diode
20080054347 - Composite stressors in mos devices
20080054399 - Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof
20080054874 - Power converter employing regulators with a coupled inductor
20080056045 - Device for refreshing memory contents
20080056188 - Transmitting page and broadcast control channel through the same time frequency resources across the sectors in a wireless communications system
20080057660 - Step-gate for a semiconductor device
20080057976 - Wireless communications control in a controlled environment facility
20080059927 - Method and device and their use for checking the layout of an electronic circuit
February 2008 - Slater & Matsil, L.L.P. patents
20080047577 - Substrate cleaning device and cleaning method thereof
20080048173 - Semiconductor device including a lateral field-effect transistor and schottky diode
20080048174 - Semiconductor device including a lateral field-effect transistor and schottky diode
20080048545 - Gas-filled discharge gap
20080049525 - Integrated semiconductor memory and method for operating an integrated semiconductor memory
20080050898 - Semiconductor devices and methods of manufacture thereof
20080042123 - Methods for controlling thickness uniformity of sige regions
20080043561 - Circuit for an sram with reduced power consumption
20080046306 - System and method for analyzing strategic network investments in wireless networks
20080035997 - Fin field-effect transistor and method for fabricating a fin field-effect transistor
20080038904 - Method and device for handling an article in the course of semiconductor fabrication
20080039053 - Information dissemination systems and methods for use in a controlled environment facility
20080029830 - Forming reverse-extension mos in standard cmos flow
20080029831 - Cmos devices with graded silicide regions
20080032472 - Methods for improving uniformity of cap layers
January 2008 - Slater & Matsil, L.L.P. patents
20080022763 - Apparatus and method for fluid flow measurement with sensor shielding
20080023850 - Silicon-based thin substrate and packaging schemes
20080024259 - Extended e matrix integrated magnetics (mim) core
20080024276 - Interrogator and interrogation system employing the same
20080024277 - Interrogator and interrogation system employing the same
20080024278 - Interrogator and interrogation system employing the same
20080017948 - Structures of high-voltage mos devices with improved electrical performance
20080018350 - Test probe for integrated circuits with ultra-fine pitch terminals
20080018366 - Driver for switch and a method of driving the same
20080018432 - Interrogator and interrogation system employing the same
20080018450 - Interrogator and interrogation system employing the same
20080018468 - Interrogator and interrogation system employing the same
20080018469 - Interrogator and interrogation system employing the same
20080020533 - Method and apparatus for semiconductor device with improved source/drain junctions
20080022037 - Memory system and method for transferring data therein
20080012133 - Reducing resistivity in interconnect structures by forming an inter-layer
20080012138 - One-time-programmable anti-fuse formed using damascene process
20080012936 - 3-d displays and telepresence systems and methods therefore
20080014706 - Increasing dielectric constant in local regions for the formation of capacitors
20080014741 - Process for improving the reliability of interconnect structures and resulting structure
20080006868 - Logic compatible storage device
20080006908 - Body-tied, strained-channel multi-gate device and methods of manufacturing same
20080008972 - Method for automatically generating at least one of a mask layout and an illumination pixel pattern of an imaging system
20080001189 - Shielding structures for preventing leakages in high voltage mos devices
20080001237 - Semiconductor device having nitrided high-k gate dielectric and metal gate electrode and methods of forming same
20080002452 - Method for setting a read voltage, and semiconductor circuit arrangement
20080002481 - Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module
20080003734 - Selective formation of stress memorization layer
December 2007 - Slater & Matsil, L.L.P. patents
20070296002 - Backside contacts for mos devices
20070296013 - Semiconductor device structure for reducing mismatch effects
20070296022 - Flash memory process with high voltage ldmos embedded
20070296028 - Vertical field-effect transistor and method of forming the same
20070296052 - Methods of forming silicide regions and resulting mos devices
20070298557 - Junction leakage reduction in sige process by tilt implantation
20070298559 - Vertical field-effect transistor and method of forming the same
20070298564 - Vertical field-effect transistor and method of forming the same
20070298565 - Junction leakage reduction in sige process by implantation
20070298593 - Epitaxy silicon on insulator (esoi)
20070298602 - Method for applying solder to redistribution lines
20070290277 - Process for fabricating a strained channel mosfet device
20070291526 - Structure for a non-volatile memory device
20070284615 - Ultra-shallow and highly activated source/drain extension formation using phosphorus
20070284677 - Metal oxynitride gate
20070287199 - Base oxide engineering for high-k gate stacks
20070287240 - Advanced forming method and structure of local mechanical strained transistor
20070278541 - Spacer engineering on cmos devices
20070278681 - Interconnection structure design for low rc delay and leakage
20070278682 - Self-assembled mono-layer liner for cu/porous low-k interconnections
20070278906 - Piezoelectric transformer
20070283297 - Signal processing circuit
November 2007 - Slater & Matsil, L.L.P. patents
20070272916 - Flash memory with deep quantum well and high-k dielectric
20070274027 - Housing for high performance components
20070274147 - Integrated semiconductor memory and method for operating an integrated semiconductor memory
20070276623 - Semiconductor component test process and a system for testing semiconductor components
20070267678 - Mos devices with corner spacers
20070267694 - Transistors with stressed channels and methods of manufacture
20070267724 - Integrated circuit having stress tuning layer and methods of manufacturing same
20070268747 - Static noise-immune sram cells
20070269978 - Process for improving copper line cap formation
20070264762 - Semiconductor-on-insulator sram configured using partially-depleted and fully-depleted transistors
20070257210 - Preventing dosage drift with duplicate dose integrators
20070257308 - Modifying work function in pmos devices by counter-doping
20070257366 - Barrier layer for semiconductor interconnect structure
20070257369 - Reducing resistivity in interconnect structures of integrated circuits
20070257389 - Imprint mask and method for defining a structure on a substrate
20070253239 - Read-preferred sram cell design
20070253264 - Integrated semiconductor memory with a test function and method for testing an integrated semiconductor memory
20070254447 - Decoupled pocket and ldd formation
20070254476 - Cleaning porous low-k material in the formation of an interconnect structure
October 2007 - Slater & Matsil, L.L.P. patents
20070246821 - Utra-thin substrate package technology
20070249159 - Method for forming dielectric film to improve adhesion of low-k film
20070249209 - Circuit arrangement for coupling a voltage supply to a semiconductor component, method for producing the circuit arrangement, and data processing device comprising the circuit arrangement
20070241386 - Method for reducing topography of non-volatile memory and resulting memory cells
20070241855 - Device for electrical isolation, toroidal core choke, and method for producing the toroidal core choke
20070235817 - Write margin improvement for sram cells with sige stressors
20070235823 - Cmos devices with improved gap-filling
20070235838 - Flexible metal-oxide-metal capacitor design
20070238237 - Structure and method for a sidewall sonos non-volatile memory device
20070228571 - Interconnect structure having a silicide/germanide cap layer
20070229284 - Radio frequency identification tag and method of forming the same
20070229790 - Arrangement for the transfer of structural elements of a photomask onto a substrate and method therefor
20070231999 - High performance transistor with a highly stressed channel
September 2007 - Slater & Matsil, L.L.P. patents
20070221999 - Semiconductor devices and methods of manufacture thereof
20070222035 - Stress intermedium engineering
20070224752 - Laterally diffused metal oxide semiconductor device and method of forming the same
20070224776 - Method for forming a 3d interconnect and resulting structures
20070224794 - Single passivation layer scheme for forming a fuse
20070224808 - Silicided gates for cmos devices
20070215936 - Diffusion topography engineering for high performance cmos fabrication
20070216526 - Interrogator and interrogation system employing the same
20070210777 - Controller for a power converter and method of operating the same
20070210921 - Interrogator and interrogation system employing the same
20070212841 - Structure and method for a sidewall sonos memory device
20070214220 - Method and system for recognizing desired email
20070205248 - Flexible processing method for metal-insulator-metal capacitor formation
20070205507 - Carbon and nitrogen based cap materials for metal hard mask scheme
20070205508 - Bond pad structure for wire bonding
20070207730 - Adaptive multi-beamforming systems and methods for communication systems
20070209059 - Communication system employing a control layer architecture
20070209067 - System and method for providing security for sip-based communications
August 2007 - Slater & Matsil, L.L.P. patents
20070200162 - Reducing dielectric constant for mim capacitor
20070200182 - Memory array structure with strapping cells
20070200241 - Dual damascene process without an etch stop layer
20070200247 - Interconnect structure to reduce stress induced voiding effect
20070202676 - Integration scheme for cu/low-k interconnects
20070202727 - Holder for a choke coil and an inductive component with the holder
20070194409 - Method of manufacturing semiconductor device with crack prevention ring
20070194667 - Piezoelectric transformer
20070195820 - System and method for adaptive frame size management in a wireless multihop network
20070196934 - Predictions of leakage modes in integrated circuits
20070196935 - Prediction of esl/ild remaining thickness
20070187717 - Semiconductor device having reduced on-resistance and method of forming the same
20070187725 - Method and apparatus for a semiconductor device with a high-k gate dielectric
20070190730 - Resolving pattern-loading issues of sige stressor
20070190731 - Diffusion layer for semiconductor devices
20070191067 - Adaptive beamforming systems and methods for communication systems
20070181951 - Selective cesl structure for cmos application
20070176371 - Piston ring for an internal combustion engine
July 2007 - Slater & Matsil, L.L.P. patents
20070173022 - Defect-free sige source/drain formation by epitaxy-free process
20070164439 - In-situ deposition for cu hillock suppression
20070166904 - Pre-gate dielectric process using hydrogen annealing
20070157843 - Small smart weapon and weapon system employing the same
20070158783 - Interdigitated capacitive structure for an integrated circuit
20070160227 - Sound control device
20070161174 - Manufacturing of memory array and periphery
20070161195 - Structure and method for a sidewall sonos memory device
20070161230 - Uv curing of low-k porous dielectrics
June 2007 - Slater & Matsil, L.L.P. patents
20070145367 - Three-dimensional integrated circuit structure
20070145417 - High voltage semiconductor device having a lateral channel and enhanced gate-to-drain separation
20070145489 - Design of high-frequency substrate noise isolation in bicmos technology
20070145515 - Metal electrical fuse structure
20070145519 - Butted contact structure
20070145596 - Interconnect structure and method of fabricating same
20070148881 - Hybrid sti stressor with selective re-oxidation anneal
20070138531 - Metal-insulator-metal capacitors
20070139849 - Line filter
20070143307 - Communication system employing a context engine
20070143396 - Method for client-server-based communication over several interfaces and client supporting the method
20070132033 - High voltage cmos devices
20070132035 - Transistor mobility improvement by adjusting stress in shallow trench isolation
20070132059 - Laser fuse with efficient heat dissipation
20070126053 - Non-volatile memory array structure
20070126121 - Via structure with improved reliability
20070127183 - Surge arrester
20070128736 - Multi-metal-oxide high-k gate dielectrics
May 2007 - Slater & Matsil, L.L.P. patents
20070120172 - Logic compatible non-volatile memory cell
20070114979 - Power converter employing a tapped inductor and integrated magnetics and method of operating the same
20070117374 - Method of forming via recess in underlying conductive line
20070108529 - Strained gate electrodes in semiconductor devices
20070109852 - One time programming memory cell using mos device
20070109972 - Method for wireless network self-configuration
20070111402 - Production and packaging control for repaired integrated circuits
20070111404 - Method of manufacturing strained-silicon semiconductor device
20070111425 - Composite gate structure in an integrated circuit
20070111535 - Method to create damage-free porous low-k dielectric films and structures resulting therefrom
20070102763 - Multiple-gate transistors formed on bulk substrates
20070102769 - Dual soi structure
20070105301 - High-gain vertex lateral bipolar junction transistor
20070106567 - Information capture, processing and retrieval system and method of operating the same
20070096092 - Semiconductor device fault detection system and method
20070100575 - Method for eliminating reading errors in a non-contact microwave solids flow meter
April 2007 - Slater & Matsil, L.L.P. patents
20070090462 - Silicided regions for nmos and pmos devices
20070090547 - Exclusion zone for stress-sensitive circuit design
20070085130 - Tungsten-containing nanocrystal, an array thereof, a memory comprising such an array, and methods of making and operating the foregoing
20070085145 - High voltage transistor with improved driving current
20070086098 - Color wheel device and projector using the same
20070080387 - Method and structure for a 1t-ram bit cell and macro
20070080461 - Ultra low-k dielectric in damascene structures
20070074386 - Method of forming a power module with a magnetic device having a conductive clip
20070075347 - Phase change memory devices with reduced programming current
20070075377 - High performance device design
20070075815 - Method of forming a magnetic device having a conductive clip
20070075816 - Power module with a magnetic device having a conductive clip
20070075817 - Magnetic device having a conductive clip
20070076477 - Sonos type two-bit finfet flash memory cell
March 2007 - Slater & Matsil, L.L.P. patents
20070045702 - Insulation layer to improve capacitor breakdown voltage
20070045719 - Multi-purpose semiconductor device
20070045765 - Semiconductor device having substrate-driven field-effect transistor and schottky diode and method of forming the same
20070045849 - Semiconductor structure having selective silicide-induced stress and a method of producing same
February 2007 - Slater & Matsil, L.L.P. patents
20070039270 - Veneered raised panel element and method of manufacturing thereof
20070040188 - Contact or via hole structure with enlarged bottom critical dimension
20070034517 - Interconnect structure for semiconductor devices
20070034906 - Mos devices with reduced recess on substrate surface
20070034956 - Embedded silicon-controlled rectifier (scr) for hvpmos esd protection
20070035383 - Radio frequency identification interrogation systems and methods of operating the same
20070037326 - Shallow source/drain regions for cmos transistors
20070037355 - Esd protection device for high voltage
20070029608 - Offset spacers for cmos transistors
20070032037 - Method of forming soi-like structure in a bulk semiconductor substrate using self-organized atomic migration
January 2007 - Slater & Matsil, L.L.P. patents
20070018253 - Memory cell and manufacturing methods
20070018331 - Dummy structures extending from seal ring into active circuit area of integrated circuit chip
20070020777 - Controlling system for gate formation of semiconductor devices
20070020866 - Cmos transistor with high drive current and low sheet resistance
20070020921 - Prevention of trench photoresist scum
20070020952 - Repairing method for low-k dielectric materials
20070012905 - Novel phase change random access memory
20070013010 - High performance mos device with graded silicide
20070013070 - Semiconductor devices and methods of manufacture thereof
20070010051 - Method of forming a mos device with an additional layer
20070010073 - Method of forming a mos device having a strained channel region
20070011151 - Concept bridge and method of operating the same
20070001217 - Closed loop cesl high performance cmos devices
December 2006 - Slater & Matsil, L.L.P. patents
20060289920 - Composite gate structure in an integrated circuit
20060291577 - System and method for selecting pilot tone positions in communication systems
20060292770 - Cmos on soi substrates with hybrid crystal orientations
20060292834 - High performance transistors with hybrid crystal orientations
20060284249 - Impurity co-implantation to improve transistor performance
20060286735 - Integrated circuit transistor insulating region fabrication method
20060286758 - Super anneal for process induced strain modulation
20060278870 - Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
20060278915 - Finfet split gate eeprom structure and method of its fabrication
20060273391 - Cmos devices for low power integrated circuits
20060273409 - High performance cmos with metal-gate and schottky source/drain
20060275975 - Nitridated gate dielectric layer
20060276030 - Novel method to implement stress free polishing
November 2006 - Slater & Matsil, L.L.P. patents
20060270112 - Overhang support for a stacked semiconductor device, and method of forming thereof
20060270166 - Laser spike annealing for gate dielectric materials
20060261490 - Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
20060263992 - Method of forming the n-mos and p-mos gates of a cmos semiconductor device
20060254927 - Image sensor system for monitoring condition of electrode for electrochemical process tools
20060255360 - Semiconductor device having multiple lateral channels and method of forming the same
20060255365 - Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
20060249755 - Method to prevent arcing during deep via plasma etching
20060252227 - Sram cell having stepped boundary regions and methods of fabrication
20060244074 - Hybrid-strained sidewall spacer for cmos process
20060244080 - Profile confinement to improve transistor performance
20060244133 - Design structure for coupling noise prevention
20060246672 - Method of forming a locally strained transistor
20060246720 - Method to improve thermal stability of silicides with additives
October 2006 - Slater & Matsil, L.L.P. patents
20060242589 - System and method for remote examination services
20060233027 - System and method for a high-speed access architecture for semiconductor memory
20060234431 - Doping of semiconductor fin devices
20060234455 - Structures and methods for forming a locally strained transistor
20060226477 - Substrate driven field-effect transistor
20060226478 - Semiconductor device having a lateral channel and contacts on opposing surfaces thereof
20060226487 - Resistor with reduced leakage
20060228850 - Pattern loading effect reduction for selective epitaxial growth
20060220133 - Doping of semiconductor fin devices
20060220244 - Contact pad and bump pad arrangement for high-lead or lead-free bumps
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