| Simultaneous scan testing for identical modules -> Monitor Keywords |
|
|
 
Simultaneous scan testing for identical modulesRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic Testing, Scan Path Testing (e.g., Level Sensitive Scan Design (lssd))Simultaneous scan testing for identical modules description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060242508, Simultaneous scan testing for identical modules. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] None. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] Not applicable. REFERENCE TO A MICROFICHE APPENDIX [0003] Not applicable. FIELD OF THE INVENTION [0004] The present invention relates to scan testing of integrated circuits. More particularly, embodiments of the present invention allow two or more substantially identical modules to be tested simultaneously using the same test patterns and testing resources. BACKGROUND OF THE INVENTION [0005] A scan chain, a serially connected set of flip-flops, is sometimes embedded in an integrated circuit chip to facilitate testing of the chip prior to its delivery to a customer. To test an integrated circuit by means of a scan chain, a pattern of data is serially clocked into the chain of flip-flops. On the first clock pulse of a series of clock pulses, the first flip-flop in the chain accepts a data bit. For example, a bit of data moves from the input to the output of the flip-flop. Since the output of the first flip-flop is the input of the second flip-flop, the first bit of data is then present at the input of the second flip-flop. At the second clock pulse, the data bit that was at the input of the second flip-flop moves to the output of that flip-flop and the first flip-flop accepts a new bit of data. Data continues to move in this manner through the chain of flip-flops until the first bit of data reaches the last flip-flop. This serial input of data into a scan chain is known as the shift mode. [0006] After the shift mode is complete, the scan chain can enter the capture mode. In capture mode, the data bits at the outputs of the flip-flops are moved in parallel fashion into the logic circuits of the integrated circuit chip. The logic circuits then manipulate the data and the resulting data is moved in parallel fashion back to the flip-flops. A shift mode is then re-entered and the data is shifted out of the flip-flops one bit at a time in a manner similar to the way data was shifted in. The data that is shifted out of the flip-flops can be compared to the expected output to determine if the integrated circuit logic performed as expected in manipulating the data. [0007] As used herein, the terms "scan test", "scan testing", and the like refer to the testing of integrated circuits in the manner described above. "Scan input" refers to a stream of binary data that is entered into an integrated circuit to perform a scan test and "scan output" refers to the stream of binary data that is produced by a scan test. "Input" and "output" can also refer to physical points in a digital circuit into which binary data is entered and from which binary data is produced. [0008] The symbols "0" and "1" are used herein as they are commonly used by those of skill in the art to refer to binary data values. The binary values might represent the absence or presence, or approximate absence or presence, of a voltage or might represent some other physical attribute typically manipulated by a digital circuit. Regardless of the actual physical characteristic represented, a "0" or a "1" is intended to symbolize a value that might appear in one of the truth tables commonly associated with the standard logic gates well known in the art. SUMMARY OF THE INVENTION [0009] According to one embodiment, a system is provided for scan testing at least two substantially identical modules within an integrated circuit. The system includes a first module to receive and process scan input and produce a first scan output. The system includes a second module substantially similar to the first module. The second module receives and processes scan input and produces a second scan output. The system also includes a first component to receive the first and second scan outputs and to produce a first output. The first output is used to determine whether the first and second modules are functioning properly. [0010] In an alternative embodiment, a system is provided for scan testing at least two substantially identical modules within an integrated circuit. The system includes a scan input, a first module, and a second module. The first module is operable to receive and process the scan input and produce a first scan output. The second module is substantially similar to the first module. The second module is operable to receive and process the scan input and produce a second scan output. The system also includes a means for receiving the first and second scan outputs and producing a first output. The first output used to determine whether the first and second modules are functioning properly. [0011] In another embodiment, a method is provided for determining whether at least two substantially identical modules within an integrated circuit are functioning properly. The method includes sending a scan input to a first module and a second module. The method includes producing a first scan output by the first module, and producing a second scan output by the second module. The method includes sending the first and second scan outputs to a first component, and producing a first output by the first component. The method also includes using the first output to determine whether the first and second modules are functioning properly. [0012] These and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS [0013] For a more complete understanding of the presentation and the advantages thereof, reference is now made to the following brief description, taken in connection with the accompanying drawings in detailed description, wherein like reference numerals represent like parts. [0014] FIG. 1 is a block diagram of an embodiment of an electronic circuit for simultaneous scan testing of two identical modules. [0015] FIG. 2 is a block diagram of another embodiment of an electronic circuit for simultaneous scan testing of two identical modules. [0016] FIG. 3 is a block diagram of an embodiment of an electronic circuit for simultaneous scan testing of three identical modules. [0017] FIG. 4 is a block diagram of an embodiment of an electronic circuit for simultaneous scan testing of four identical modules. Continue reading about Simultaneous scan testing for identical modules... Full patent description for Simultaneous scan testing for identical modules Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Simultaneous scan testing for identical modules patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Simultaneous scan testing for identical modules or other areas of interest. ### Previous Patent Application: Method and system for an on-chip ac self-test controller Next Patent Application: Enhancements to data integrity verification mechanism Industry Class: Error detection/correction and fault detection/recovery ### FreshPatents.com Support Thank you for viewing the Simultaneous scan testing for identical modules patent info. IP-related news and info Results in 0.16613 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
