Site News  |   Monitor Keywords  |   Monitor Archive  |   Organizer  |   Account Info  |

Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (sonos) transistor and a gate oxide in a metal oxide semiconductor (mos)

Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (sonos) transistor and a gate oxide in a metal oxide semiconductor (mos) description/claims

1. Field of Invention

The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to simultaneous formation of the top oxide in a nonvolatile silicon oxide nitride oxide silicon (SONOS) based nonvolatile memory transistor and a gate oxide for a metal oxide semiconductor (MOS) transistor included within control circuits.

2. The Relevant Technology

Some semiconductor chips include SONOS based nonvolatile memory transistors, and MOS transistors in various configurations. In particular, the MOS transistors are located within control circuits, which can be located in the nonvolatile memory array, volatile memory array, or a peripheral control circuit. The MOS transistors in the control circuits include, in part, pass gate transistors in the nonvolatile memory array for controlling access to SONOS based nonvolatile memory transistors, peripheral MOS transistors in the peripheral control circuit, and volatile transistors in the volatile memory array.

A current process flow for fabricating a nonvolatile memory device separately forms the top oxide in a oxide-nitride-oxide (ONO) structure and a gate oxide of a MOS transistor used in a control circuit. Specifically, the tunnel oxide, nitride, and the top oxide are sequentially formed on a silicon substrate for the ONO structure. The top oxide layer is typically a deposited oxide which is not dense and easily etched during subsequent cleaning processes. As such, the top oxide layer may be further densified to minimize losses to the top oxide layer processing steps.

The ONO layers are patterned and etched from the silicon surface except for areas where the SONOS memory transistors are formed. Also, the gate oxides of MOS transistors located on the semiconductor chip are formed separately through thermal oxidation. Unfortunately, even after densification, the top oxide of the ONO structure is susceptible to etching during subsequent cleaning steps, which results in a non-uniform top oxide layer of the ONO structure. As a result, the thickness of the top oxide layer in the ONO structure is hard to control, which can lead to lower yields.

A method for semiconductor fabrication includes providing a silicon substrate and forming a tunnel oxide layer over the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at least one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.

In an alternate configuration, a semiconductor chip includes a silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory transistor. The SONOS based nonvolatile memory transistor comprises an oxide-nitride-oxide (ONO) structure, wherein the ONO structure comprises a top oxide layer. The semiconductor chip also includes at least one MOS transistor, wherein the MOS transistor includes a gate oxide formed from a gate oxide layer, wherein a quality of the top oxide layer is substantially similar to a quality of the gate oxide layer of the at least one MOS transistor.

Exemplary embodiments are illustrated in referenced figures of the drawings which illustrate what is regarded as the preferred embodiments presently contemplated. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than limiting.

FIG. 1 is a simplified block diagram illustrating a semiconductor chip implementing the simultaneous formation of oxide layers, in accordance with one embodiment of the present invention.

FIG. 2 is a flow diagram illustrating the process flow for simultaneously forming oxide layers in a semiconductor chip, in accordance with one embodiment of the present invention.

FIG. 3A is a simplified depiction of multiple transistors in cross section showing the formation of the nitride and tunnel oxide layers, in accordance with one embodiment of the present invention.

FIG. 3B is a simplified depiction of multiple transistors in cross section showing the isolation of the SONOS memory transistor, in accordance with one embodiment of the present invention.

FIG. 3C is a simplified depiction of multiple transistors in cross section showing the simultaneous formation of the top oxide of the SONOS transistor and the gate oxide of a MOS transistor in a control circuit, in accordance with one embodiment of the present invention.

FIG. 4 is a flow diagram illustrating the process flow for simultaneous formation of oxide layers for a SONOS based nonvolatile memory transistor and at least one corresponding pass-gate MOS transistor, in accordance with one embodiment of the present invention.

FIG. 5 is simplified depiction of tri-gate structure in cross section for a nonvolatile memory cell as a specific example of the simultaneous formation of oxide layers for a SONOS based nonvolatile memory transistor and at least one corresponding pass-gate MOS transistor, in accordance with one embodiment of the present invention.

• Provisional Patent
• Utility Patent

• What Is a Patent?
• What Is a Trademark or Servicemark?
• What Is a Copyright?
• Patent Laws