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  Simulation method for semiconductor circuit device and simulator for semiconductor circuit deviceUSPTO Application #: 20070209027Title: Simulation method for semiconductor circuit device and simulator for semiconductor circuit device Abstract: A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias gate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ΔPD(t)=CD+BD·log(t) is calculated by using constants CD and BD depending on the negative bias voltage, a recovery amount ΔPR (t)=CR+BR·log(t) is calculated by using constants CR and BR depending on the bias free voltage, and the deterioration amount (ΔPD), the recovery amount (ΔPR) and a basic deterioration amount (XD) are summed. (end of abstract) Agent: Lerner, David, Littenberg, Krumholz & Mentlik - Westfield, NJ, US Inventor: Hiroki Usui USPTO Applicaton #: 20070209027 - Class: 716004000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating The Patent Description & Claims data below is from USPTO Patent Application 20070209027. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates to a simulation method of characteristics of a transistor and a semiconductor circuit device composed of a transistor, and a simulator of characteristics of a semiconductor circuit device for carrying out the method. [0002] The present invention particularly relates to a simulation method of characteristics deterioration of an MIS (Metal Insulator Semiconductor) transistor and a semiconductor circuit device including an MIS transistor due to an NBTI (Negative Bias Temperature Instability) phenomenon, and a simulator for carrying out the method. BACKGROUND ART [0003] As a semiconductor integrated circuit device being developed to be high-density, high-integrated and miniaturized, development of a miniaturizing technique of dimensions of a semiconductor circuit device including a MIS transistor, etc., such as a MOS transistor, composing a semiconductor integrated circuit device is notable. Amid the technological development, reliability of a semiconductor circuit device including a MIS transistor, etc., such as a MOS transistor, has been a significant problem because of deterioration of transistor characteristics. [0004] As the deterioration of MOS transistor characteristics, there is, for example, deterioration of a drain current over time. The deterioration of a drain current leads to deterioration of characteristics that a delay time of the circuit increases over time. When the increase of the delay time exceeds a certain degree, there is a possibility that a timing error of a signal input/output operation in the semiconductor integrated circuit or to/from the outside arises to cause an erroneous operation of the whole system incorporating the semiconductor integrated circuit. [0005] Previously, hot carrier deterioration has been mainly studied in the characteristics deterioration of a MOS transistor. For example, the Japanese Unexamined Patent Publication No. 11-135388 and the Japanese Unexamined Patent Publication No. 2001-352059 describe contents on hot carrier deterioration. [0006] A hot carrier deterioration phenomenon is a phenomenon that electrons and electron holes having high energy (hereinafter, referred to as a "hot carrier") are generated due to a strong electric field at a drain end of a MOS transistor and the hot carriers deteriorate characteristics of a gate oxide film. [0007] The Lucky Electron model (hereinafter, referred to as the LE model) presented at the IEEE in 1985, which is a currently used existing technique for simulating hot carrier deterioration, is expressed by the formula 1 below and is a method of calculating a characteristics deterioration model limited to one phenomenon regarding hot electrons having high energy due to the strong electric field. .DELTA. .times. .times. P = ( time Ids w .times. ( Ib Ids ) m ) n ( 1 ) [0008] The ".DELTA.P" indicates a deterioration amount of transistor characteristics when time "time" has passed, the "Ids" indicates a source/drain current of the transistor, the "Ib" indicates a substrate current, the "w" indicates a channel width, and the "m" and "n" are constants. [0009] Previously, transistor deterioration expressed by using the LE model, that is, transistor deterioration expressed by the source/drain current "Ids" and the substrate current "Id", was the most noteworthy deterioration phenomenon. [0010] However, as MOS transistors getting miniaturized, a new deterioration phenomenon called NBTI (Negative Bias Temperature Instability) was found and acknowledged as a problem. [0011] The NBTI deterioration phenomenon indicates a phenomenon that characteristics of a transistor, such as a drive ability, deteriorate when a negative voltage (a negative bias voltage) is continuously applied to a gate electrode of the transistor in the semiconductor substrate composing the transistor in a high temperature condition. Particularly, the characteristics deterioration due to the NBTI deterioration phenomenon is large in a MIS type transistor, such as a p-type MOS transistor having a surface channel structure wherein a nitride is used for a gate insulation film. [0012] In a MOS transistor, the NBTI deterioration phenomenon is interpreted as a phenomenon caused by a high temperature condition of a balanced state of chemical reaction arisen on a boundary between a silicon substrate and an oxide silicon insulation film and changes due to application of a negative voltage. [0013] In the NBTI deterioration phenomenon, the deterioration amount increases and decreases in a short time while deterioration of the transistor characteristics proceeds over time as a whole. [0014] Studies for improving the structure of the transistor not to cause characteristics deterioration have been pursued on the NBTI deterioration phenomenon and, on an assumption of an existence of the NBTI deterioration phenomenon, an approach by a simulation for designing a semiconductor device with high reliability by accurately perceiving the details and calculating on the NBTI deterioration phenomenon has been also pursued. [0015] However, the conventional simulation method, for example the LE model, is not capable of sufficiently dealing with changes of characteristics deterioration in the NBTI deterioration phenomenon, so that it is not sufficient for correctly estimating a deterioration amount due to the NBTI deterioration phenomenon and designing a semiconductor device or a semiconductor integrated circuit with high reliability. As a result, it is difficult to correctly setting a design margin in accordance with the characteristics deterioration of the transistor. [0016] When the design margin is set to be larger than necessary, an area of the semiconductor chip may become large and an amount of a semiconductor chips produced from one wafer decreases. Thus, setting a larger margin than necessary has to be prevented as much as possible. On the other hand, when a necessary and sufficient design margin is not set, a lifetime of the semiconductor circuit device may become short. [0017] However, in the conventional method, since changes of a direct current portion of the deterioration are not correctly expressed, it is pointed out that there is a high possibility that a deterioration amount in the NBTI deterioration phenomenon is overestimated. The direct current portion of the deterioration will be explained later on. [0018] Furthermore, changes of transistor characteristics deterioration due to a temperature of the transistor on operations and application of a gate voltage of a negative level as a negative bias voltage in the NBTI deterioration phenomenon have not been known at all. However, when changes of transistor characteristics deterioration are not taken into consideration, there are problems that the NBTI deterioration phenomenon is not correctly perceived and the deterioration cannot be correctly estimated. For example, there is a possibility that the deterioration amount is underestimated or inversely overestimated. DISCLOSURE OF THE INVENTION [0019] An object of the present invention is to provide a method of correctly simulating a characteristics deterioration phenomenon of a circuit including a transistor by correctly estimating change of the characteristics deterioration amount when a transistor deterioration phenomenon is also taken into consideration. [0020] Also, an object of the present invention is to provide a semiconductor characteristics simulator for effectively implementing the above simulation method. [0021] Furthermore, an object of the present invention is to make it possible to produce a semiconductor circuit device effectively by designing a semiconductor circuit device having high reliability by using a result of the above simulation method and/or the semiconductor characteristics simulator. Continue reading... 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