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  Simple and amended saturation for pipelined arithmetic processorsUSPTO Application #: 20070005676Title: Simple and amended saturation for pipelined arithmetic processors Abstract: A method and apparatus to substantially prevent overflow in microprocessors are described. (end of abstract) Agent: Volentine Francos & Whitt, PLLC. One Freedom Square - Reston, VA, US Inventor: Matthew R. Henry USPTO Applicaton #: 20070005676 - Class: 708552000 (USPTO) Related Patent Categories: Electrical Computers: Arithmetic Processing And Calculating, Electrical Digital Calculating Computer, Particular Function Performed, Arithmetical Operation, Compensation For Finite Word Length, Overflow Or Underflow The Patent Description & Claims data below is from USPTO Patent Application 20070005676. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] Microprocessors are ubiquitous in today's world, finding applications from sophisticated computer and communication systems to childrens' toys. One type of microprocessor is a digital signal processor (DSP). A DSP is a microprocessor specifically designed for processing digital signals. With the proliferation of digital circuits and applications utilizing digital processing, DSPs are used in many different digital applications. Recently, DSPs have been developed which incorporate dedicated hardware accelerators to perform tasks that are normally MIPS (millions of instructions per second). [0002] While DSPs have provided improved information processing speeds, there remains further demand to improve the processing speed of DSPs and microprocessors in general. One shortcoming of known DSPs results from overflow during calculations. Signed fixed-point digital addition and subtraction can overflow the designated numerical representation. For example, an N-bit signed number system generally encompasses numbers in the range of -2.sup.N-1 to 2.sup.N-1 -1. After attaining the highest possible number (maximum positive/minimum negative), the number `wraps around` to the minimum negative or maximum positive number, depending on the numbers. As can be appreciated, overflow can be deleterious to the accuracy of the microprocessor. [0003] One way to address overflow in critical paths of a microprocessor is to saturate a result that would otherwise overflow. Saturation is a technique whereby a maximum positive or a minimum negative is assigned to a number that overflows. Accordingly, saturation prevents conditions where a computation would result in overflow by clipping the result. As can be appreciated, saturation results in some inaccuracy in processor computation, but can prevent overflow of numbers in a continuum, and thereby prevent even more significant processor errors. Furthermore, arithmetic results often become operands of another calculation. As such, a saturated result is often used recursively. While the use of a saturated result is not ideal, it is a better alternative than use of an overflow result. [0004] Many known methods for saturating results in processors results in significant propagation delays incurred for arithmetic functions, which can directly limit the operating frequency of the DSP or microprocessor. [0005] There is a need for a saturation method and apparatus that overcomes at least the shortcomings described above. SUMMARY [0006] In an example embodiment a method includes providing a first operand and a second operand. The method also includes performing an arithmetic operation on the first and second operands. In parallel with performing the arithmetic operation, the method includes predicting whether and overflow will occur based on the first and second operands. [0007] In another example embodiment, an arithmetic and logic unit (ALU) includes an arithmetic unit adapted to perform an arithmetic function. The ALU also includes an amended saturation detection unit a saturation prediction unit and a Boolean logic unit. [0008] In yet another example embodiment, a method includes providing a first operand and a second operand. The method also includes performing an arithmetic operation on the first operand and on the second operand to obtain an arithmetic result. In addition, the method includes providing an amended arithmetic result if the arithmetic result overflows. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The example embodiments are best understood from the following detailed description when read with the accompanying drawing figures. Wherever applicable and practical, like reference numerals refer to like elements. [0010] FIG. 1 is a simplified block diagram of a digital signal processor (DSP) in accordance with an example embodiment. [0011] FIG. 2A is a simplified schematic diagram of an ALU in accordance with an example embodiment. [0012] FIG. 2B is a simplified schematic diagram of an ALU in accordance with an example embodiment. [0013] FIG. 3a is a tabular representation used to predict saturation in accordance with an example embodiment. [0014] FIG. 3b is a tabular representation used to predict saturation in accordance with an example embodiment. DETAILED DESCRIPTION [0015] In the following detailed description, for purposes of explanation and not limitation, example embodiments disclosing specific details are set forth in order to provide a thorough understanding of an embodiment according to the present teachings. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure that other embodiments according to the present teachings that depart from the specific details disclosed herein remain within the scope of the appended claims. Moreover, descriptions of well-known apparati and methods may be omitted so as to not obscure the description of the example embodiments. Such methods and apparati are clearly within the scope of the present teachings. [0016] Specific details will now be set forth with respect to example embodiments depicted in the attached drawings. [0017] FIG. 1 is a simplified block diagram of a DSP 100 in accordance with an example embodiment. The DSP of the example embodiment includes a memory 101. The memory 101 is coupled to an operand fetch unit 102, which is adapted to provide and retrieve operands from the memory. In addition, an instruction fetch and decode unit 106 is coupled to the memory. The operand fetch unit 102 is coupled to a multiplier 103, which is in turn coupled to an ALU 104. The ALU 104 of example embodiments is described in greater detail herein. [0018] The output of the ALU is provided to accumulators 105, which are a series of registers. As is known, the function of the ALU 104 is often recursive in nature, with the output of one arithmetic operation performed in the ALU 104 being an operand of a subsequent operation. As such, some or all of the output of the accumulators 105 may be fed back into the ALU 104 as shown. Alternatively, some or all of the output of the accumulators may be provided to the memory 101. [0019] The processed data from the memory 101 may then be provided to a bus or other communication link (not shown), or may be further processed by the DSP 100, or both. Notably, many of the elements of the DSP 101 and their function are known to one of ordinary skill in the art, and may be implemented in known hardware and software. Details of these elements and their function are not provided so as to avoid obscuring the description of the example embodiments. [0020] FIG. 2A is a simplified schematic diagram of the ALU 104 in accordance with an example embodiment. An instruction from the memory 101 presents a first operand 201 (operand 0) and a second operand 202 (operand 1). The operands 201, 202 are input in parallel to an arithmetic unit (e.g., an adder/subtractor) 203; to a simple saturation prediction unit 204; and to a logic unit 205. Notably, the processing of two operands is merely illustrative and it is emphasized that the present teachings may be applied to more operands than two. [0021] As described in specific detail herein, the ALU 104 substantially prevents overflow and saturates certain results. Saturating a result first requires an overflow of the positive or negative bounds set for the DSP 100. Such overflow could occur as a result of the arithmetic function of the arithmetic unit 203. If overflow is detected, the ALU 104 selects a saturated result to replace the sum or difference that would overflow. Continue reading... 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