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  Silicon on insulator structure with a single crystal cz silicon device layer having a region which is free of agglomerated intrinsic point defectsUSPTO Application #: 20080020168Title: Silicon on insulator structure with a single crystal cz silicon device layer having a region which is free of agglomerated intrinsic point defects Abstract: The present invention relates to a silicon on insulator (“SOI”) structure in which the device layer is derived from a single crystal Cz silicon wafer which has an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The device layer of the silicon on insulator structure is single crystal Cz silicon having an axially symmetric region which is substantially free of agglomerated intrinsic point defects. (end of abstract) Agent: Senniger Powers - St Louis, MO, US Inventor: Robert J. Falster USPTO Applicaton #: 20080020168 - Class: 428064100 (USPTO) Related Patent Categories: Stock Material Or Miscellaneous Articles, Circular Sheet Or Circular Blank The Patent Description & Claims data below is from USPTO Patent Application 20080020168. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation application based on U.S. Ser. No. 10/963,137 filed on Oct. 12, 2004, which is a continuation application based on U.S. Ser. No. 10/038,084 filed on Jan. 3, 2002, now U.S. Pat. No. 6,849,901 which is a divisional application based on U.S. Ser. No. 09/737,715 filed on Dec. 15, 2000, now U.S. Pat. No. 6,342,725, which is a continuation of U.S. Ser. No. 09/387,288 filed on Aug. 31, 1999, now U.S. Pat. No. 6,236,104, which claims priority to U.S. provisional application Ser. No. 60/098,902 filed on Sep. 2, 1998, the entire disclosures of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention is directed to a silicon on insulator (SOI) structure having a low defect density device layer. More specifically, the present invention is directed to a SOI structure wherein the device layer is derived from a single crystal silicon wafer which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention is directed to a SOI structure having a single crystal silicon handle wafer which is capable of forming an ideal, non-uniform depth distribution of oxygen precipitates, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process. [0003] A SOI structure generally comprises a handle wafer, a device layer, and an insulating film, (typically an oxide layer) between the handle wafer and the device layer. Generally, the device layer is between 0.5 and 20 micrometers thick. Such a wafer may be prepared using various techniques known in the art. For example, wafer thinning techniques may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. (See, e.g., U.S. Pat. No. 5,189,500). Alternatively, a single wafer may be used wherein molecular oxygen ions (O.sub.2.sup.+) or atomic oxygen ions (O.sup.+) are implanted below the surface of the wafer to form an oxide layer. This process is generally referred to as SIMOX (i.e., separation by implantation of oxygen; see, e.g., U.S. Pat. No. 5,436,175 and Plasma Immersion Ion Implantation For Semiconductor Processing, Materials Chemistry and Physics 46 (1996) 132-139). Such a process is considered advantageous because it acts to reduce the number of silicon wafers which are consumed, as compared to the more conventional wafer thinning processes, in the preparation of a SOI structure. [0004] SOI structures may be prepared from silicon wafers sliced from single crystal silicon ingots grown in accordance with the Czochralski method. In recent years, it has been recognized that a number of defects in single crystal silicon form during the growth process as the crystal cools after solidification. Such defects arise, in part, due to the presence of an excess (i.e., a concentration above the solubility limit) of intrinsic point defects, which are known as vacancies and self-interstitials. Silicon crystals grown from a melt typically contain an excess of one or the other type of intrinsic point defect, either crystal lattice vacancies or silicon self-interstitials. It has been suggested that the type and initial concentration of these point defects in the silicon are determined at the time of solidification and, if these concentrations reach a level of critical supersaturation in the system and the mobility of the point defects is sufficiently high, a reaction, or an agglomeration event, will likely occur. Agglomerated intrinsic point defects in silicon can severely impact the yield potential of the material in the production of complex and highly integrated circuits, such as those utilizing SOI structures. [0005] Vacancy-type defects are recognized to be the origin of such observable crystal defects as D-defects, Flow Pattern Defects (FPDs), Gate Oxide Integrity (GOI) Defects, Crystal Originated Particle (COP) Defects, crystal originated Light Point Defects (LPDs), as well as certain classes of bulk defects observed by infrared light scattering techniques such as Scanning Infrared Microscopy and Laser Scanning Tomography. Also present in regions of excess vacancies are defects which act as the nuclei for ring oxidation induced stacking faults (OISF). It is speculated that this particular defect is a high temperature nucleated oxygen agglomerate catalyzed by the presence of excess vacancies. [0006] In addition to the above-mentioned vacancy-type defects, it is also believed that agglomerated vacancy defects, or voids, may be the cause of "HF defects" (i.e., metal precipitation defects). HF defects are, like these other vacancy-type defects, considered to be a critical problem with current SOI technology. [0007] Defects relating to self-interstitials are less well studied. They are generally regarded as being low densities of interstitial-type dislocation loops or networks. Such defects are not responsible for gate oxide integrity failures, an important wafer performance criterion, but they are widely recognized to be the cause of other types of device failures usually associated with current leakage problems. [0008] Agglomerated intrinsic point defects can create performance problems for SOI substrates if silicon wafers containing such defects are utilized as the source of the device layer. Performance problems may also result from metallic contaminants present in the handle wafer portion of the SOI structure. During the heat treatments employed by the SOI process, metallic contaminants, present in the handle wafer as a result of cleaning and handling of the SOI structure, may migrate through the silicon matrix until the oxide layer, present between the handle wafer and the device layer, is reached. Although generally speaking these impurities may not pass through the oxide layer and into the device layer, the oxide layer is a preferential site for the precipitation of these impurities. This precipitation acts to disrupt the oxide layer and interfere with the performance of the SOI device. [0009] Accordingly, a need continues to exist for a SOI substrate which contains a device layer which is substantially free of agglomerated intrinsic point defects. Additionally, a need continues to exist for a SOI substrate which contains a handle wafer capable of inhibiting the precipitation of metallic impurities at or near the oxide layer/silicon interface. SUMMARY OF THE INVENTION [0010] Among the objects of the present invention, therefore, is the provision of a silicon on insulator structure having a device layer containing an axially symmetric region of substantial radial width which is substantially free of defects resulting from an agglomeration of crystal lattice vacancies or silicon self-interstitials; the provision of such a structure having a handle wafer with improved gettering capabilities; the provision of such a structure wherein the handle wafer comprises a silicon wafer which is capable, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, of forming an ideal, non-uniform depth distribution of oxygen precipitates; and, the provision of such a structure which is less susceptible to the formation of metal precipitate defects during device fabrication. [0011] Briefly, therefore, the present invention is directed to a silicon on insulator structure which comprises (i) a handle wafer, (ii) a single crystal silicon device layer having a central axis, a circumferential edge, a radius extending from the central axis to the circumferential edge, and a first axially symmetric region which is substantially free of agglomerated intrinsic point defects, and (iii) an insulating layer between the handle wafer and the device layer. [0012] The present invention is further directed to a silicon on insulator structure which comprises (i) a handle wafer, the handle wafer comprising a Czochralski single crystal silicon wafer having two major, generally parallel surfaces, one of which is the front surface and the other of which is the back surface of the silicon wafer, a central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, a surface layer which comprises a first region of the silicon wafer between the front surface and a distance, D.sub.1, of at least about 10 micrometers, as measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the silicon wafer between the central plane and the first region, the silicon wafer being characterized in that it has a non-uniform distribution of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer, with the vacancies having a concentration profile in which the peak density of the vacancies is at or near the central plane with the concentration generally decreasing from the position of peak density in the direction of the front surface of the handle wafer, (ii) a single crystal silicon device layer, and (iii) an insulating layer between the handle wafer and the device layer. [0013] The present invention is still further directed to a silicon on insulator structure which comprises (i) a handle wafer, the handle wafer comprising a Czochralski single crystal silicon wafer having two major, generally parallel surfaces, one of which is the front surface and the other of which is the back surface of the silicon wafer, a central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, a denuded zone which comprises the region of the silicon wafer from the front surface to a distance, D.sub.1, of at least about 10 micrometers, as measured in the direction of the central plane, and which contains interstitial oxygen, the silicon wafer being characterized in that the concentration of interstitial oxygen in the denuded zone at a distance equal to about one-half of D.sub.1 is at least about 75% of the maximum concentration of interstitial oxygen in the denuded zone, (ii) a single crystal silicon device layer; and (iii) an insulating layer between the handle wafer and the device layer. [0014] Other objects and features of this invention will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a schematic depiction of the ideal precipitating wafer process. [0016] FIG. 2 is a photograph of a cross-section of a wafer (sample 4-7) which was processed as described in Example 1. [0017] FIG. 3 is a photograph of a cross-section of a wafer (sample 4-8) which was subjected to the series of steps described in Example 1. [0018] FIG. 4 is a photograph of a cross-section of a wafer (sample 3-14) which was subjected to the series of steps described in Example 1. [0019] FIG. 5 is a graph of the log of platinum concentration (atoms/cm.sup.3) versus depth from the surface of a wafer (sample 4-7) which was subjected to the series of steps set forth in Example 1. [0020] FIG. 6 is a photograph of a cross-section of a wafer (sample 3-4) which was subjected to the series of steps set forth in Example 2. Continue reading... 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