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Signal flow driven circuit analysis and partitioning techniqueRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit DesignSignal flow driven circuit analysis and partitioning technique description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070006103, Signal flow driven circuit analysis and partitioning technique. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This is a continuation application based on U.S. patent application Ser. No. 10/762,790 filed Jan. 23, 2004, which claims priority to provisional patent application Ser. No. 60/442,306 filed Jan. 27, 2003. BACKGROUND [0002] The present invention relates generally to circuit analysis and partitioning and more specifically, to a signal flow driven circuit analysis and partitioning technique for mixed-signal circuit performance optimization, yield enhancement and layout optimization. [0003] It should be appreciated that circuit analysis and partitioning have been in use for years with digital designs. Typically, circuit analysis and partitioning include the manual partitioning of circuit blocks based on their functionality and physical requirements during the circuit design and layout stages. For radio frequency (RF)/Analog circuit blocks, identifying the critical signal flow is either not performed or implicitly identified at the layout stages manually by layout designers. Circuit optimization is commonly performed by trial-and-error with detailed simulators, such as SPICE. [0004] The main problem with conventional circuit analysis and partitioning is that mixed signal circuit designs often suffer sub-optimal block level partitioning or no partitioning at all due to the lack of an automated solution. This results in either compromised performance of the product or excessive physical area of the layout. Another problem with conventional circuit analysis and partitioning is that massive numerical simulations are needed to optimize the performance of the circuit. Simulation can be so prohibitively time and/or computation power intensive, that performance optimization may not be feasible for a certain scale of circuits. Yet another problem with conventional circuit analysis and partitioning is the difficulty to assure high quality layout, as it is up to the layout designer to manually identify the critical signal path during the layout stage, which is largely dependent on designers' experience level and is susceptible to errors. [0005] In these respects, the signal flow driven circuit analysis and partitioning technique according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of mixed signal circuit performance optimization, yield enhancement and layout optimization. SUMMARY [0006] In view of the foregoing disadvantages inherent in the known types of circuit analysis and partitioning now present in the prior art, the present invention provides a new signal flow driven circuit analysis and partitioning technique construction wherein the same can be utilized for mixed signal circuit performance optimization, yield enhancement and layout optimization. [0007] The general purpose of the present invention, which will be described subsequently in greater detail, is to provide a new signal flow driven circuit analysis and partitioning technique that has many of the advantages of the circuit analysis and partitioning mentioned heretofore and many novel features that result in a new signal flow driven circuit analysis and partitioning technique which is not anticipated, rendered obvious, suggested, or even implied by any of the prior art circuit analysis and partition, either alone or in any combination thereof. [0008] To attain this, the embodiments described herein generally cover automatic partitioning of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/radio frequency (RF) circuits, automatic identification of fundamental unit circuits, and the automatic identification of matching and symmetry requirements. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Automatically tracing the signal flow and identifying the critical path based on a set of rules achieve identification of the signal flow. Various building blocks of known characteristics and optimization requirements can also be automatically obtained. By tracing the signal path, matching and symmetry requirements and parasitic loading requirements at critical circuit nodes can also be automatically generated. [0009] There has thus been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof may be better understood, and in order that the present contribution to the art may be better appreciated. There are additional features of the invention that will be described hereinafter. [0010] In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of the description and should not be regarded as limiting. [0011] In one embodiment, a method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is then defined through the analog portion of the circuit netlist. [0012] In another embodiment, a system for characterizing a circuit design having an analog circuit portion and a digital circuit portion is provided. The system includes a signal flow tracking module configured to trace a signal flow through the analog circuit portion and a unit circuit module configured to characterize structure details associated with the signal flow through the analog circuit portion and determine if the characterized structure matches a unit circuit. [0013] Other objects and advantages of the present invention will become obvious to the reader and it is intended that these objects and advantages within the scope of the present invention. To the accomplishment of the above and related objects, this invention may be embodied in the form illustrated in the accompanying drawings, attention being called to the fact, however, that the drawings are illustrative only, and that changes may be made in the specific construction illustrated. BRIEF DESCRIPTION OF THE DRAWINGS [0014] Various other objects, features and attendant advantages of the present invention will become fully appreciated as the same becomes better understood when considered in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the several views. [0015] FIG. 1A is a high level schematic diagram of a simplified device having digital and analog circuitry in which a design for the device must be generated. [0016] FIG. 1B is a simplified schematic illustrating further details of a functional block of FIG. 1A. [0017] FIG. 2 is a simplified schematic diagram illustrating the conversion of a schematic diagram to a physical layout in accordance with one embodiment of the invention. [0018] FIG. 3 is a simplified schematic diagram of a functional block within an analog circuit in accordance with one embodiment of the invention. [0019] FIG. 4 is a simplified schematic diagram illustrating a system having the signal flow circuit analysis and partition logic in accordance with one embodiment of the invention. [0020] FIG. 5 is a flow chart diagram illustrating the method operations for a signal flow driven circuit analysis in accordance with one embodiment of the invention. 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