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  Shrinking key generator for parallel processUSPTO Application #: 20060133608Title: Shrinking key generator for parallel process Abstract: A parallel processing shrinking key generator is provided. The parallel processing shrinking key generator includes: a selection linear feedback shift register (LFSR); a source LFSR; a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal, and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter. (end of abstract)
Agent: Mayer, Brown, Rowe & Maw LLP - Washington, DC, US Inventors: Dong Soo Kim, Young Soo Kim, Dae Seon Park, Jang Hong Yoon USPTO Applicaton #: 20060133608 - Class: 380044000 (USPTO) Related Patent Categories: Cryptography, Key Management, Having Particular Key Generator The Patent Description & Claims data below is from USPTO Patent Application 20060133608. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a parallel processing shrinking key generator, and more particularly, to a shrinking key generator for providing a high speed key generation by configuring a parallel processing logic with a 2:1 multiplexer. [0003] 2. Description of the Related Art [0004] FIG. 1 is a block diagram illustrating a conventional shrinking key generator. [0005] As show in FIG. 1, the conventional shrinking key generator includes a selection linear feedback shift register (LFSR) 1 for shifting a selection bit according to an inputted clock signal (Clock); a source LFSR 2 for shifting a source bit according to the clock signal (Clock); a sequential processing logic 3 having a multiplexer 31 for sequentially processing the selection bit of the selection LFSR 1 and the source bit of the source LFSR 2, and logic elements 32, 33; and an output amount register 4 for storing output bits of the sequential processing logic 3. [0006] Hereinafter, operations of the conventional shrinking key generator will be explained in detail. [0007] The conventional sequential processing logic 3 is easy to be implemented as hardware but a speed of generating key in the conventional sequential processing logic 3 is unusually slow. However, a parallel processing logic according to the present invention may be difficult to be embodied as hardware but quickly generates a key. A parallel processing logic is embodied as hardware by combining logical elements, such as AND gate or OR gate, based on a Boolean Algebraic characteristic of a parallel processing algorithm. That is, a combinational logic is used for embodying the parallel processing logic. In case of a shrinking key generator, a non-boolean algebraic key generation algorithm is used. Since the non-boolean algebraic key generation algorithm does not have the boolean algebraic characteristic, it is impossible to use a parallel processing logic for embodying the shrinking key generator as hardware up to now. [0008] The shrinking key generator has been spotlighted as the most reliable algorithm for encoding/decoding data in a view of a security because there are no specific attacking methods reported or introduced. The shrinking key generator is generally selected when a high-speed key generation is not required. Although the shrinking key generator provides excellent reliability, the shrinking key generator is not selected for a system requiring an Mbps-level data processing speed because of slow speed of key generation. According to development of a wireless data link having wide-bandwidth and a fast Codec processing technology, a high-speed processing technology is also required for encoding and decoding data. [0009] Conventionally, Behavioral hardware description language (HDL) codes were not synthesized. According to development of a synthesis tool, many of Behavioral HDL codes, such as a conditional statement and a repetition statement, can be synthesized without problems. However, there are many difficulties still remained to synthesize Behavioral HDL codes, i.e., operation statements related to a pointer index, because of instabilities in an ineffective use of a Cell and a timing simulation. In order to express a selection logic of a shrinking key generator, operations related the pointer index and operations related to a dynamic memory assignment must be expressed as the Behavioral HDL codes by using the synthesis tool. Therefore, it is impossible to express the selection logic of the shrinking key generator having the non-boolean algebraic characteristic as HDL codes and to synthesize the HDL codes by using the synthesis tool. SUMMARY OF THE INVENTION [0010] Accordingly, the present invention is directed to a [title], which substantially obviates one or more problems due to limitations and disadvantages of the related art. [0011] It is an object of the present invention to provide a parallel-processing shrinking key generator for increasing a speed of key generation by configuring a parallel processing logic with a 2:1 multiplexer without using logical elements such as an AND gate or an OR gate. [0012] It is another object of the present invention to provide a parallel-processing shrinking key generator designed with a combinational logic by selecting a structural hardware description language (HDL) approach. [0013] It is a further another object of the present invention to provide a parallel-processing shrinking key generator including a combinational logic using a 2:1 multiplexer for including number of all cases and an index counter variably indexing a dynamic memory generated from a non-boolean algebraic. [0014] It is a still another object to the present invention to provide a parallel-processing shrinking key generator designed as a parallel processing logic based on 16 Bus bit and including a pipeline stage register between stages for solving a fan in & fan out problem. [0015] It is a further still another object of the present invention to provide a parallel-processing shrinking key generator including a combinational logic having: a counter logic varied according to the number of output bits of a selection logic; and a pushing logic and a through logic for expressing number of all cases by using a 2:1 multiplexer. [0016] It is a further still another object of the present invention to provide a parallel-processing shrinking key generator for increasing a speed of generating a key by designing a selection logic as a combinational logic capable of a parallel processing. For example, a speed of key generation in a conventional shrinking key generator is average 1 bit per 2 clocks. In the present invention, a speed of key generation is the number of bus bit per 2 clocks. If the number of bus bit is 16, the speed is 16 bits per 2 clocks. [0017] It is a further still another object of the present invention to provide a parallel-processing shrinking key generator for eliminating instabilities such as a fan-in & fan-out and a clock skew in order to reduce ineffective use of logic cell when a selection logic is synthesized to a Behavioral HDL code, and accurately estimate a result in a timing simulation. [0018] Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. [0019] To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a parallel processing shrinking key generator having a selection linear feedback shift register (LFSR), a source LFSR and an output amount register, the parallel processing shrinking key generator including: a selection logic circuit for selecting one of a source bit of the source LFSR and a predetermined input bit according to a selection bit of the selection LFSR; an index counter for assigning an index where output bits of the selection logic circuit are stored at a next clocking of a clock signal; and an output amount register for shifting an output bit of the selection logic circuit according to the assignment of the index counter. [0020] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS [0021] The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings: Continue reading... Full patent description for Shrinking key generator for parallel process Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Shrinking key generator for parallel process patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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