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Shallow trench isolation structures and a method for forming shallow trench isolation structuresRelated Patent Categories: Semiconductor Device Manufacturing: Process, Chemical Etching, Vapor Phase Etching (i.e., Dry Etching)Shallow trench isolation structures and a method for forming shallow trench isolation structures description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070066074, Shallow trench isolation structures and a method for forming shallow trench isolation structures. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to integrated circuits and more particularly to a method for forming a shallow trench isolation (STI) structure within an integrated circuit and to a shallow trench isolation structure formed according to the method. BACKGROUND OF THE INVENTION [0002] Integrated circuits (or chips) typically comprise a silicon substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. Interconnect structures disposed in parallel-like layers overlying the semiconductor substrate provide electrical connection between doped regions to form electrical devices and circuits. A conventional interconnect system comprises a plurality of substantially vertical conductive vias or plugs interconnecting substantially horizontal conductive traces or runners, with a dielectric layer disposed between two vertically adjacent horizontal conductive traces. [0003] Within an integrated circuit substrate, it may be necessary to isolate or separate certain doped regions to avoid the effects of parasitic devices that are formed by the interaction of adjacent doped regions. A CMOSFET device (complimentary metal-oxide semiconductor field effect transistor) comprises an n-channel and a p-channel metal-oxide semiconductor field effect transistor (MOSFET) formed in oppositely doped adjacent wells. The MOSFETS each further comprise source and drain regions separated by a channel, a silicon dioxide gate formed over the channel and a doped polysilicon gate electrode formed over the silicon dioxide gate. [0004] A parasitic bipolar structure, e.g., a p-n-p-n thyristor, is formed by the adjacent wells and the doped source/drain regions formed therein. The thyristor is inoperative (off) under normal CMOSFET operating conditions. However, under certain bias conditions the p-n-p regions supply base current to the n-p-n regions, causing a large leakage current between adjacent MOSFETS that can latch-up the CMOS device. Isolation structures are conventionally formed between adjacent MOSFETS to prevent leakage current flow. [0005] A thick oxide (silicon dioxide) region, formed according to a local oxidation of silicon (LOCOS) process or according to a shallow trench isolation (STI) process, electrically isolates adjacent transistors and their doped regions (and other devices formed in the integrated circuit) to minimize leakage current and reduce these parasitic effects. [0006] The local oxidation of silicon process forms recessed LOCOS isolation regions in non-active areas (also referred to as field regions) of the semiconductor substrate. For example, LOCOS regions are formed between the PMOSFET and NMOSFET devices of a CMOS device. According to a one LOCOS process, a layer of silicon nitride is deposited over the substrate and patterned according to conventional masking and etching steps to form openings that expose underlying silicon substrate regions. The isolating LOCOS regions are formed by oxidizing the exposed silicon through the openings. No oxidation occurs in the regions masked by the silicon nitride. [0007] An STI structure comprises a dielectric-filled substrate trench (about 3000 Angstroms deep) that electrically isolates doped regions of active devices, including CMOS devices, MOSFETS and bipolar junction transistors. Shallow trench isolation structures enjoy certain advantages over the LOCOS structures as the trenches consume a smaller surface area and exhibit a flatter upper surface topology than the LOCOS structures (which is beneficial for forming the subsequent overlying material layers). STI structures are especially useful for device sizes below about 0.25 microns. Since the shallow trench isolation structure consumes less substrate surface than the LOCOS structure, additional transistors per unit area can be fabricated in an integrated circuit employing STI isolation techniques. STI structures also provide superior isolation because sharp comers formed at the bottom of the STI trench create voltage barriers that tend to block leakage currents between adjacent doped regions. LOCOS regions generally present rounded corners and thus may permit some leakage current. [0008] As is known, a plurality of integrated circuits are fabricated in a semiconductor wafer, each integrated circuit comprising doped regions formed in a wafer substrate, with dielectric layers and conductive interconnect layers formed over an upper surface of the substrate. FIGS. 1-6 are cross-sectional views, not drawn to scale, illustrating successive prior art processing steps across a common plane for forming a shallow trench isolation structure in a substrate of one integrated circuit of the plurality of integrated circuits. [0009] A semiconductor substrate 30 in FIG. 1 comprises spaced-apart doped regions 32. It is desired to isolate the doped regions 32 with a shallow trench isolation structure therebetween. A stress-reducing silicon dioxide layer 36 (also referred to as a pad oxide layer 36) is deposited or grown over an upper surface 37 of the substrate 30. Next, a silicon nitride layer 38 is deposited (typically according to a low pressure chemical vapor deposition process) over the silicon dioxide layer 36. As is known, when a silicon nitride layer is formed directly on a substrate, it imposes stresses on the substrate, with the stresses increasing with increasing thickness of the silicon nitride layer. The pad oxide layer 36 isolates the substrate 30 from the silicon nitride layer 38 to reduce the effects of the stresses on the semiconductor substrate 30. [0010] A photoresist layer 40 is deposited, exposed and developed according to known processes to form an opening 41 therein. [0011] Using the photoresist layer 40 as an etch mask, an opening 46 (see FIG. 2) is formed in the silicon nitride layer 38 and the pad oxide layer 36, preferably using a plasma etching process. During the etching process, sidewalls 47 of the opening 46 are formed with a positive taper angle, i.e., the sidewalls 47 are inclined such that an opening size decreases in a direction toward a bottom surface of the opening. Typically, the etch process comprises a plasma etch during which oxygen and a fluorine-containing gas, such as C2F6 and/or CHF3, are supplied to the etch chamber at predetermined fixed flow rates while the chamber is maintained at a predetermined fixed pressure and input power. The CHF3 is conventionally used to etch the pad oxide layer 36, as it provides some selectivity to the underlying silicon of the silicon substrate 30. [0012] The photoresist layer 40 is removed and the wafer is cleaned. As shown in FIG. 3, using the opening 46 as a mask, a trench 48 is formed in the silicon substrate 30 during an etching step, conventionally comprising a plasma dry etch using a mixture of chlorine, in the form of CF2, and HBr. The positive taper angle in the sidewalls 47 of the opening 46 cause the formation of positively-tapered sidewalls 49. [0013] A trench silicon dioxide liner 50 is formed or deposited in the trench 48. See FIG. 4. [0014] As illustrated in FIG. 5, an STI structure 55 is formed within the trench 48 following a silicon dioxide deposition (e.g., a high density plasma oxide deposition), during which silicon dioxide is also deposited on an upper surface 59 of the silicon nitride layer 38. A chemical-mechanical polishing (CMP) step removes the silicon dioxide from the upper surface 59, stopping on the silicon nitride layer 38. Since the CMP polishing rate for silicon dioxide is greater than the CMP polishing rate for silicon nitride, an upper surface 60 of the STI structure 55 is recessed below the upper surface 59 of the silicon nitride layer 38. [0015] To complete formation of the STI structure 55, the wafer is cleaned, the silicon nitride layer 38 and the pad oxide layer 36 are removed using known processes and finally the wafer is cleaned again. FIG. 6 illustrates the structural elements following completion of these processing steps. [0016] As can be seen from FIG. 6, due to the positive taper angle of the sidewalls 47 and 49 (see FIG. 3) sidewalls 67 and 68 of the STI structure 55 form an acute angle with the upper surface 37. It is known that conventional cleaning steps following formation of the STI structure 55 may cause formation of a notch in regions 69 of the sidewalls 67 and 68. The positive taper angle of the sidewalls 67 and 68 together with the notches formed within the regions 69 may weaken the STI structure 55 and raise the possibility of damaging the STI structure 55 during subsequent processing steps. [0017] During deposition of a gate polysilicon layer on the upper surface 37, undesired polysilicon stringers can form around the sidewalls 67 and 68 and left and right comers 64 and 66 due to the positive taper angle profile of the sidewalls 67 and 68. The stringers may create short circuits that defeat the STI isolation function, thereby degrading performance of the integrated circuit. Thus a process technology and STI structure shape is desired that avoids formation of the polysilicon stringers. [0018] According to one technique, to reduce the probability of polysilicon stringers, it is known to minimize the formation of notches as described above by reducing a duration of a clean step (typically a hydrofluoric acid clean) that follows removal of the silicon nitride layer 38 and the pad oxide layer 36. However, it is also known that a shorter cleaning step causes nitride residues and contaminants to remain on the substrate 30, possibly causing undesirable short circuits or leakage current within the STI structure 55 and the substrate 30. [0019] To improve isolation between doped regions, it is desired that the STI structure extend slightly above (up to about 300 .ANG.) the upper surface 37 of the substrate 30. Thus it is not desired to form the STI structures flush with the upper surface 37. BRIEF SUMMARY OF THE INVENTION [0020] According to one embodiment, the present invention comprises a method for forming a shallow trench isolation structure in an integrated circuit. The method comprises providing a semiconductor layer; forming a material layer overlying the semiconductor layer; etching the material layer to form an opening therein, wherein sidewalls of the opening present a negative taper angle; etching the semiconductor layer through the material layer to form a trench in the semiconductor layer and forming insulating material in and above the trench, wherein sidewalls of the insulating material exhibit a negative taper angle above the semiconductor layer. [0021] According to another embodiment of the invention, a semiconductor device, comprises a semiconductor layer; a device isolation structure formed in the semiconductor layer, the device isolation structure further comprising: a trench disposed within the semiconductor layer; an insulating material disposed within the trench, an upper region of the insulating material extending above an upper surface of the semiconductor layer, the upper region having sidewalls presenting a negative taper angle with respect to the semiconductor layer and upper regions of the sidewalls comprising a material other than the insulating material. Continue reading about Shallow trench isolation structures and a method for forming shallow trench isolation structures... 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