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Serial data input/output method and apparatusRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Pulse Or Data Error Handling, Digital Logic TestingSerial data input/output method and apparatus description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070101217, Serial data input/output method and apparatus. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of application Ser. No. 10/695,606, filed Oct. 28, 2003, currently pending; [0002] Which was a divisional of application Ser. No. 09/718,206, filed Nov. 21, 2002, now U.S. Pat. No. 6,675,333; [0003] Which was a divisional of application Ser. No. 09/320,491, filed Mar. 26, 1999, now U.S. Pat. No. 6,158,035; [0004] which was a divisional of application Ser. No. 08/935,751, filed Sep. 23, 1997, now U.S. Pat. No. 6,085,344; [0005] which was a divisional of application Ser. No. 08/415,121, filed Mar. 29, 1995, now U.S. Pat. No. 5,687,179; [0006] which was a continuation of application Ser. No. 08/082,008, filed Jun. 24, 1993, now abandoned; [0007] which was a continuation of application Ser. No. 07/863,517, filed Mar. 31, 1992, now abandoned; [0008] which was a continuation of application Ser. No. 07/502,470, filed Mar. 30, 1990, now abandoned. Applicant claims priority from these applications. TECHNICAL FIELD OF THE INVENTION [0009] This invention relates in general to integrated circuits, and more particularly to serial data communication interfaces and architectures. BACKGROUND OF THE INVENTION [0010] Advance circuit design techniques have resulted in increasingly complex circuits, both at the integrated circuit and printed circuit board level of electronic design. Diminished physical access is an unfortunate consequence of denser designs and shrinking interconnect pitch. Testability is needed, so that the finished product is still both controllable and observable during test and debug. Any manufacturing defect is preferably detectable during final test before product is shipped. This basic necessity is difficult to achieve for complex designs without taking testability into account in the logic design phase, so that automatic test equipment can test the product. Exemplary test architectures are disclosed in U.S. patent application Ser. No. 07/391,751 (Atty. Docket No. TI-14158) and Ser. No. 07/391,801 (Atty. Docket No. TI14421), to Whetsel, both filed Aug. 9, 1989, and the entire issue of the Texas Instruments Technical Journal, Vol. 5, No. 4, all of which are incorporated by reference herein. [0011] Some existing test bus interfaces allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into a selected scan path of the integrated circuit once per shift operation. However, in some applications, it may be required to utilize a serial test bus to load or unload a local memory in the integrated circuit. Since memories contain multiple data storage locations, multiple data patterns must be input using multiple shift operations. As a result, transferring data patterns into or out of memory is extremely time consuming due to the multiple shift operations. [0012] Therefore, a need has arisen in the industry for a serial data input and output method which allows devices to be accessed in a more efficient manner than previously achieved. SUMMARY OF THE INVENTION [0013] In accordance with the present invention, a data communication interface is provided which substantially eliminates or prevents the disadvantages and problems associated with prior interface devices. [0014] In the present invention, a data communication interface is provided for communication with a device. The data communication device includes bus circuitry for transferring data, storage circuitry coupled to the device and to the bus circuitry, and test interface circuitry operable to shift data between the bus and the device. Device access control circuitry is operable to transfer data between the device and the storage circuitry responsive to a control signal. [0015] The present invention provides the technical advantage of allowing efficient communication with a device. The invention is compatible with existing interface structures and requires only minimal additional hardware. BRIEF DESCRIPTION OF THE DRAWINGS [0016] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0017] FIG. 1 illustrates a block diagram of a prior art test bus; [0018] FIG. 2 illustrates a Test Access Port (TAP) state diagram; [0019] FIG. 3 illustrates a shift path through multiple integrated circuits; [0020] FIG. 4 illustrates an integrated circuit structure with a more detail block diagram of a target integrated circuit therein; [0021] FIG. 5 illustrates a block diagram of the target integrated circuit of FIG. 4, including a memory access controller; [0022] FIG. 6 illustrates a block diagram of a memory access controller; [0023] FIG. 7 illustrates a block diagram of a header detector circuit which may be used in the memory access controller of FIG. 6; and [0024] FIG. 8 illustrate a block diagram of a counter circuit which may be used in the memory access controller of FIG. 6. DETAILED DESCRIPTION OF THE INVENTION [0025] The preferred embodiment of the present invention is best understood by referring to FIGS. 1-8 of the drawings, like numerals being used for like and corresponding parts of the various drawings. [0026] FIG. 1 illustrates a block diagram of prior art test bus and architecture 10. The architecture 10 includes TDI (test data input), TCK (test clock), and TMS (test mode select) inputs and a TDO (test data output) output. The TCK and TMS inputs are connected to a TAP (test access port) 12. The output of the TAP 12 is connected to data registers DREG1 14 and DREG2 16, bypass register 18 and instruction register IREG 20. The outputs of DREG1 14, DREG2 16 and bypass register 18 are connected to a first multiplexer 22. The output of the first multiplexer 22 and an output of the IREG 20 is connected to a second multiplexer 24. REG 20 is also connected to bypass register 18 and to the select port of the first multiplexer 22. The output of the TAP 12 is connected to IREG 20 and to the select port of the second multiplexer 24. The TDI input is connected to DREG1 14, DREG2 16, bypass register 18 and IREG 20. The output of the second multiplexer 24 is connected to the TDO output. The connection between the TAP 26 and DREGs 14 and 16, bypass register 18, IREG 20 and multiplexer 24 comprises a first control bus 28. The connections between IREG 20, bypass register 28 and first multiplexer 22 comprises a second control bus 28. Continue reading about Serial data input/output method and apparatus... Full patent description for Serial data input/output method and apparatus Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Serial data input/output method and apparatus patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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