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Sense amplifier systems and methodsSense amplifier systems and methods description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060209608, Sense amplifier systems and methods. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION DATA [0001] This application is a divisional of application Ser. No. 10/797,759, filed Mar. 9, 2004. TECHNICAL FIELD [0002] The present invention relates generally to electrical circuits and, more particularly, to sense amplifiers. BACKGROUND [0003] Sense amplifiers are employed in a variety of applications to monitor data signals and provide output signals based on the data signals. For example, a sense amplifier typically is utilized in a memory array to read data from one or more bitlines. The bitlines are generally routed from a memory cell in the memory array to the sense amplifier via column decode pass gates. The sense amplifier reads the data and provides its output, which completes the read process. [0004] One drawback of some conventional sense amplifier applications, such as for example for a memory array, is the relatively long time delay from the start of a read to the start of the next read (i.e., read cycle time). One technique to reduce the amount of time required to complete a read cycle is to precharge the bitlines prior to each read. However, typically there is still a relatively long read cycle time, especially with large memory arrays having significant signal propagation delays. As a result, there is a need for improved sense amplifier techniques. SUMMARY [0005] Systems and methods are disclosed herein to provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier is disclosed having an associated precharge circuit and a read completion detection circuit. The precharge circuit and the read completion detection circuit reduce the amount of time required to complete a read cycle as compared to some conventional sense amplifier circuits. Additional logic circuits may be provided to provide the desired application granularity so that the techniques disclosed herein may apply, for example, to one, four, eight, or more bits at a time. [0006] More specifically, in accordance with one embodiment of the present invention, a sense amplifier circuit includes a sense amplifier coupled to a first input line and a second input line and adapted to receive an enable signal, wherein the enable signal controls whether the sense amplifier is enabled; a first inverter coupled to the first input line and adapted to provide a first output signal; a second inverter coupled to the second input line and adapted to provide a second output signal; and a logic gate adapted to receive the first output signal and the second output signal and to provide a trip signal. [0007] In accordance with another embodiment of the present invention, a memory array includes a plurality of sense amplifiers adapted to read data provided on bitlines; a plurality of corresponding precharge circuits adapted to precharge the bitlines coupled to the sense amplifiers; a plurality of corresponding inverters coupled to the bitlines and adapted to provide output signals based on signal levels on the bitlines coupled to the sense amplifiers; a plurality of corresponding logic gates adapted to receive the output signals from the corresponding inverters and to provide trip signals based on the output signals; and a plurality of corresponding latches adapted to store the output signals from one of the corresponding inverters under control of the corresponding trip signals, wherein the trip signals transition to a first value if the corresponding bitlines are precharged and transition to a second value if the corresponding sense amplifiers read the data on the corresponding bitlines. [0008] In accordance with another embodiment of the present invention, a method of reading data from data lines includes disabling a sense amplifier coupled to the data lines; precharging the data lines; providing a first signal value via inverters coupled to the data lines about when the data lines are precharged; providing the data on the data lines about when the first signal value is provided; enabling the sense amplifier to read the data placed on the data lines about when the first signal value is provided; and providing a second signal value via the inverters coupled to the data lines about when the sense amplifier has read the data placed on the data lines. [0009] The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly. BRIEF DESCRIPTION OF THE DRAWINGS [0010] FIG. 1 shows a circuit diagram utilizing a sense amplifier in accordance with an embodiment of the present invention. [0011] FIG. 2 shows an exemplary circuit for a portion of the circuit diagram of FIG. 1 in accordance with an embodiment of the present invention. [0012] FIG. 3 shows an exemplary circuit for a portion of the circuit diagram of FIG. 1 in accordance with an embodiment of the present invention. [0013] FIG. 4 shows a block diagram of a sense amplifier application in accordance with an embodiment of the present invention. [0014] FIG. 5 shows a circuit diagram for a portion of the block diagram of FIG. 4 in accordance with an embodiment of the present invention. [0015] FIG. 6 shows a state diagram for the circuit diagram of FIG. 5 in accordance with an embodiment of the present invention. [0016] Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION [0017] FIG. 1 shows a circuit 100 in accordance with an embodiment of the present invention. Circuit 100 represents, for example, a portion of a memory array and illustrates certain aspects of the present invention. However, it should be understood that one or more of the techniques disclosed herein are applicable to a number of different types of sense amplifier applications, such as for example for sense amplifier applications within a product term circuit of a programmable logic device. [0018] Circuit 100 includes logic gates 102, 104, 106, and 108, precharge circuits 110 and 112, a sense amplifier 114, a latch 116, pass gates 122, and inverters 124 and 126. In terms of general operation, when a column select signal 128 and an enable signal 130 are asserted (e.g., a logical high level), logic gate 102 (e.g., a NAND gate) switches on pass gates 122, while logic gate 104 (e.g., a NAND gate) switches off precharge circuit 112 and switches on sense amplifier 114 via an enable signal 138 to initiate a read operation of bitlines 118 and 120 by sense amplifier 114. Continue reading about Sense amplifier systems and methods... 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