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12/29/05 - USPTO Class 438 | 27 views | #20050287733 | Prev - Next | About this Page

Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

Title: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), Including Isolation Structure, Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material, With Epitaxial Semiconductor Layer Formation

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20050287733, Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry.

1-50. (canceled)

51. A method of forming integrated circuitry, comprising: forming a plurality of spaced isolation regions in a substrate, the space between each pair of isolation regions comprising an active area width within the substrate, at least two active area widths being formed and comprising different active area widths; and fabricating a field effect transistor within each of the at least two active area widths, the field effect transistors comprising different threshold voltages which correspond to the different respective active area widths.

52. The method of claim 51, wherein the fabricating comprises forming at least one of the field effect transistors to have an active area width of less than one micron.

53. The method of claim 51, wherein the fabricating comprises forming the field effect transistors to have respective active area widths of less than one micron.

54. The method of claim 51, wherein the fabricating comprises fabricating using at least one common channel implant for the field effect transistors.

55. The method of claim 51, wherein the fabricating comprises fabricating using more than one common channel implant for the field effect transistors.

56. The method of claim 51, wherein the fabricating comprises fabricating using at least one common channel implant for the field effect transistors, and the at least one common channel implant comprises the only implant which defines the threshold voltage for the field effect transistors.

57. The method of claim 51, wherein the field effect transistors comprise the same conductivity type.

58. The method of claim 51, wherein the substrate comprises the same conductivity type.

Brief Patent Description - Full Patent Description - Patent Claims

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