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Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitryRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), Including Isolation Structure, Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material, With Epitaxial Semiconductor Layer FormationSemiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050287733, Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This invention relates to semiconductor processing methods of forming transistors, to semiconductor processing methods of forming dynamic random access memory circuitry, and to related integrated circuitry. BACKGROUND OF THE INVENTION [0002] Semiconductor processing typically involves a number of complicated steps which include patterning, etching, and doping or implanting steps, to name just a few, which are necessary to form desired integrated circuitry. One emphasis on improving the methods through which integrated circuitry is formed, and which is directed to reducing the processing complexity, relates to reducing the number of processing steps. By reducing the number of processing steps, risks associated with processing mistakes entering into the processing flow are reduced. Additionally, wherever possible, it is also highly desirable to reduce processing complexities while providing added flexibility in the processing itself. [0003] For example, several processing steps are required to form transistor constructions. One or more of these steps can include a threshold voltage definition step in which one or more channel implantation steps are conducted to define the threshold voltage for the ultimately formed transistor. In some applications, it is desirable to have transistors with different threshold voltages. Typically, different threshold voltages are provided by additional masking and doping or implanting steps to adjust the doping concentration within the channel region of the various transistors desired to have the different threshold voltage. Specifically, one transistor might be masked while another receives a threshold implant; and then other of the transistors might be masked while the first-masked transistor receives a threshold implant. [0004] This invention grew out of concerns associated with reducing the processing complexities involved in forming transistors having different threshold voltages. SUMMARY OF THE INVENTION [0005] Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. The transistor with the lower of the threshold voltages corresponds to the active area having the width less than one micron. [0006] In another embodiment, a plurality of shallow trench isolation (STI) regions are formed within a substrate and define a plurality of active areas having widths at least some of which are no greater than about one micron, with at least two of the widths preferably being different. A gate line is formed over the respective active areas to provide individual transistors, with the transistors -corresponding to the active areas having the different widths having different threshold voltages. In an STI process, devices having width smaller than 1 micron typically also have a lower threshold voltage. This is referred to as "reversed narrow width effect as contrasted with the case of transistors formed using LOCOS isolation, where threshold voltage tends to increase as device width decreases. [0007] In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other. [0008] In yet another embodiment, two series of field effect transistors are formed, with one series being isolated from adjacent devices by shallow trench isolation, the other series having active area widths greater than one micron. The one series is formed to have active area widths less than one micron to achieve lower threshold voltages than the other of the series. [0009] In yet another embodiment, one of the two series of field effect transistors are isolated- by shallow trench isolation, and different threshold voltages between the field effect transistors in different series are achieved by varying the active area widths of the field effect transistors in the series. At least one of the series preferably has active area widths less than one micron. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0011] FIG. 1 is a diagrammatic side sectional view of the semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0012] FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG. 1. [0013] FIG. 3 is a plan view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG. 2. [0014] FIG. 4 is a side view of the FIG. 3 wafer fragment. [0015] FIG. 5 is a schematic diagram of circuitry formed in accordance with another embodiment of the invention. [0016] FIG. 6 is a schematic diagram of circuitry formed in accordance with another embodiment of the invention. [0017] FIG. 7 is a schematic diagram of circuitry formed in accordance with another embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0018] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8). [0019] Referring to FIG. 1, a semiconductor wafer fragment in process is shown generally at 10, and includes a semiconductive substrate 12. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to, the semiconductive substrates described above. Continue reading about Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry... Full patent description for Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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