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  Semiconductor processing methods of forming integrated circuitryUSPTO Application #: 20060211207Title: Semiconductor processing methods of forming integrated circuitry Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages. (end of abstract) Agent: Wells St. John P.s. - Spokane, WA, US Inventor: Luan C. Tran USPTO Applicaton #: 20060211207 - Class: 438276000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Making Plural Insulated Gate Field Effect Transistors Of Differing Electrical Characteristics, Introducing A Dopant Into The Channel Region Of Selected Transistors The Patent Description & Claims data below is from USPTO Patent Application 20060211207. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This invention relates generally to semiconductor processing methods of forming integrated circuitry, and particularly to methods of forming integrated circuit devices having different threshold voltages. BACKGROUND OF THE INVENTION [0002] Field effect transistors are characterized by a source region, a drain region and a gate. The source and drain regions are typically received within a semiconductive material, such as a semiconductive substrate. The gate is typically disposed elevationally over the source and drain regions. A gate voltage of sufficient minimum magnitude can be placed on the gate to induce a channel region underneath the gate and between the source and drain regions. Such channel-inducing voltage is typically referred to as the transistor's threshold voltage, or V.sub.t. Accordingly, the threshold voltage turns the transistor on. Once the magnitude of the threshold voltage has been exceeded, current can flow between the source and drain regions in accordance with a voltage called the source/drain voltage, or V.sub.ds. [0003] Threshold voltage magnitudes can be affected by channel implants. Specifically, during fabrication of semiconductor devices, a substrate can be implanted with certain types of impurity to modify or change the threshold voltage of a resultant device. Such channel implants can also affect a condition known as subsurface punchthrough. Punchthrough is a phenomenon which is associated with a merging of the source and drain depletion regions within a MOSFET. Specifically, as the channel gets shorter (as device dimensions get smaller), depletion region edges get closer together. When the channel length is decreased to roughly the sum of the two junction depletion widths, punchthrough is established. Punchthrough is an undesired effect in MOSFETS. [0004] One way of addressing punchthrough in sub-micron devices is through provision of a so-called halo implant, also known as a "pocket" implant. Halo implants are formed by implanting dopants (opposite in type to that of the source and drain) within the substrate proximate the source and drain regions, and are typically disposed underneath the channel region. The implanted halo dopant raises the doping concentration only on the inside walls of the source/drain junctions, so that the channel length can be decreased without needing to use a higher doped substrate. That is, punchthrough does not set in until a shorter channel length because of the halo. [0005] It is desirable to have MOSFETS with different threshold voltages depending upon the context in which the integrated circuitry of which they comprise a part is to be used. In the context of memory devices it can be beneficial to have transistors with different threshold voltages. [0006] This invention arose out of concerns associated with improving the methods through which integrated circuits are fabricated. In particular, the invention arose concerns associated with providing improved methods of forming memory devices. SUMMARY OF THE INVENTION [0007] Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages. BRIEF DESCRIPTION OF THE DRAWINGS [0008] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0009] FIG. 1 is a diagrammatic side sectional view of a semiconductor wafer fragment in process, which is suitable for use in connection with one or more embodiments of the present invention. [0010] FIG. 2 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0011] FIG. 3 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0012] FIG. 4 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0013] FIG. 5 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0014] FIG. 6 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. [0015] FIG. 7 is a side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0016] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8). [0017] Referring to FIG. 1, a semiconductor wafer fragment in process is shown generally at 10 and includes a semiconductive substrate 12. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. [0018] Memory array circuitry 14 and peripheral circuitry 16 are formed over substrate 12. Memory circuitry 14 comprises individual transistors 20, 22. Peripheral circuitry 16 comprises a transistor 26. These transistors are shown for example only. Each exemplary transistor will typically include a conductive gate line 28 (designated for transistors 20 and 26 only) having a gate oxide layer 30, a polysilicon layer 32, a silicide layer 34, and an overlying insulative cap 36. Conventional sidewall spacers SS are optionally provided over the sidewalls of gate line 28. Of course, other gate line constructions could be used. Source/drain regions 37 and 38 are provided within substrate 12. [0019] The drain regions 37 may be formed in several different ways. In one embodiment, the drain regions 37 are doped first with a blanket n-minus implant, which may be performed before or after formation of the sidewalls SS. As used herein, the term "blanket implant" refers to an implant process that does not employ a masking step. In one embodiment, the drain regions 37 are doped by out-diffusion of dopants from a doped polysilicon layer forming a portion of a storage node 39. Continue reading... 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