| Semiconductor package suitable for high voltage applications -> Monitor Keywords |
|
|
 
Semiconductor package suitable for high voltage applicationsRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Lead FrameSemiconductor package suitable for high voltage applications description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070181984, Semiconductor package suitable for high voltage applications. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of U.S. application Ser. No. 10/762,075 filed Jan. 21, 2004, which claims the benefit of Korean Patent Application No. 2003-4025, filed on Jan. 21, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor package, and more particularly, to a semiconductor package suitable for high voltage applications. [0004] 2. Description of the Related Art [0005] Generally, semiconductor devices such as diodes, thyristors, or MOS gate devices, for example, metal-oxide-semiconductor field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT), are formed in a silicon semiconductor die including a device junction. The die includes a metal drain electrode at its lower portion, a metal source electrode, and a gate electrode. The die is attached to a surface of a leadframe pad, and electrodes are electrically connected to the leadframe by a wire bonding. Consequently, the electrodes are electrically connected to outer leads of the leadframe. The outer leads protrude out of a molded housing. The silicon semiconductor die and the wire are completely molded in the housing. [0006] Creepage distance is the distance along a path that begins at one exposed lead, travels along the surface of the one exposed lead and the package and ends at the adjacent exposed lead. In a semiconductor package having a structure in which outer leads protrude out of a molded housing, there must be enough creepage distance to ensure a high voltage. If the creepage distance is insufficient, it is well-known in the art that the maximum application voltage of the semiconductor package is limited. [0007] FIG. 1 is a plane view of an embodiment of a conventional semiconductor package having a structure ensuring a creepage distance as long as possible. FIGS. 2 and 3 are side views of the semiconductor package of FIG. 1. [0008] Referring to FIGS. 1 through 3, the conventional semiconductor package 20 includes a plastic molded housing 21. The molded housing 21 completely surrounds a semiconductor die 22 which is denoted by dotted line in FIG. 2. Three outer leads 25, 26, and 27 protrude out of front side surface 28 of the molded housing 21. The above outer leads may be a gate, a source, and a drain of the MOS transistor. The outer leads 25 and 27 disposed on an edge portion include bent portions 30 and 31 which increase spaces from the outer lead 26 on a center portion. The bent portion 30 of the outer lead 25 is bent toward a direction opposite to the outer lead 26, and accordingly, the creepage distance increases. The bent portion 31 of the outer lead 27 is bent toward a direction opposite to the outer lead 26, and therefore, the creepage distance also increases. [0009] Since the creepage distance between the outer leads can be increased, a higher voltage can be applied to the conventional semiconductor package. However, in order to ensure the longer creepage distance, side surface 28 in FIG. 3 of the molded housing, that is, a body of the package should be increased, and consequently, an entire size of the package increases. [0010] FIG. 4 is a plane view of another embodiment of the conventional semiconductor package having the structure ensuring the maximum creepage distance. FIG. 5 shows a configuration of an inner lead in the semiconductor package in FIG. 4. [0011] Referring to FIGS. 4 and 5, outer leads 45 and 47 of the conventional semiconductor package 40 are inclined toward directions opposite to a central outer lead 46 at the portions adjacent to a side surface 48 of the molded housing 41. Also, the molded housing has depressed structures between the outer lead 45 and the outer lead 46, and between the outer lead 47 and the outer lead 45. Inner leads 55, 56, and 57 extended from the outer leads 45, 46, and 47 and located in the molded housing 41 are connected to a leadframe pad 59 in the molded housing without any change in their structures. [0012] In the semiconductor package having the above structure, the creepage distance 52 between the outer lead 45 and the outer lead 46 increases, and the creepage distance 53 between the outer lead 47 and the outer lead 45 also increases. However, as in the semiconductor package of FIGS. 1 through 3, the side surface 48 of the molded housing, that is, the body of the package, should be increased to obtain larger creepage distance. Consequently, the entire size of the package increases. SUMMARY OF THE INVENTION [0013] The present invention provides a semiconductor package suitable for high voltage applications, having a structure in which a creepage distance between outer leads is increased without increasing a size of the semiconductor package. [0014] According to an aspect of the present invention, there is provided a semiconductor package in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extended from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, and second and third outer leads respectively disposed in a right and left portions of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. Also, at least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing. [0015] A portion where the first outer lead is adjacent to the side surface of the molded housing may be covered by the extended portion of the molded housing. In this case, a distance between a surface of the molded housing covering the portion of the first outer lead and a surface of the molded housing covering at least one of the bent portions of the second and third outer leads may be 1 mm or more. [0016] A depression toward a body of the molded housing may be formed on at least one of a surface of the molded housing between the first outer lead and the second outer lead and a surface of the molded housing between the first outer lead and the third outer lead. [0017] According to an aspect of the present invention, there is provided a semiconductor package in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extended from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each include inclinations in which a distance between the first outer lead and the inclinations becomes larger as a distance between the inclinations and the side surface of the molded housing becomes smaller. And at least one of the inclinations of the second and third outer leads is covered by an extended portion of the molded housing. [0018] A portion where the first outer lead is adjacent to the side surface of the molded housing may be covered by the extended portion of the molded housing. In this case, a distance between a surface of the molded housing covering the portion of the first outer lead and a surface of the molded housing covering at least one of the inclinations of the second and third outer leads may be 1 mm or more. [0019] A depression toward a body of the molded housing may be formed on at least one of a surface of the molded housing between the first outer lead and the second outer lead and a surface of the molded housing between the first outer lead and the third outer lead. [0020] At least one of the inclinations of the second and third outer leads may include a portion which is perpendicular to a surface of the molded housing and a flat portion which is larger than a thickness of the molded housing covering the inclinations in a boundary between the inclinations and the molded housing, BRIEF DESCRIPTION OF THE DRAWINGS [0021] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: Continue reading about Semiconductor package suitable for high voltage applications... Full patent description for Semiconductor package suitable for high voltage applications Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor package suitable for high voltage applications patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor package suitable for high voltage applications or other areas of interest. ### Previous Patent Application: Semiconductor device and manufacturing method thereof Next Patent Application: Substrate for device bonding and method for manufacturing same Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Semiconductor package suitable for high voltage applications patent info. IP-related news and info Results in 0.12299 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
