| Semiconductor package, stack package using the same package and method of fabricating the same -> Monitor Keywords |
|
|
 
Semiconductor package, stack package using the same package and method of fabricating the sameRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead, Bump Leads, Ball ShapedSemiconductor package, stack package using the same package and method of fabricating the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187827, Semiconductor package, stack package using the same package and method of fabricating the same. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY STATEMENT [0001] This application claims the benefit of Korean Patent Application No. 10-2005-0101755, filed on Oct. 27, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND [0002] 1. Field of the Invention [0003] Example embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor package that may be implemented in a stack package, a stack package using the same, and a method that may be implemented to fabricate the stack package. [0004] 2. Description of the Related Art [0005] A semiconductor package may be molded using an epoxy molding compound (EMC), for example, that may seal and/or protect a semiconductor chip with micro-circuits. An external terminal of the semiconductor chip may be electrically connected to the PCB through a wire, for example. [0006] Numerous attempts may have been pursued to miniaturize semiconductor packages. [0007] The components of a semiconductor package may be disposed close to each other and/or provided in a group. If numerous semiconductor chips are implemented, then various structures may be provided to reduce a space therebetween. Conventional structures may include a chip stack package and a stack package. In the chip stack package, a plurality of semiconductor chips may be implemented in an individual package. In the stack package, two or more unit semiconductor packages may be stacked together. [0008] FIG. 1 is a schematic sectional view of a conventional chip stack package. Here, a conductive bump 40 may be provided on a bottom of a PCB 10. A plurality of semiconductor chips 20 may be stacked on a top of the PCB 10. The semiconductor chips 20 may be sealed using a sealing material 30 (e.g., EMC). Although the chip stack package is generally thought to provide acceptable performance, it is not without shortcomings. For example, the chips 20 may be damaged during a stacking process, thereby reducing a production yield. [0009] A chip scale package (CSP) may provide a reduced package size and maintain the characteristics of a bare chip in a package state. A fine ball-grid array (FBGA) package is one example of a CSP. [0010] FIG. 2A is a schematic sectional view of a conventional stack package. Here, the stack package may include a second unit semiconductor package B that may be stacked on a first unit semiconductor package A. The first and the second unit semiconductor packages may include PCBs 10 and 10a, sealing materials 30 and 30a sealing a single chip (not shown), and conductive bumps 40. The first and the second unit semiconductor packages A and B (including the chips) may become warped during a stacking process (for example), as shown in phantom. Such warp may cause a defective adhesion of the conductive bumps 40 (e.g., non-wet) located within the stacked structure. [0011] FIG. 2B is a sectional view of another conventional stack package. The structure of FIG. 2B may be stronger than the structure illustrated in FIG. 2A. As shown, a substrate 80 may be disposed between the first unit semiconductor package A and the second unit semiconductor package B. The substrate 80 may reduce the package warp that might otherwise occur. A via hole (not shown) may be provided on the substrate 80. The unit packages A and B may be electrically connected to each other through a post that may be provided in the via hole. However, the structure shown in FIG. 2b may be difficult to manufacture and/or involve cumbersome processes. [0012] In the stack packages in FIGS. 2A and 2B, the sealing materials 30 and 30a may be provided on only a portion of the surface of the PCB that supports the chip. Further, the location of the conductive bumps 40 may be somewhat limited to the extent that the conductive bumps 40 may be positioned laterally outward of the sealing materials 30 and 30a to facilitate stacking. SUMMARY [0013] According to an example, non-limiting embodiment, a semiconductor package may include a substrate. A conductive bump may be provided on a bottom surface of the substrate. A semiconductor chip may be provided on a top surface of the substrate. A sealing material may seal the semiconductor chip. A first conductive adhesive may be provided on a top surface of the sealing material. A second conductive adhesive may be provided on a side surface of the printed circuit board and a side surface of the sealing material. [0014] According to another example, non-limiting embodiment, a method of fabricating a stack package may involve providing a frame having a top surface that may support a semiconductor chip and a sealing material that may seal the semiconductor chip. A first conductive adhesive may be provided on a top surface of the sealing material. A conductive bump may be provided on a bottom surface of the frame. A first semiconductor package may be separated from the frame. A second conductive adhesive may be provided on a side surface of the first semiconductor package to electrically connect the first conductive adhesive with the conductive bump. BRIEF DESCRIPTION OF THE DRAWINGS [0015] Example, non-limiting embodiments of the present invention will be described with reference to the attached drawings. [0016] FIG. 1 is a sectional view of a conventional chip stack package. [0017] FIGS. 2A and 2B are sectional views of conventional stack packages. [0018] FIGS. 3A and 3B are a plan view and a side view, respectively, of a semiconductor package according to an example, non-limiting embodiment of the present invention. [0019] FIG. 4 is a side view of a stack package according to another example, non-limiting embodiment of the present invention. [0020] FIG. 5 is a side view of stack package according to another example, non-limiting embodiment of the present invention. Continue reading about Semiconductor package, stack package using the same package and method of fabricating the same... Full patent description for Semiconductor package, stack package using the same package and method of fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor package, stack package using the same package and method of fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor package, stack package using the same package and method of fabricating the same or other areas of interest. ### Previous Patent Application: 3-d package stacking system Next Patent Application: Ild layer with intermediate dielectric constant material immediately below silicon dioxide based ild layer Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Semiconductor package, stack package using the same package and method of fabricating the same patent info. IP-related news and info Results in 0.1365 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
