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  Semiconductor memory device and method of manufacturing the sameUSPTO Application #: 20060240619Title: Semiconductor memory device and method of manufacturing the same Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film. (end of abstract) Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP - Washington, DC, US Inventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa USPTO Applicaton #: 20060240619 - Class: 438257000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate) The Patent Description & Claims data below is from USPTO Patent Application 20060240619. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-128232, filed Apr. 26, 2005, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor memory device including a floating gate electrode and control gate electrode, and a method of manufacturing the same. [0004] 2. Description of the Related Art [0005] Conventionally, a nonvolatile semiconductor memory device including a floating gate electrode FG and control gate electrode CG has been proposed as a semiconductor memory. [0006] In this nonvolatile semiconductor memory device, as shown in FIG. 19, a floating gate electrode FG, interelectrode insulating film 208, and control gate electrode CG are processed into a desired shape, and a gate sidewall oxide film 212 is formed on the entire surface by oxidation after that. When the gate sidewall oxide film 212 is formed, however, thick so-called "bird's beak" oxidation regions 213 are formed in the upper and lower end portions of the interelectrode insulating film 208. This decreases the electric capacitance of the interelectrode insulating film 208, and causes faulty operations of the memory device. These problems caused by the formation of the bird's beak oxidation regions 213 similarly arise when a high-k oxide film such as a hafnium oxide film, zirconium oxide film, or tantalum oxide film, or an insulating film obtained by adding an impurity to a high-k oxide film like this is used as the interelectrode insulating film 208. [0007] As a method of avoiding the formation of the bird's beaks described above, a technique as shown in FIGS. 20A and 20B is disclosed (e.g., Jpn. Pat. Appln. KOKAI Publication No. 7-249697, 8-153814, or 9-219459). In this technique, silicon nitride layers 231 and 232 are formed in the upper and lower interfaces of an interelectrode insulating film 208, thereby preventing the penetration of an oxidation species during gate sidewall oxidation and preventing the formation of bird's beaks. [0008] This technique discloses CVD (Chemical Vapor Deposition) or thermal nitriding as the method of forming the silicon nitride layers 231 and 232. However, the following problems arise if the silicon nitride layers 231 and 232 are formed by using CVD or thermal nitriding. [0009] When CVD is used, the total physical film thickness of an interelectrode insulating film 208a between a control gate electrode CG and floating gate electrode FG increases. Therefore, as shown in FIG. 20B, the depth P of the control gate electrode CG buried between adjacent cells decreases. This decreases the capacitance of the interelectrode insulating film 208 and increases the parasitic capacitance between the adjacent cells, so the memory device suffers faulty operation. In addition, the width Q of the control gate electrode CG buried between the adjacent cells decreases. Since this depletes the buried portion of the control gate electrode CG, the memory device suffers faulty operation. Furthermore, if the depth P is well increased, the distance R between a substrate 201 and the interelectrode insulating film 208 shortens. This decreases the breakdown voltage between the substrate 201 and control gate electrode CG, so the memory device suffers faulty operation. These problems are significant when the depth P, width Q, and distance R are approximately 100 nm or less. [0010] On the other hand, when thermal nitriding is used, a high-temperature, long-time thermal budget is necessary to form silicon nitride layers 231 and 232 having a thickness which prevents the formation of bird's beaks. Since this degrades the quality of a tunnel oxide film 202, the reliability of the memory device is also degraded. BRIEF SUMMARY OF THE INVENTION [0011] A semiconductor memory device according to a first aspect of the present invention comprises a semiconductor substrate, a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, and having a first side-surface portion positioned in an upper portion and a second side-surface portion positioned below the first side-surface portion, an element isolation trench formed in the semiconductor substrate to be adjacent to the floating gate electrode, a first element isolation insulating film formed along a side surface and bottom surface of the element isolation trench from the second side-surface portion of the floating gate electrode, a second element isolation insulating film formed on the first element isolation insulating film to expose a side-surface portion in an upper portion of the first element isolation insulating film, a first radical nitride film formed on the floating gate electrode and first and second element isolation insulating films, an interelectrode insulating film formed on the first radical nitride film, a nitrogen-containing film formed on the interelectrode insulating film, and a control gate electrode formed on the nitrogen-containing film, wherein in the second side-surface portion of the floating gate electrode, a portion of the first element isolation insulating film exists between the floating gate electrode and first radical nitride film. [0012] A semiconductor memory device manufacturing method according to a second aspect of the present invention comprises forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING [0013] FIGS. 1A and 1B are sectional views in the bit line direction and word line direction, respectively, showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention; [0014] FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A and 7B are sectional views in the bit line direction and word line direction, respectively, showing the manufacturing steps of the nonvolatile semiconductor memory device according to the first embodiment of the present invention; [0015] FIGS. 8A and 8B are sectional views in the bit line direction and word line direction, respectively, showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention; [0016] FIGS. 9A, 9B, 10A, 10B, 11A, 11B, 12A and 12B are sectional views in the bit line direction and word line direction, respectively, showing the manufacturing steps of the nonvolatile semiconductor memory device according to the second embodiment of the present invention; [0017] FIG. 13 is a sectional view showing a nonvolatile semiconductor memory device according to a third embodiment of the present invention; [0018] FIG. 14 is a sectional view showing a nonvolatile semiconductor memory device of means example 1 according to the third embodiment of the present invention; [0019] FIGS. 15, 16 and 17 are sectional views showing the manufacturing steps of the nonvolatile semiconductor memory device of means example 1 according to the third embodiment of the present invention; [0020] FIG. 18 is a graph showing the film thinning ratio and radical nitriding rate as functions of the radical nitriding pressure according to means example 2 of the third embodiment of the present invention; Continue reading... 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