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  Semiconductor memory device and manufacturing method of the sameUSPTO Application #: 20080023743Title: Semiconductor memory device and manufacturing method of the same Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure. (end of abstract) Agent: Mcdermott Will & Emery LLP - Washington, DC, US Inventors: Masakazu Hirose, Fukashi Morishita USPTO Applicaton #: 20080023743 - Class: 257296000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) The Patent Description & Claims data below is from USPTO Patent Application 20080023743. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to a semiconductor memory device and a manufacturing method of the same. More particularly, the present invention relates to a semiconductor memory device enabling microfabrication of the semiconductor memory device and improvement in performance thereof, and a manufacturing method of the same. [0003] 2. Description of the Background Art [0004] A conventional DRAM (Dynamic Random Access Memory) cell formed in a SOI (Silicon On Insulator) structure will now be described with reference to FIG. 14. [0005] An insulation layer 2 is formed on a p-type first semiconductor layer 1. A p-type second semiconductor layer 3 is formed on the insulation layer 2. A body portion 4, a first impurity region 6, a second impurity region 7, and an isolation region 8 are provided in the second semiconductor layer 3. The first impurity region 6 and the second impurity region 7 interpose the body portion 4 therebetween. [0006] A word line 10 is formed above the body portion 4 with a gate insulation film 9 interposed therebetween. A bit line 13 is connected to the first impurity region 6 through a wiring layer 12. A cylindrical storage node 14 is connected to the second impurity region 7. A dielectric film 15 is formed along the surface of the storage node 14. A cell plate 16 is formed in the cylindrical portion of the storage node 14 with the dielectric film 15 interposed therebetween. The storage node 14, the dielectric film 15 and the cell plate 16 form a capacitor. The second semiconductor layer 3 is covered with an interlayer insulation film 11. [0007] Hereinafter, a method for manufacturing a DRAM cell having the above structure will be described briefly with reference to FIGS. 15 to 17. A SIMOX (Separation by IMplanted OXygen) method is known as a process for forming the SOI structure. However, there is a limit in the SIMOX method in terms of microfabrication. A lamination method is also known as a process for forming the SOI structure. A method for manufacturing a DRAM cell by using the lamination method will now be described. [0008] Referring to FIG. 15, the surface of a first semiconductor substrate 1A is oxidized to form the insulation layer 2. Referring to FIG. 16, a second semiconductor substrate 1B is then laminated to the first semiconductor substrate 1A with the insulation layer 2 interposed therebetween. [0009] Referring to FIG. 17, a surface of the first semiconductor substrate 1A located opposite to that facing the second semiconductor substrate 1B is removed. As a result, the first semiconductor layer 1 and the second semiconductor layer 3 are formed. The first semiconductor layer 1 is formed from the second semiconductor substrate 1B, and the second semiconductor layer 3 is formed from the first semiconductor substrate 1A. By using known technology, a semiconductor storage element is then formed on the surface of the first semiconductor substrate 1A exposed as a result of removing the surface of the first semiconductor substrate 1A. [0010] The DRAM cell in the SOI structure thus formed has the following advantages: [0011] (1) A small junction area between the storage node 14 and the substrate reduces junction leakage, resulting in improved pause refresh characteristics; [0012] (2) A small junction capacity of the bit line 13 reduces the bit-line capacity (CB), allowing for an increased read margin; [0013] (3) A small parasitic capacitance of the wirings enables high-speed operation; [0014] (4) Excellent sub-threshold characteristics and a small substrate effect enable low-voltage operation; and [0015] (5) Very good soft-error resistance. [0016] Thus, producing the DRAM cell in the SOI structure enables manufacturing of a low power consumption DRAM having a long data holding time and capable of implementing high-speed operation even with a low voltage. [0017] However, when the DRAM cell is produced in the SOI structure, the potential of the body portion in the SOI structure is in a floating state. Therefore, holes generated near the drain by impact ionization are accumulated in the floating region under the body portion. The holes thus accumulated raise a lead electrode, increasing sub-threshold leakage. Such a body floating effect degrades disturb refresh characteristics. [0018] Accordingly, the body portion must have a fixed potential. In order to fix the potential of the body portion, an active region 4A for a body contact 30 must be added (enlarged) in the memory cell layout, as shown in FIGS. 18A and 18B. This increases the layout area as compared to the case where the DRAM memory cell is produced with a bulk structure. [0019] Moreover, a DRAM cell must be produced by using a method for reducing sub-threshold leakage in order to prevent degradation in disturb refresh characteristics. Examples of the method for reducing sub-threshold leakage are as follows: [0020] (1) Negative-Voltage Word Line Method [0021] In this method, an inactive access transistor (a DRAM memory cell transistor) has a potential lower than 0 V so that the gate-source voltage VGS of the access transistor becomes negative. The sub-threshold leakage is thus reduced. [0022] (2) Boosted Sense Ground Method [0023] In this method, the ground voltage VSS of a sense amplifier is a positive voltage so that the gate-source voltage VGS of an inactive access transistor becomes negative. The sub-threshold leakage is thus reduced. Continue reading... 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