| Semiconductor integrated circuits with stacked node contact structures -> Monitor Keywords |
|
|
  Semiconductor integrated circuits with stacked node contact structuresUSPTO Application #: 20080023728Title: Semiconductor integrated circuits with stacked node contact structures Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers. (end of abstract) Agent: Myers Bigel Sibley & Sajovec - Raleigh, NC, US Inventors: Jae-Hoon Jang, Soon-Moon Jung, Kun-Ho Kwak, Byung-Jun Hwang USPTO Applicaton #: 20080023728 - Class: 257208000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Gate Arrays, With Particular Signal Path Connections The Patent Description & Claims data below is from USPTO Patent Application 20080023728. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims priority under 35 U.S.C, .sctn. 120 from U.S. patent application Ser. No. 11/033,432, filed on Jan. 11, 2005, which in turn claims priority under 35 U.S.C. .sctn. 119 from Korean Patent Application No. 2004-0002088, filed on Jan. 12, 2004, the disclosures of each of which are incorporated herein by reference as if set forth in there entireties. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor integrated circuits and, more particularly, to contact structures for semiconductor integrated circuits. BACKGROUND OF THE INVENTION [0003] As is known by those of skill in the art, static random access memory (SRAM) integrated circuits may exhibit relatively low power consumption and high operating speeds as compared to dynamic random access memory (DRAM) integrated circuits. As a result, SRAM circuits are widely used to implement cache memories in computers and portable consumer electronic devices. [0004] The unit cells of an SRAM integrated circuit can be implemented, for example, as either a high load resistor SRAM cell or as a complementary metal oxide semiconductor (CMOS) SRAM cell. Typically, the high load resistor SRAM cells use a high resistance resistor as the load device, and the CMOS SRAM cells use a p-channel or "p-type" metal oxide semiconductor (PMOS) transistor as the load device. [0005] At least two types of CMOS SRAM unit cells are known in the art. The first type is a thin film transistor (TFT) SRAM cell in which thin film transistors are stacked on a semiconductor substrate as the load device. The second type of CMOS SRAM unit cell is a bulk CMOS SRAM cell that uses bulk transistors that are formed at a semiconductor substrate as the load device. [0006] The bulk CMOS SRAM cells may exhibit high cell stability (i.e., good low voltage characteristics and low stand-by current) as compared to TFT SRAM cells and high-load resistor SRAM cells. This high degree of cell stability may be achieved because the bulk transistors in the bulk CMOS SRAM cell are formed at a single crystalline silicon substrate, whereas the thin film transistors of the TFT SRAM cells are typically formed using polysilicon layers. However, bulk CMOS SRAM cells may exhibit low integration density and/or weak latch-up immunity as compared to TFT SRAM cells. [0007] Typically, each SRAM unit cell includes a pair of node contact structures. In the TFT SRAM cells, each of the node contact structures electrically connects a P-type drain region of the load transistor to an N-type drain region of a driver transistor. Typically, an ohmic contact is provided between the P-type drain region of the load transistor and the N-type drain region of the driver transistor. [0008] Semiconductor devices that include TFTs stacked over a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766 to Chen et al., entitled "Semiconductor Structure Incorporating Thin Film Transistors and Methods for Its Manufacture." In particular, Chen et al. discloses a semiconductor device in which a conventional bulk transistor is formed at a single crystalline silicon substrate, and a thin film transistor is then stacked over the bulk transistor. In Chen et al., the body layer of the TFT is formed by depositing an amorphous silicon layer on the semiconductor substrate and a metal plug. This amorphous silicon layer is then crystallized via a thermal treatment process. This thermal treatment process converts the amorphous silicon layer into a polycrystalline or "polysilicon" layer having large grains. The electrical characteristics of these TFTs that are formed with a polysilicon body layer may not be as good as the electrical characteristics of bulk transistors formed at a single crystalline silicon substrate. SUMMARY OF THE INVENTION [0009] Pursuant to embodiments of the present invention, integrated circuits are provided which include a first transistor having first and second impurity regions that is formed at a semiconductor substrate. A first interlayer insulating layer is on the first transistor, and a second transistor having first and second impurity regions is on the first interlayer insulating layer opposite the first transistor. A second interlayer insulating layer is on the second transistor opposite the first interlayer insulating layer, and a third transistor having first and second impurity regions is on the second interlayer insulating layer opposite the second transistor. Finally, a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer. The integrated circuit further includes a node plug that penetrates the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another. [0010] In certain embodiments of the present invention, the second transistor may overlap the first transistor, and the third transistor may overlap the second transistor. The first transistor may be a bulk transistor whereas the second and third transistors are thin film transistors. The second and third transistors may be single crystalline thin film transistors. In specific embodiments, the integrated circuit may further include a lower node semiconductor plug that is between the first impurity region of the second transistor and the first impurity region of the first transistor and an upper node semiconductor plug that is between the first impurity region of the third transistor and the first impurity region of the second transistor. In these embodiments, the node plug may also be electrically connected to the lower and upper node semiconductor plugs. The lower and upper node semiconductor plugs may be single crystalline semiconductor plugs. The node plug may be a metal plug such as, for example, a tungsten plug or a tungsten plug with a surrounding metal barrier layer. Corresponding methods of fabricating such devices are also provided. [0011] Pursuant to further embodiments of the present invention, static random access memory (SRAM) cells are provided which include first and second bulk transistors which are formed at least partially in a semiconductor substrate. A first interlayer insulating layer is provided on the first and second bulk transistors, and first and second lower thin film transistors are provided on the first interlayer insulating layer. A second interlayer insulating layer is provided on the first and second lower thin film transistors, and a first and second upper thin film transistors are provided on the second interlayer insulating layer. A third interlayer insulating layer is provided on the first and second upper thin film transistors. A first node plug is provided that penetrates the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another. Finally, a second node plug is provided that penetrates the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another. [0012] In certain embodiments of the present invention, the first lower thin film transistor may overlap the first bulk transistor and the second lower thin film transistor may overlap the second bulk transistor. Likewise, the first upper thin film transistor may overlap the first lower thin film transistor and the second upper thin film transistor may overlap the second lower thin film transistor. The first and second lower thin film transistors and the first and second upper thin film transistors may each be single crystalline thin film transistors. [0013] In embodiments of the present invention, the SRAM cell may also include a first lower node semiconductor plug that is between the first impurity region of the first lower thin film transistor and the first impurity region of the first bulk transistor and a first upper node semiconductor plug that is between the first impurity region of the first upper thin film transistor and the first impurity region of the first lower thin film transistor. The SRAM cell may further include a second lower node semiconductor plug that is between the first impurity region of the second lower thin film transistor and the first impurity region of the second bulk transistor and a second upper node semiconductor plug that is between the first impurity region of the second upper thin film transistor and the first impurity region of the second lower thin film transistor. In these embodiments, the first node plug may be electrically connected to the first lower node semiconductor plug and the first tipper node semiconductor plug, and the second node plug may be electrically connected to the second lower node semiconductor plug and the second upper node semiconductor plug. The first and second upper node semiconductor plugs and the first and second lower node semiconductor plugs may each be single crystalline semiconductor plugs. The first and second node plugs may be metal plugs such as, for example, tungsten plugs or tungsten plugs with a surrounding barrier metal layer. [0014] The first lower node semiconductor plug may have the same conductivity type as the first impurity region of the first bulk transistor and the second lower node semiconductor plug may have the same conductivity type as the first impurity region of the second bulk transistor. In other embodiments, the first lower node semiconductor plug may have a different conductivity type than does the first impurity region of the first bulk transistor, and the second lower node semiconductor plug may have a different conductivity type than does the first impurity region of the second bulk transistor. In these embodiments, the first node plug may be in direct contact with the first impurity region of the first bulk transistor and the second node plug may be in direct contact with the first impurity region of the second bulk transistor. [0015] In certain embodiments of the SRAM cell, the first and second bulk transistors may be first and second N-channel driver transistors, respectively, where the first impurity region of the first and second bulk transistors are each drain regions. The gate electrode of the first N-channel driver may be electrically connected to the second node plug, and the gate electrode of the second N-channel driver may be electrically connected to the first node plug. The first and second lower thin film transistors may be first and second P-channel load transistors, respectively, and the first and second upper thin film transistors may be first and second N-channel transfer transistors, respectively. The first impurity region of the first and second lower thin film transistor may each be drain regions, and the first impurity region of the first and second upper thin film transistors may each be source regions. The gate electrode of the first P-channel load transistor may be electrically connected to the second node plug and the gate electrode of the second P-channel load transistor may be electrically connected to the first node plug. The gate electrodes of the first and second N-channel transfer transistors may be electrically connected to each other to act as a word line. [0016] In the above-mentioned embodiments, the SRAM cell may also include a ground line that is electrically connected to the source regions of the first and second N-channel driver transistors and a power line that is electrically connected to the source regions of the first and second P-channel load transistors. The SRAM cell may further include a first bit line that is electrically connected to the drain region of the first N-channel transfer transistor and a second bit line that is electrically connected to the drain region of the second N-channel transfer transistor. The first bit line may be substantially perpendicular to a gate electrode of the first N-channel driver transistor, a gate electrode of the first P-channel load transistor and a gate electrode of the first N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate, and the second bit line may be substantially perpendicular to a gate electrode of the second N-channel driver transistor, a rate electrode of the second P-channel load transistor and a gate electrode of the second N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate. [0017] In other embodiments of the present invention, the first and second lower thin film transistors may be first and second N-channel transfer transistors, respectively, and the first and second upper thin film transistors may be first and second P-channel load transistors, respectively. [0018] In still further embodiments of the present invention, static random access memory (SRAM) cells are provided that include an isolation layer in a semiconductor substrate that defines first and second active regions. First and second bulk transistors are provided at least partially in the first and second active regions, respectively. A first interlayer insulating layer is provided on the first and second bulk transistors, and first and second single crystalline lower body patterns are provided on the first interlayer insulating layer. First and second lower thin film transistors are provided at the first and second lower body patterns, respectively, and a second interlayer insulating layer is provided on the first and second lower thin film transistors. First and second single crystalline upper body patterns are provided on the second interlayer insulating layer, and first and second upper thin film transistors are provided at the first and second upper body patterns, respectively. A third interlayer insulating layer is provided on the first and second upper thin film transistors. A first node plug is provided that penetrates the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another, and a second node plug is provided that penetrates the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another. [0019] In certain embodiments of these SRAM cells, the first and second bulk transistors may be respective first and second N-channel driver transistors. The first impurity region of each of the first and second bulk transistors may be a drain region. The gate electrode of the first N-channel driver transistor may be electrically connected to the second node plug, and the gate electrode of the second N-channel driver transistor may be electrically connected to the first node plug. The first and second lower thin film transistors may be respective first and second P-channel load transistors, and the first and second upper thin film transistors may be respective first and second N-channel transfer transistors. The first impurity region of the first and second lower thin film transistors may be drain regions and the first impurity region of the first and second upper thin film transistors may be source regions. [0020] The SRAM cell may also include a first ground active region that extends from a first end of the first active region in a direction perpendicular to the first active region and a second ground active region that extends from a first end of the second active region in a direction perpendicular to the second active region. Continue reading... Full patent description for Semiconductor integrated circuits with stacked node contact structures Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor integrated circuits with stacked node contact structures patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor integrated circuits with stacked node contact structures or other areas of interest. ### Previous Patent Application: Schottky gate metallization for semiconductor devices Next Patent Application: Solid-state image sensor Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Semiconductor integrated circuits with stacked node contact structures patent info. IP-related news and info Results in 4.60703 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , |
||
