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  Semiconductor imaging device and fabrication process thereofUSPTO Application #: 20070023800Title: Semiconductor imaging device and fabrication process thereof Abstract: A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate and such that an inner edge part invades underneath a channel region right underneath the gate electrode, a shielding layer formed of a second conductivity type at a surface of the silicon substrate at the first side of the gate electrode such that an inner edge part thereof is aligned with a sidewall surface of the gate electrode at the first side, a floating diffusion region formed in the active region at a second side of the gate electrode, and a channel region formed right underneath said gate electrode, wherein the channel region includes a first channel region part formed adjacent to the shielding layer and a second channel region part formed adjacent to the floating diffusion region, wherein the second channel region part contains an impurity element with a concentration level lower than the impurity concentration level of the first channel region part. (end of abstract)
Agent: Westerman, Hattori, Daniels & Adrian, LLP - Washington, DC, US Inventor: Narumi Ohkawa USPTO Applicaton #: 20070023800 - Class: 257292000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Light Responsive Or Combined With Light Responsive Device, Imaging Array, Photodiodes Accessed By Fets The Patent Description & Claims data below is from USPTO Patent Application 20070023800. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application is based on Japanese priority application No. 2005-220131 filed on Jul. 29, 2005, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION [0002] The present invention generally relates to semiconductor devices and more particularly to a semiconductor photodetection device constituting a CMOS imaging apparatus. [0003] Today, CMOS imaging apparatuses are used extensively in cellular phones with camera, digital still cameras, and the like. A CMOS imaging apparatus has an advantageous feature over a CCD imaging apparatus in that the construction thereof is simple and can be produced with low cost. [0004] FIG. 1 shows the construction of such a CMOS imaging apparatus 100. [0005] Referring to FIG. 1, the CMOS imaging apparatus 100 includes a photodetection region 101A in which a large number of CMOS pixel elements 10 are arranged in rows and columns, wherein a row selection circuit 101B and a signal reading circuit 101C are provided so as to cooperate with the CMOS pixel elements 10 in the photodetection region 101A. Here, the row selection circuit 101B selects a transfer control line TG, a reset control line RST and a selection control line SEL of a desired CMOS pixel element 10, while the signal reading circuit 101C supplies a reset voltage to the reset voltage line VR and reads out the signal voltage from the pixel, which is output to the signal reading line SIG. [0006] FIG. 2 shows the construction of the CMOS device 10 for one pixel used in the CMOS imaging apparatus 100 of FIG. 1. [0007] Referring to FIG. 2, a photodiode 10D is connected to a power supply terminal 10A connected to the reset voltage line VR and supplied with a reset voltage, wherein the photodiode 10D is connected to the power supply terminal 10A in a reverse bias state via a reset transistor 10B controlled by a reset signal on the reset control line RST and a transfer gate transistor 10C controlled by a transfer control signal on the transfer control line TG. Thereby, the photoelectrons formed by optical irradiation in the photodiode 10D are accumulated in a floating diffusion region FD forming an intermediate node between the reset transistor 10B and the transfer gate transistor 10C. Thereby, the photoelectrons are converted to voltage in the floating diffusion region FD. [0008] In the construction of FIG. 2, a voltage signal thus formed in the floating diffusion region FD in response to the photoelectrons from the photodiode 10D is taken over by a reading transistor 10F driven by a supply voltage from the power supply terminal 10A, wherein the reading transistor 10F forms a source follower circuit and supplies an output signal to the signal line SIG via a select transistor 10S connected in series to the reading transistor 10F. The select transistor 10S is controlled by a selection control signal on the selection control line SEL and the output of the read transistor 10F is obtained on the signal line SIG in response to activation of the select transistor 10S via the selection control signal on the selection control line SEL. [0009] FIG. 3 is a diagram explaining the operation of the CMOS pixel element 10 of FIG. 2. [0010] Referring to FIG. 3, the selection control signal on the selection control line SEL rises first, and a row of CMOS pixel elements including the desired CMOS pixel element is selected as a result of conduction of the select transistor 10S. [0011] Next, the reset signal on the reset control line RST goes high, causing conduction of the reset transistor 10B. With this, the floating diffusion region FD is charged to a initial state (resetting). In this stage, it should be noted that the transfer gate transistor 10C is turned off. In response to the rising of the reset signal, the potential of the floating diffusion region FD rises at the same time, and the effect of this rising potential of the floating diffusion region FD is transferred also to the signal line SIG via the reading transistor 10F and the select transistor 10S in the conduction state, while it should be noted that this rising of the signal line SIG is not used for reading of the signal. [0012] Next, the reset signal goes low, and the potential of the floating diffusion region FD is read out to the signal line SIG by the reading transistor 10F while maintaining the transfer gate transistor 10C in the turned off state. With this, reading of noise level is achieved. [0013] Further, after the foregoing noise level reading, the transfer control signal on the transfer control line TG goes high and the electric charges accumulated inside the photodiode 10D are transferred to the floating diffusion region 10F via the transfer gate transistor 10C. Thereby, the potential of the floating diffusion region 10F changes by .DELTA.V=Q/C by the transferred electric charge amount Q where C is the capacitance of the floating diffusion region FD. Thus, after the transfer control signal goes low, the potential of the floating diffusion region 10F is read out by the reading transistor 10F and is output to the signal line SIG via the select transistor 10S. REFERENCES [0014] Patent Reference 1 Japanese Laid-Open Patent Application 11-274450 official gazette [0015] Patent Reference 2 Japanese Laid-Open Patent Application 2001-15727 official gazette [0016] Patent Reference 3 Japanese Laid-Open Patent Application 11-284166 official gazette SUMMARY OF THE INVENTION [0017] FIGS. 4A and 4B are diagrams showing the transistor 10C and the photodiode 10D in the circuit of the FIG. 2 respectively in the cross-sectional view and plan view. [0018] FIG. 4A and 4B correspond to the construction of Patent Reference 1 wherein the transistor 10C is formed on a p-type active region 21 defined on a silicon substrate 21 by an STI device isolation region 21I, and a polysilicon gate electrode 23 is formed via a gate insulation film 22 of high quality insulation film typically of a thermal oxide film in correspondence to a p-type channel region 21P. [0019] Further, there is formed an n-type diffusion region 21D that constitutes the photodiode 10D in the silicon substrate 21 at one side of the gate electrode 23, and a diffusion region 21N of n.sup.+-type constituting the floating diffusion region FD is formed at the other side of the gate electrode 23. [0020] In operation, the diffusion region 21D undergoes depletion and photoelectrons are formed in response to irradiation of incident light. The photoelectrons thus formed are then caused to flow to the diffusion region 21N at the time of electric charge transfer operational mode via the channel region 21P of the transfer gate transistor 10C formed right underneath the gate electrode 23 as shown by an arrow in FIG. 4A and cause a change of potential therein. Continue reading... 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