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Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods

Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods description/claims

This application is a divisional of application Ser. No. 11/110,431, filed Apr. 20, 2005, pending, which is a continuation of application Ser. No. 10/732,558, filed Dec. 10, 2003, now U.S. Pat. No. 6,962,867, issued Nov. 8, 2005, which is a divisional of application Ser. No. 10/209,823, filed Jul. 31, 2002, now U.S. Pat. No. 6,800,930, issued Oct. 5, 2004. The disclosure of each of the previously referenced U.S. patent applications and patents referenced is hereby incorporated by reference in its entirety.

1. Field of the Invention

The present invention relates generally to methods and apparatus for assembling one or more semiconductor dice with a substrate. In particular, the present invention relates to methods and apparatus for electrically interconnecting a back side of one or more semiconductor dice to a carrier substrate and various assembly and stacking arrangements implemented using back side electrical interconnections of semiconductor dice.

2. State of the Art

Interconnection and packaging-related issues are among the factors that determine not only the number of circuits that can be integrated on a semiconductor die or “chip,” but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced sizes of transistors and enhanced chip performance. The industry has come to realize that merely having a fast chip will not necessarily result in a fast system; the fast chip must also be supported by equally fast and reliable electrical connections. Essentially, on-chip connections, in conjunction with those of the chip's associated packaging, supply the chip with signals and power, provide signals from the chip and redistribute the tightly spaced or pitched terminals or bond pads of the chip to the terminals of a carrier substrate such as a printed circuit board.

Flip-chip technology, its fabrication and use are well known to those of ordinary skill in the art, as the technology has been in use for over 30 years and continues to develop. A flip-chip semiconductor device conventionally comprises a semiconductor die having an active surface having active integrated circuitry components formed therein and bearing contacts such as bond pads, and an opposing back surface or “back side” devoid of active components or, usually, of any components whatsoever. A dielectric layer, for example, of silicon dioxide or silicon nitride, is formed over the active surface by techniques well known in the art. Apertures are defined in the dielectric layer (also termed a passivation layer), for example, using well-known photolithographic techniques to mask and pattern the dielectric layer and etch the same, for example, with buffered HF to expose the contacts or bond pads on the active surface. The bond pads may be respectively connected to traces of a redistribution layer on the dielectric layer in the form of redistribution lines, i.e., power, ground and signal lines, in a well-known manner, for example, by evaporating or sputtering a layer of aluminum or an alloy thereof over the passivation layer, followed by masking and etching to define the traces. The redistribution lines of the redistribution layer enable the external connections of the semiconductor device provided by the relatively compact arrangement of closely spaced or pitched bond pads to be distributed over a larger surface area with wider spacing or pitch between external connections to higher-level packaging. Solder bumps, or balls, are typically placed upon a pad located at an end of each redistribution line to enable electrical coupling with contact pads or terminals on the higher-level packaging, typically comprising a carrier substrate, such as a printed circuit board. The flip-chip semiconductor device, with the solder bumps on its active surface, is “flipped” and attached face down to a surface of the carrier substrate, with each solder bump on the semiconductor device being positioned on the appropriate contact pad or terminal of the carrier substrate. The assembly of the flip-chip semiconductor device and the carrier substrate is then heated so as to reflow the solder bumps to a molten state and thus connect each bond pad on the semiconductor device through its associated redistribution line and solder bump to an associated contact pad or terminal on the carrier substrate.

Because the flip-chip arrangement does not require leads of a lead frame or other carrier structures coupled to a semiconductor die and extending beyond the lateral periphery thereof it provides a compact assembly in terms of the semiconductor die's “footprint” on the carrier substrate. In other words, the area of the carrier substrate within which the contact pads or terminals are located is, for a given semiconductor die, the same as or less than that occupied by the semiconductor die itself. Furthermore, the contacts on the die, in the form of widely spaced or pitched solder bumps, may be arranged in a so-called “area array” disposed over substantially the entire active surface of the die. Flip-chip bonding, therefore, is well suited for use with dice having large numbers of I/O contacts, in contrast to wire bonding and tape-automated bonding techniques which are more limiting in terms of the number of bond pads which may reasonably and reliably be employed. As a result, the maximum number of I/O contacts and power/ground terminals available can be increased without substantial difficulty, and signal and power/ground interconnections can be more efficiently routed on the semiconductor die. Examples of methods of fabricating semiconductor die assemblies using flip-chip and other techniques are described in U.S. Pat. No. 6,048,753 to Farnworth et al., U.S. Pat. No. 6,018,196 to Noddin, U.S. Pat. No. 6,020,220 to Gilleo et al., U.S. Pat. No. 5,950,304 to Khandros et al., and U.S. Pat. No. 4,833,521 to Early.

As with any conductive line carrying a signal, the redistribution lines for integrated circuits generate electromagnetic and electrostatic fields, or “cross-talk.” These electromagnetic and electrostatic fields may affect the signals carried in adjacent redistribution lines unless some form of compensation is used. Examples of redistribution lines formed over the active circuitry in a flip-chip semiconductor device that disclose methods of limiting cross-talk are illustrated in U.S. Pat. Nos. 5,994,766 and 6,025,647, each to Shenoy et al.

Electromagnetic and electrostatic coupling between redistribution lines, or cross-talk, is undesirable because it increases the impedance of the redistribution lines and may create impedance mismatching and signal delays. Significant factors affecting cross-talk between adjacent redistribution lines include redistribution line length, the distance between the adjacent redistribution lines and the dielectric constant (∈r) of the material between the adjacent redistribution lines. For flip-chip devices, where a large number of bond pads with associated redistribution lines on the active surface are used to carry signals to and from various external connection locations with higher-level packaging for convenient access, impedance can be a significant factor affecting the speed of the system. The location of redistribution lines on the active surface also severely limits the location, size and number of passive circuit elements such as resistors, capacitors and inductors which may be used to compensate for cross-talk or otherwise enhance performance of the packaged semiconductor device without undesirably enlarging the size thereof. Further, such impedance problems affecting the speed of the semiconductor device are only compounded when stacking multiple flip-chip devices.

Therefore, it would be advantageous to prevent cross-talk between adjacent redistribution lines on the active surface of a flip-chip configured semiconductor die while also maintaining a large number of available, widely spaced or pitched I/O terminals and, further, maintaining or even reducing the size of the semiconductor die and associated footprint. It would also be advantageous to provide a flip-chip configured semiconductor die that offers improved stacking capabilities without compounding impedance problems, may be tailored to provide physical and thermal stress relief, and may be configured to provide enhanced resistive, inductive and capacitive electrical characteristics to the packaged semiconductor die.

The present invention relates to methods and apparatus for rerouting redistribution lines from an active surface of a semiconductor device substrate such as a semiconductor die to the back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The rerouted redistribution lines formed on the back surface of the semiconductor substrate may be located, configured and oriented to substantially reduce and even prevent cross-talk in comparison to those which might ordinarily be located on an active surface of the semiconductor substrate and to provide physical and thermal stress relief in assemblies formed with such semiconductor substrate. Further, rerouting such redistribution lines to the back surface of the semiconductor substrate may be used to maintain or even further reduce the footprint of the resulting individual semiconductor die or dice after packaging and provides additional space for additional electrical components on both the active surface and the back surface of the semiconductor substrate.

The present invention includes a semiconductor substrate comprising one or more semiconductor dice. Such semiconductor substrate may be in wafer or other bulk substrate form, an interconnected array of semiconductor dice such as a partial wafer, or a single semiconductor die. In any case, the semiconductor substrate includes an active surface and a back surface with at least one via extending from the active surface to the back surface and having conductive material herein. At least one redistribution line is formed over the back surface of the semiconductor substrate to extend from the conductive material in the at least one via to a predetermined location on the back surface of the semiconductor substrate.

According to one aspect of the present invention, redistribution lines are routed to specific locations on the hack surface of the semiconductor substrate to correspond with an interconnect pattern of another, adjacent substrate such as a carrier substrate for attachment thereto. Additionally, the redistribution lines interconnect with the active circuitry on the active surface of the semiconductor substrate and may also interconnect with additional electronic components as well as with circuitry of other semiconductor substrates stacked thereon or thereunder. Rerouting redistribution lines to the back surface of the semiconductor substrate thus limits the necessary footprint for a semiconductor die and provides improved assembly and stacking configurations that provide physical and thermal stress relief therein.

The electronic components which may be integrated in the back surface of the semiconductor substrate with redistribution lines extending thereto may include, by way of example only, capacitors, inductors, resistors, fuses, controllers and/or additional circuits. Such electronic components may be discrete and configured to remove or reroute thermal and electrical stresses from the active surface to the back surface as well as enabling more even distribution of stresses over the active surface.

According to another aspect of the present invention, the semiconductor substrate may be attached to another substrate, such as a carrier substrate like an interposer or printed circuit board. In particular, the back surface of the semiconductor substrate may be attached to the other substrate with the ends of the redistribution lines distal from the vias positioned and configured to correspond to an interconnection pattern of the other substrate. In this configuration, the resulting assembly provides that the active surface of the semiconductor substrate is facing upward with the back surface attached to the other substrate. Conductive bumps or pillars may be placed between the distal ends of the redistribution lines and the corresponding electronic interconnects such as contact pads or terminals on the other substrate. A dielectric filler material may also be provided between the semiconductor substrate and the other substrate for environmental protection of the conductive interconnections therebetween and enhanced mechanical bonding of the two substrates.

According to the present invention, the redistribution lines on the back surface of a semiconductor substrate enable various embodiments of semiconductor substrate stacking arrangements. The stacking arrangements may include embodiments of active surface-on-active surface attachment, back surface-on-active surface attachment, back surface-on-back surface attachment and active surface-on-back surface attachment of semiconductor substrates. In each of the various stacking arrangements, conductive bumps, studs or pillars may be utilized for electrical interconnection between the stacked semiconductor substrates. An appropriate dielectric filler material may be applied between adjacent semiconductor dice.

In another aspect, the semiconductor substrate of the present invention is fabricated by forming vias in “dead space” on the active surface side of the semiconductor substrate. Such vias may be formed by drilling or laser ablation or any other suitable known method so that the vias are defined by at least one sidewall and a bottom wall. A thin insulative film, such as silicon dioxide, is formed on via wall surfaces, after which a conductive material may be used to fill the vias. Thinning of the semiconductor substrate is then effected by, for example, grinding or etching the back surface of the semiconductor substrate to remove a predetermined depth of semiconductor material. The back surface may then be etched by either a dry or wet etch and/or polished by abrasive polishing techniques such as so-called chemical-mechanical polishing, or “CMP,” to expose the conductive material in the vias. A redistribution layer precursor of metal may ten be deposited and patterned on the back surface of the semiconductor substrate to form redistribution lines. Such patterning may be employed by etching excess portions of the redistribution layer precursor therefrom. The redistribution lines are located, configured and oriented to extend from the conductive material-filled vias to predetermined remote locations on the back surface that will correspond with the interconnection pattern of another substrate. Conductive bumps, such as solder balls, may be disposed or formed on portions of the redistribution lines, typically ends thereof distal from the associated via, to provide an interconnect between the semiconductor substrate and the substrate, such as a carrier substrate, circuit board, or another semiconductor substrate. It is also contemplated that the ends of the vias on the active surface of the substrate may also be used to electrically interconnect the semiconductor substrate to another semiconductor or other type of substrate placed thereover and having appropriately located contacts thereon.

In another aspect of the present invention, the semiconductor substrate of the present invention is mounted to a circuit board in an electronic system, such as a computer system. In the electronic system, the circuit board is electrically connected to a processor device which also electrically communicates with an input device and an output device.

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