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  Semiconductor device with multiple wiring layers and moisture-protective ringUSPTO Application #: 20070044057Title: Semiconductor device with multiple wiring layers and moisture-protective ring Abstract: A semiconductor device with a space-saving design of common power lines shared by a plurality of function macros. An LSI chip has a plurality of wiring layers, a moisture-protective ring, and a plurality of function macros (e.g., I/O macros and I/O macro groups). Each function macro has a VSS power supply terminal that is electrically connected to the moisture-protective ring. This connection enables the moisture-protective ring to function as part of a common VSS power line for the function macros. The proposed architecture reduces the space required for routing VSS power lines inside the moisture-protective ring, thus contributing to space-saving LSI designs. (end of abstract) Agent: Westerman, Hattori, Daniels & Adrian, LLP - Washington, DC, US Inventors: Kazuhiro Kitani, Kenji Hashimoto USPTO Applicaton #: 20070044057 - Class: 716008000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Floorplanning The Patent Description & Claims data below is from USPTO Patent Application 20070044057. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2005-239747, filed on Aug. 22, 2005, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to semiconductor devices and particularly to a semiconductor device having multiple wiring layers and a moisture-protective ring. [0004] 2. Description of the Related Art [0005] Recent years have seen an increasing demand for highly space-saving designs of electrical appliances, particularly in the field of portable devices. Achieving this goal requires smaller, more function-rich large-scale integrated circuit (LSI) products. To integrate many different functions in a single chip, the recent LSI design technology offers a variety of modularized circuit elements, called function macros in a single device, each providing a particular function. LSI chips contain a great number of such function macros. [0006] Each function macro has a power supply terminal for VSS voltage. In some conventional LSI design, VSS power supply terminals of a group of function macros are wired to a common VSS power line. Because of their high-speed operation at low operating voltages, the recent function macros are sensitive to noise on their VSS power supply terminals providing a reference potential for each macro. Electrical noise on a common VSS power line could cause a malfunction of macro circuits connected to that line. Analog function macros are particularly sensitive to such VSS noise. A conventional approach to solve this problem is to isolate the VSS power line of analog function macros from that of digital function macros. [0007] The above issue aside, some existing LSI chips have a moisture-protective ring (see, for example, Japanese Patent Application Publication No. 2-123753 (1990)). Intrusion of water or etchant into an LSI chip would cause damage or degradation to the chip. To prevent this problem, a ring-shaped moisture-protective pattern is fabricated in a region between the scribe lines and I/O (input/output) pads of an LSI chip. Moisture-protective rings often have a multilayer structure to adapt to the multilayer wiring architecture of LSI chips. [0008] A couple of LSI chip designs having a moisture-protective ring are known in the art. FIG. 1 shows a simplified layout of a conventional LSI chip 800 with a moisture-protective ring 801. The moisture-protective ring 801 is formed in an outer region of the LSI chip 800 to protect its function macros and wiring patterns located inside. In FIG. 1, the bold-line boxes represent I/O pads 802. The other boxes are I/O macros 803 and 804 and I/O macro groups 805, 806, 807, and 808, the circuits for input and/or output of signals and VSS. While the LSI chip 800 actually contains other kinds of function macros, FIG. 1 omits them for the sake of simplicity. [0009] More specifically, the double-line boxes indicate VSS I/O macros, and the other boxes represent signal I/O macros. Although not shown in FIG. 1, those I/O macros 803 and 804 are coupled to arithmetic/logic operators, memory modules, or other function macros, as are the I/O macro groups 805 to 808. [0010] For example, the I/O macros 803, 804 and I/O macro group 807 are connected to a particular function macro (not shown), the I/O macro groups 805, 806 are connected to another function macro (not shown). The LSI chip 800 has separate VSS power supply terminals for different kinds of function macros to reduce the noise mentioned above. The same kind of function macros shares VSS power supply terminals through VSS power lines 809, 810, and 811. Each VSS power line 809, 810, and 811 is routed from a VSS I/O macro to the VSS power supply terminal (not shown) of a signal I/O macro. [0011] Some existing LSI chips have a feature of protecting itself from electro-static discharge (ESD). ESD may happen when an electrically conductive object (including a human body) comes close to, or actually comes into contact with, a terminal of an LSI chip, causing damage to some function macro elements in the chip. [0012] FIG. 2 shows a simplified layout of a conventional LSI chip with ESD protection capabilities. The illustrated LSI chip 900 has a similar layout to the aforementioned LSI chip 800 of FIG. 1. A moisture-protective ring 901 runs along the outer region of the LSI chip 900, and I/O pads 902 and I/O macro groups (signal I/O macro, VSS I/O macro) 903, 904, 905, and 966 are placed in the inner region for input and/or output of signals and VSS. FIG. 2 shows some hatched boxes as part of the I/O pads 902 and I/O macro groups 903 to 906. The hatching indicates that those elements share a common VSS potential. [0013] The difference between the LSI chip 800 of FIG. 1 and the ESD-protected LSI chip 900 of FIG. 2 is that the latter LSI chip 900 has bidirectional diodes 903a, 904a, 905a, and 906a to connect VSS I/O macros (depicted as double-line boxes) of each I/O macro group 903 to 906 to their common VSS power line 907. This special structure of the LSI chip 900 provides a bypass for an ESD current, thereby protecting function macro elements from electrostatic damage. Suppose, for example, that an electrostatic voltage is applied to one I/O macro group 903 with respect to the VSS power supply terminal (not shown) of another I/O macro group 906. The resulting discharge current flows from the I/O macro group 903 into the common VSS power line 907 via a bidirectional diode 903a. This current is then routed to the VSS power supply terminal (not shown) of the I/O macro group 906 via another bidirectional diode 906a. The same protection mechanism also applies to ESD on the other I/O macro groups 904 to 906. [0014] However, the above-described conventional LSI chip design consumes a certain amount of chip space to implement common power lines shared by a plurality of function macros. This would restrict the layout of other function macro circuits and the like, thus making it difficult to achieve efficient space usage. SUMMARY OF THE INVENTION [0015] In view of the foregoing, it is an object of the present invention to provide a semiconductor device with a space-saving design of common power lines shared by a plurality of function macros. [0016] To accomplish the above object, the present invention provides a semiconductor device having a plurality of wiring layers, a moisture-protective ring, and a plurality of function macros. Each function macro has a power supply terminal that is electrically connected to the moisture-protective ring. This connection provides a common electrical potential for the function macros. [0017] The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 shows a simplified layout of a conventional LSI chip with a moisture-protective ring. [0019] FIG. 2 shows a simplified layout of a conventional LSI chip with ESD protection capabilities. [0020] FIG. 3 shows a simplified layout of an LSI chip according to a first embodiment of the present invention. Continue reading... Full patent description for Semiconductor device with multiple wiring layers and moisture-protective ring Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device with multiple wiring layers and moisture-protective ring patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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